| H A D | ar9003_eeprom.c | 4523 u8 *targetPowerValT2, ar9003_hw_get_legacy_target_powers()
4526 targetPowerValT2[ALL_TARGET_LEGACY_6_24] = ar9003_hw_get_legacy_target_powers()
4529 targetPowerValT2[ALL_TARGET_LEGACY_36] = ar9003_hw_get_legacy_target_powers()
4532 targetPowerValT2[ALL_TARGET_LEGACY_48] = ar9003_hw_get_legacy_target_powers()
4535 targetPowerValT2[ALL_TARGET_LEGACY_54] = ar9003_hw_get_legacy_target_powers()
4541 u8 *targetPowerValT2) ar9003_hw_get_cck_target_powers()
4543 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] = ar9003_hw_get_cck_target_powers()
4546 targetPowerValT2[ALL_TARGET_LEGACY_5S] = ar9003_hw_get_cck_target_powers()
4548 targetPowerValT2[ALL_TARGET_LEGACY_11L] = ar9003_hw_get_cck_target_powers()
4550 targetPowerValT2[ALL_TARGET_LEGACY_11S] = ar9003_hw_get_cck_target_powers()
4555 u8 *targetPowerValT2, bool is2GHz) ar9003_hw_get_ht20_target_powers()
4557 targetPowerValT2[ALL_TARGET_HT20_0_8_16] = ar9003_hw_get_ht20_target_powers()
4560 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] = ar9003_hw_get_ht20_target_powers()
4563 targetPowerValT2[ALL_TARGET_HT20_4] = ar9003_hw_get_ht20_target_powers()
4566 targetPowerValT2[ALL_TARGET_HT20_5] = ar9003_hw_get_ht20_target_powers()
4569 targetPowerValT2[ALL_TARGET_HT20_6] = ar9003_hw_get_ht20_target_powers()
4572 targetPowerValT2[ALL_TARGET_HT20_7] = ar9003_hw_get_ht20_target_powers()
4575 targetPowerValT2[ALL_TARGET_HT20_12] = ar9003_hw_get_ht20_target_powers()
4578 targetPowerValT2[ALL_TARGET_HT20_13] = ar9003_hw_get_ht20_target_powers()
4581 targetPowerValT2[ALL_TARGET_HT20_14] = ar9003_hw_get_ht20_target_powers()
4584 targetPowerValT2[ALL_TARGET_HT20_15] = ar9003_hw_get_ht20_target_powers()
4587 targetPowerValT2[ALL_TARGET_HT20_20] = ar9003_hw_get_ht20_target_powers()
4590 targetPowerValT2[ALL_TARGET_HT20_21] = ar9003_hw_get_ht20_target_powers()
4593 targetPowerValT2[ALL_TARGET_HT20_22] = ar9003_hw_get_ht20_target_powers()
4596 targetPowerValT2[ALL_TARGET_HT20_23] = ar9003_hw_get_ht20_target_powers()
4603 u8 *targetPowerValT2, ar9003_hw_get_ht40_target_powers()
4609 targetPowerValT2[ALL_TARGET_HT40_0_8_16] = ar9003_hw_get_ht40_target_powers()
4612 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] = ar9003_hw_get_ht40_target_powers()
4616 targetPowerValT2[ALL_TARGET_HT40_4] = ar9003_hw_get_ht40_target_powers()
4619 targetPowerValT2[ALL_TARGET_HT40_5] = ar9003_hw_get_ht40_target_powers()
4622 targetPowerValT2[ALL_TARGET_HT40_6] = ar9003_hw_get_ht40_target_powers()
4625 targetPowerValT2[ALL_TARGET_HT40_7] = ar9003_hw_get_ht40_target_powers()
4628 targetPowerValT2[ALL_TARGET_HT40_12] = ar9003_hw_get_ht40_target_powers()
4631 targetPowerValT2[ALL_TARGET_HT40_13] = ar9003_hw_get_ht40_target_powers()
4634 targetPowerValT2[ALL_TARGET_HT40_14] = ar9003_hw_get_ht40_target_powers()
4637 targetPowerValT2[ALL_TARGET_HT40_15] = ar9003_hw_get_ht40_target_powers()
4640 targetPowerValT2[ALL_TARGET_HT40_20] = ar9003_hw_get_ht40_target_powers()
4643 targetPowerValT2[ALL_TARGET_HT40_21] = ar9003_hw_get_ht40_target_powers()
4646 targetPowerValT2[ALL_TARGET_HT40_22] = ar9003_hw_get_ht40_target_powers()
4649 targetPowerValT2[ALL_TARGET_HT40_23] = ar9003_hw_get_ht40_target_powers()
4656 u8 *targetPowerValT2) ar9003_hw_get_target_power_eeprom()
4664 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2); ar9003_hw_get_target_power_eeprom()
4666 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz); ar9003_hw_get_target_power_eeprom()
4667 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz); ar9003_hw_get_target_power_eeprom()
4670 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2, ar9003_hw_get_target_power_eeprom()
4675 i, targetPowerValT2[i]); ar9003_hw_get_target_power_eeprom()
5303 u8 *targetPowerValT2) ar9003_paprd_set_txpower()
5325 ah->paprd_target_power = targetPowerValT2[i]; ar9003_paprd_set_txpower()
5337 u8 targetPowerValT2[ar9300RateSize]; ath9k_hw_ar9300_set_txpower() local
5343 memset(targetPowerValT2, 0 , sizeof(targetPowerValT2)); ath9k_hw_ar9300_set_txpower()
5348 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2); ath9k_hw_ar9300_set_txpower()
5369 memcpy(target_power_val_t2_eep, targetPowerValT2, ath9k_hw_ar9300_set_txpower()
5370 sizeof(targetPowerValT2)); ath9k_hw_ar9300_set_txpower()
5374 if (targetPowerValT2[pwr_idx] && ath9k_hw_ar9300_set_txpower()
5375 targetPowerValT2[pwr_idx] == ath9k_hw_ar9300_set_txpower()
5377 targetPowerValT2[pwr_idx] -= ath9k_hw_ar9300_set_txpower()
5382 memcpy(target_power_val_t2_eep, targetPowerValT2, ath9k_hw_ar9300_set_txpower()
5383 sizeof(targetPowerValT2)); ath9k_hw_ar9300_set_txpower()
5387 targetPowerValT2, cfgCtl, ath9k_hw_ar9300_set_txpower()
5391 memcpy(targetPowerValT2_tpc, targetPowerValT2, ath9k_hw_ar9300_set_txpower()
5392 sizeof(targetPowerValT2)); ath9k_hw_ar9300_set_txpower()
5397 (abs(targetPowerValT2[i] - ath9k_hw_ar9300_set_txpower()
5409 if (targetPowerValT2[i] > regulatory->max_power_level) ath9k_hw_ar9300_set_txpower()
5410 regulatory->max_power_level = targetPowerValT2[i]; ath9k_hw_ar9300_set_txpower()
5420 i, targetPowerValT2[i]); ath9k_hw_ar9300_set_txpower()
5424 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); ath9k_hw_ar9300_set_txpower()
5426 ar9003_paprd_set_txpower(ah, chan, targetPowerValT2); ath9k_hw_ar9300_set_txpower()
5428 ar9003_hw_selfgen_tpc_txpower(ah, chan, targetPowerValT2); ath9k_hw_ar9300_set_txpower()
4522 ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq, u8 *targetPowerValT2, bool is2GHz) ar9003_hw_get_legacy_target_powers() argument
4540 ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq, u8 *targetPowerValT2) ar9003_hw_get_cck_target_powers() argument
4554 ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq, u8 *targetPowerValT2, bool is2GHz) ar9003_hw_get_ht20_target_powers() argument
4601 ar9003_hw_get_ht40_target_powers(struct ath_hw *ah, u16 freq, u8 *targetPowerValT2, bool is2GHz) ar9003_hw_get_ht40_target_powers() argument
4654 ar9003_hw_get_target_power_eeprom(struct ath_hw *ah, struct ath9k_channel *chan, u8 *targetPowerValT2) ar9003_hw_get_target_power_eeprom() argument
5301 ar9003_paprd_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u8 *targetPowerValT2) ar9003_paprd_set_txpower() argument
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