Searched refs:subc (Results 1 - 25 of 25) sorted by relevance

/linux-4.1.27/arch/c6x/lib/
H A Dremu.S57 || [B1] subc .l1x A4,B4,A4
60 [B1] subc .l1x A4,B4,A4
63 [B1] subc .l1x A4,B4,A4
65 [B1] subc .l1x A4,B4,A4
67 [B1] subc .l1x A4,B4,A4
69 [B1] subc .l1x A4,B4,A4
71 [B1] subc .l1x A4,B4,A4
76 [B1] subc .l1x A4,B4,A4
78 [B1] subc .l1x A4,B4,A4
H A Ddivremu.S22 ;; We use a series of up to 31 subc instructions. First, we find
25 ;; to the, and the number of times we have to execute subc.
52 || [b1] subc .l1x A4,B4,A4
54 [b1] subc .l1x A4,B4,A4
60 || [b1] subc .l1x A4,B4,A4
62 [b1] subc .l1x A4,B4,A4
65 [b1] subc .l1x A4,B4,A4
67 [b1] subc .l1x A4,B4,A4
69 [b1] subc .l1x A4,B4,A4
71 [b1] subc .l1x A4,B4,A4
73 [b1] subc .l1x A4,B4,A4
H A Ddivu.S39 ;; We use a series of up to 31 subc instructions. First, we find
42 ;; to the, and the number of times we have to execute subc.
64 || [B1] subc .l1x A4,B4,A4
66 [B1] subc .l1x A4,B4,A4
72 || [B1] subc .l1x A4,B4,A4
74 [B1] subc .l1x A4,B4,A4
77 [B1] subc .l1x A4,B4,A4
79 [B1] subc .l1x A4,B4,A4
81 [B1] subc .l1x A4,B4,A4
83 [B1] subc .l1x A4,B4,A4
85 [B1] subc .l1x A4,B4,A4
/linux-4.1.27/arch/mn10300/lib/
H A D__ucmpdi2.S31 subc a1,d1 # may clear Z, never sets it
38 subc d0,d0 # -1 if LE, 0 if GE
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv50.h22 u32 subc[8]; member in struct:nv50_fifo_chan
H A Dnv04.c361 const int subc = (addr >> 13) & 0x7; nv04_fifo_swmthd() local
380 engine = 0x0000000f << (subc * 4); nv04_fifo_swmthd()
381 chan->subc[subc] = data; nv04_fifo_swmthd()
391 if (unlikely(((engine >> (subc * 4)) & 0xf) != 0)) nv04_fifo_swmthd()
394 bind = nvkm_namedb_get(nv_namedb(chan), chan->subc[subc]); nv04_fifo_swmthd()
434 "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", nv04_fifo_cache_error()
H A Dnv04.h156 u32 subc[8]; member in struct:nv04_fifo_chan
H A Dgf100.c687 u32 subc = (addr & 0x00070000) >> 16; gf100_fifo_intr_pbdma() local
701 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", gf100_fifo_intr_pbdma()
704 subc, mthd, data); gf100_fifo_intr_pbdma()
H A Dgk104.c829 u32 subc = (addr & 0x00070000) >> 16; gk104_fifo_intr_pbdma_0() local
844 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", gk104_fifo_intr_pbdma_0()
847 subc, mthd, data); gk104_fifo_intr_pbdma_0()
/linux-4.1.27/drivers/media/i2c/
H A Dadv7175.c157 0x02, 0x0c, /* subc. freq. */
158 0x03, 0x8c, /* subc. freq. */
159 0x04, 0x79, /* subc. freq. */
160 0x05, 0x26, /* subc. freq. */
161 0x06, 0x40, /* subc. phase */
179 0x02, 0x0c, /* subc. freq. */
180 0x03, 0x8c, /* subc. freq. */
181 0x04, 0x79, /* subc. freq. */
182 0x05, 0x26, /* subc. freq. */
183 0x06, 0x40, /* subc. phase */
189 0x02, 0x55, /* subc. freq. */
190 0x03, 0x55, /* subc. freq. */
191 0x04, 0x55, /* subc. freq. */
192 0x05, 0x25, /* subc. freq. */
193 0x06, 0x1a, /* subc. phase */
/linux-4.1.27/drivers/gpu/drm/nouveau/
H A Dnouveau_dma.h111 BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) BEGIN_NV04() argument
113 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); BEGIN_NV04()
117 BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) BEGIN_NI04() argument
119 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); BEGIN_NI04()
123 BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) BEGIN_NVC0() argument
125 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); BEGIN_NVC0()
129 BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) BEGIN_NIC0() argument
131 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); BEGIN_NIC0()
135 BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) BEGIN_IMC0() argument
137 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); BEGIN_IMC0()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgt215.c90 u32 subc = (addr & 0x3800) >> 11; gt215_ce_intr() local
100 pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", gt215_ce_intr()
101 chid, inst << 12, nvkm_client_name(engctx), subc, gt215_ce_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A Dg98.c88 u32 subc = (addr & 0x3800) >> 11; g98_sec_intr() local
98 pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", g98_sec_intr()
100 subc, mthd, data); g98_sec_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c598 u32 subc = (addr & 0x00070000) >> 16; nv50_gr_trap_handler() local
608 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", nv50_gr_trap_handler()
610 nvkm_client_name(engctx), subc, nv50_gr_trap_handler()
625 u32 subc = (addr & 0x00070000) >> 16; nv50_gr_trap_handler() local
633 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", nv50_gr_trap_handler()
635 nvkm_client_name(engctx), subc, nv50_gr_trap_handler()
794 u32 subc = (addr & 0x00070000) >> 16; nv50_gr_intr() local
837 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", nv50_gr_intr()
839 subc, class, mthd, data); nv50_gr_intr()
H A Dnv20.c200 u32 subc = (addr & 0x00070000) >> 16; nv20_gr_intr() local
203 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; nv20_gr_intr()
228 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", nv20_gr_intr()
229 chid, nvkm_client_name(engctx), subc, class, mthd, nv20_gr_intr()
H A Dgf100.c1076 u32 subc = (addr & 0x00070000) >> 16; gf100_gr_ctxctl_isr() local
1080 nv_error(priv, "FECS MTHD subc %d class 0x%04x " gf100_gr_ctxctl_isr()
1082 subc, class, mthd, data); gf100_gr_ctxctl_isr()
1117 u32 subc = (addr & 0x00070000) >> 16; gf100_gr_intr() local
1123 if (nv_device(priv)->card_type < NV_E0 || subc < 4) gf100_gr_intr()
1124 class = nv_rd32(priv, 0x404200 + (subc * 4)); gf100_gr_intr()
1144 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", gf100_gr_intr()
1146 subc, class, mthd, data); gf100_gr_intr()
1155 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", gf100_gr_intr()
1156 chid, inst << 12, nvkm_client_name(engctx), subc, gf100_gr_intr()
1165 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", gf100_gr_intr()
1166 chid, inst << 12, nvkm_client_name(engctx), subc, gf100_gr_intr()
H A Dnv40.c296 u32 subc = (addr & 0x00070000) >> 16; nv40_gr_intr() local
299 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff; nv40_gr_intr()
331 "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", nv40_gr_intr()
332 chid, inst << 4, nvkm_client_name(engctx), subc, nv40_gr_intr()
H A Dnv04.c450 int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; nv04_gr_set_ctx1() local
459 nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); nv04_gr_set_ctx1()
1261 u32 subc = (addr & 0x0000e000) >> 13; nv04_gr_intr() local
1264 u32 class = nv_rd32(priv, 0x400180 + subc * 4) & 0xff; nv04_gr_intr()
1302 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", nv04_gr_intr()
1303 chid, nvkm_client_name(chan), subc, class, mthd, nv04_gr_intr()
H A Dnv10.c1163 u32 subc = (addr & 0x00070000) >> 16; nv10_gr_intr() local
1166 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; nv10_gr_intr()
1203 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", nv10_gr_intr()
1204 chid, nvkm_client_name(chan), subc, class, mthd, nv10_gr_intr()
/linux-4.1.27/drivers/gpu/drm/i2c/
H A Dch7006_mode.c106 subc, scale, scale_mask, norm_mask, e_hd, e_vd) { \
128 .subc_coeff = subc * fixed1, \
136 subc, scale, scale_mask, norm_mask) \
137 __MODE(f, hd, vd, ht, vt, hsynp, vsynp, subc, scale, \
/linux-4.1.27/arch/sh/lib/
H A Dashiftrt.S80 subc r4,r4
H A Dashrsi3.S112 subc r0,r0
/linux-4.1.27/lib/mpi/
H A Dlonglong.h125 "subc %0,%2,%3" \
462 "subc %5,%4,%1\n" \
463 "subc %3,%2,%0" \
/linux-4.1.27/arch/sh/kernel/
H A Ddisassemble.c215 {"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}},
/linux-4.1.27/arch/powerpc/xmon/
H A Dppc-opc.c3363 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3366 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },

Completed in 518 milliseconds