Searched refs:sparc_pmu (Results 1 - 1 of 1) sorted by relevance

/linux-4.1.27/arch/sparc/kernel/
H A Dperf_event.c155 struct sparc_pmu { struct
319 static const struct sparc_pmu ultra3_pmu = {
457 static const struct sparc_pmu niagara1_pmu = {
592 static const struct sparc_pmu niagara2_pmu = {
749 static const struct sparc_pmu niagara4_pmu = {
779 static const struct sparc_pmu sparc_m7_pmu = {
802 static const struct sparc_pmu *sparc_pmu __read_mostly;
807 event_id <<= sparc_pmu->upper_shift; event_encoding()
809 event_id <<= sparc_pmu->lower_shift; event_encoding()
815 return event_encoding(sparc_pmu->event_mask, idx); mask_for_index()
821 sparc_pmu->upper_nop : nop_for_index()
822 sparc_pmu->lower_nop, idx); nop_for_index()
830 if (sparc_pmu->num_pcrs > 1) sparc_pmu_enable_event()
850 if (sparc_pmu->num_pcrs > 1) sparc_pmu_disable_event()
870 new_raw_count = sparc_pmu->read_pmc(idx); sparc_perf_event_update()
910 sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff); sparc_perf_event_set_period()
1009 if (sparc_pmu->num_pcrs == 1) { update_pcrs_for_enable()
1030 for (i = 0; i < sparc_pmu->num_pcrs; i++) sparc_pmu_enable()
1045 for (i = 0; i < sparc_pmu->num_pcrs; i++) { sparc_pmu_disable()
1048 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit | sparc_pmu_disable()
1049 sparc_pmu->hv_bit | sparc_pmu->irq_bit); sparc_pmu_disable()
1152 for (i = 0; i < sparc_pmu->num_pcrs; i++) perf_stop_nmi_watchdog()
1186 if (!sparc_pmu->cache_map) sparc_map_cache_event()
1201 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]); sparc_map_cache_event()
1239 if (n_ev > sparc_pmu->max_hw_events) sparc_check_constraints()
1242 if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) { sparc_check_constraints()
1305 if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME)) check_excludes()
1366 if (n0 >= sparc_pmu->max_hw_events) sparc_pmu_add()
1419 if (attr->config >= sparc_pmu->max_events) sparc_pmu_event_init()
1421 pmap = sparc_pmu->event_map(attr->config); sparc_pmu_event_init()
1450 hwc->config_base = sparc_pmu->irq_bit; sparc_pmu_event_init()
1452 hwc->config_base |= sparc_pmu->user_bit; sparc_pmu_event_init()
1454 hwc->config_base |= sparc_pmu->priv_bit; sparc_pmu_event_init()
1456 hwc->config_base |= sparc_pmu->hv_bit; sparc_pmu_event_init()
1461 sparc_pmu->max_hw_events - 1, sparc_pmu_event_init()
1528 if (!sparc_pmu) sparc_pmu_commit_txn()
1562 if (!sparc_pmu) perf_event_print_debug()
1570 for (i = 0; i < sparc_pmu->num_pcrs; i++) perf_event_print_debug()
1573 for (i = 0; i < sparc_pmu->num_pic_regs; i++) perf_event_print_debug()
1611 if (sparc_pmu->irq_bit && perf_event_nmi_handler()
1612 sparc_pmu->num_pcrs == 1) perf_event_nmi_handler()
1621 if (sparc_pmu->irq_bit && perf_event_nmi_handler()
1622 sparc_pmu->num_pcrs > 1) perf_event_nmi_handler()
1651 sparc_pmu = &ultra3_pmu; supported_pmu()
1655 sparc_pmu = &niagara1_pmu; supported_pmu()
1660 sparc_pmu = &niagara2_pmu; supported_pmu()
1665 sparc_pmu = &niagara4_pmu; supported_pmu()
1669 sparc_pmu = &sparc_m7_pmu; supported_pmu()

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