Searched refs:socfpgaclk (Results 1 – 3 of 3) sorted by relevance
31 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local34 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()35 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()37 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()38 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()39 val &= div_mask(socfpgaclk->width); in clk_periclk_recalc_rate()42 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); in clk_periclk_recalc_rate()
106 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate() local109 if (socfpgaclk->fixed_div) in socfpga_clk_recalc_rate()110 div = socfpgaclk->fixed_div; in socfpga_clk_recalc_rate()111 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()112 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()113 val &= div_mask(socfpgaclk->width); in socfpga_clk_recalc_rate()115 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()126 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local132 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()140 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
52 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local57 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()72 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local74 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()