Searched refs:read_aux_reg (Results 1 – 10 of 10) sorted by relevance
80 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_read_counter()82 result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32; in arc_pmu_read_counter()83 result |= read_aux_reg(ARC_REG_PCT_SNAPL); in arc_pmu_read_counter()171 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_enable()179 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_disable()309 cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0); in arc_pmu_device_probe()310 cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1); in arc_pmu_device_probe()
54 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); in read_arc_build_cfg_regs()61 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ in read_arc_build_cfg_regs()62 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ in read_arc_build_cfg_regs()63 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ in read_arc_build_cfg_regs()64 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; in read_arc_build_cfg_regs()65 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ in read_arc_build_cfg_regs()77 bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR); in read_arc_build_cfg_regs()84 bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR); in read_arc_build_cfg_regs()
62 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_mask()71 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_unmask()
131 return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); in arc_counter_read()
123 idx = read_aux_reg(ARC_REG_TLBINDEX); in tlb_entry_lkup()171 idx = read_aux_reg(ARC_REG_TLBINDEX); in utlb_invalidate()488 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff; in create_tlb()585 tmp = read_aux_reg(ARC_REG_MMU_BCR); in read_decode_mmu_bcr()693 write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID)); in do_tlb_overlap_fault()703 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()704 pd1[way] = read_aux_reg(ARC_REG_TLBPD1); in do_tlb_overlap_fault()768 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff; in tlb_paranoid_check()
279 reg = read_aux_reg(ARC_REG_DC_CTRL); in __before_dc_op()290 while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS); in __after_dc_op()403 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ in __ic_entire_inv()
109 #define read_aux_reg(reg) __builtin_arc_lr(reg) macro117 #define read_aux_reg(reg) \ macro165 tmp = read_aux_reg(reg); \
343 pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0); \
61 #define IDU_GET_PARAM() read_aux_reg(ARC_AUX_IDU_REG_PARAM)
48 uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR); in get_hw_config_num_irq()