/linux-4.1.27/drivers/crypto/qce/ |
H A D | core.c | 36 static void qce_unregister_algs(struct qce_device *qce) qce_unregister_algs() argument 43 ops->unregister_algs(qce); qce_unregister_algs() 47 static int qce_register_algs(struct qce_device *qce) qce_register_algs() argument 54 ret = ops->register_algs(qce); qce_register_algs() 79 static int qce_handle_queue(struct qce_device *qce, qce_handle_queue() argument 86 spin_lock_irqsave(&qce->lock, flags); qce_handle_queue() 89 ret = crypto_enqueue_request(&qce->queue, req); qce_handle_queue() 92 if (qce->req) { qce_handle_queue() 93 spin_unlock_irqrestore(&qce->lock, flags); qce_handle_queue() 97 backlog = crypto_get_backlog(&qce->queue); qce_handle_queue() 98 async_req = crypto_dequeue_request(&qce->queue); qce_handle_queue() 100 qce->req = async_req; qce_handle_queue() 102 spin_unlock_irqrestore(&qce->lock, flags); qce_handle_queue() 108 spin_lock_bh(&qce->lock); qce_handle_queue() 110 spin_unlock_bh(&qce->lock); qce_handle_queue() 115 qce->result = err; qce_handle_queue() 116 tasklet_schedule(&qce->done_tasklet); qce_handle_queue() 124 struct qce_device *qce = (struct qce_device *)data; qce_tasklet_req_done() local 128 spin_lock_irqsave(&qce->lock, flags); qce_tasklet_req_done() 129 req = qce->req; qce_tasklet_req_done() 130 qce->req = NULL; qce_tasklet_req_done() 131 spin_unlock_irqrestore(&qce->lock, flags); qce_tasklet_req_done() 134 req->complete(req, qce->result); qce_tasklet_req_done() 136 qce_handle_queue(qce, NULL); qce_tasklet_req_done() 139 static int qce_async_request_enqueue(struct qce_device *qce, qce_async_request_enqueue() argument 142 return qce_handle_queue(qce, req); qce_async_request_enqueue() 145 static void qce_async_request_done(struct qce_device *qce, int ret) qce_async_request_done() argument 147 qce->result = ret; qce_async_request_done() 148 tasklet_schedule(&qce->done_tasklet); qce_async_request_done() 151 static int qce_check_version(struct qce_device *qce) qce_check_version() argument 155 qce_get_version(qce, &major, &minor, &step); qce_check_version() 164 qce->burst_size = QCE_BAM_BURST_SIZE; qce_check_version() 165 qce->pipe_pair_id = 1; qce_check_version() 167 dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n", qce_check_version() 176 struct qce_device *qce; qce_crypto_probe() local 180 qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); qce_crypto_probe() 181 if (!qce) qce_crypto_probe() 184 qce->dev = dev; qce_crypto_probe() 185 platform_set_drvdata(pdev, qce); qce_crypto_probe() 188 qce->base = devm_ioremap_resource(&pdev->dev, res); qce_crypto_probe() 189 if (IS_ERR(qce->base)) qce_crypto_probe() 190 return PTR_ERR(qce->base); qce_crypto_probe() 196 qce->core = devm_clk_get(qce->dev, "core"); qce_crypto_probe() 197 if (IS_ERR(qce->core)) qce_crypto_probe() 198 return PTR_ERR(qce->core); qce_crypto_probe() 200 qce->iface = devm_clk_get(qce->dev, "iface"); qce_crypto_probe() 201 if (IS_ERR(qce->iface)) qce_crypto_probe() 202 return PTR_ERR(qce->iface); qce_crypto_probe() 204 qce->bus = devm_clk_get(qce->dev, "bus"); qce_crypto_probe() 205 if (IS_ERR(qce->bus)) qce_crypto_probe() 206 return PTR_ERR(qce->bus); qce_crypto_probe() 208 ret = clk_prepare_enable(qce->core); qce_crypto_probe() 212 ret = clk_prepare_enable(qce->iface); qce_crypto_probe() 216 ret = clk_prepare_enable(qce->bus); qce_crypto_probe() 220 ret = qce_dma_request(qce->dev, &qce->dma); qce_crypto_probe() 224 ret = qce_check_version(qce); qce_crypto_probe() 228 spin_lock_init(&qce->lock); qce_crypto_probe() 229 tasklet_init(&qce->done_tasklet, qce_tasklet_req_done, qce_crypto_probe() 230 (unsigned long)qce); qce_crypto_probe() 231 crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH); qce_crypto_probe() 233 qce->async_req_enqueue = qce_async_request_enqueue; qce_crypto_probe() 234 qce->async_req_done = qce_async_request_done; qce_crypto_probe() 236 ret = qce_register_algs(qce); qce_crypto_probe() 243 qce_dma_release(&qce->dma); qce_crypto_probe() 245 clk_disable_unprepare(qce->bus); qce_crypto_probe() 247 clk_disable_unprepare(qce->iface); qce_crypto_probe() 249 clk_disable_unprepare(qce->core); qce_crypto_probe() 255 struct qce_device *qce = platform_get_drvdata(pdev); qce_crypto_remove() local 257 tasklet_kill(&qce->done_tasklet); qce_crypto_remove() 258 qce_unregister_algs(qce); qce_crypto_remove() 259 qce_dma_release(&qce->dma); qce_crypto_remove() 260 clk_disable_unprepare(qce->bus); qce_crypto_remove() 261 clk_disable_unprepare(qce->iface); qce_crypto_remove() 262 clk_disable_unprepare(qce->core); qce_crypto_remove()
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H A D | common.c | 28 static inline u32 qce_read(struct qce_device *qce, u32 offset) qce_read() argument 30 return readl(qce->base + offset); qce_read() 33 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) qce_write() argument 35 writel(val, qce->base + offset); qce_write() 38 static inline void qce_write_array(struct qce_device *qce, u32 offset, qce_write_array() argument 44 qce_write(qce, offset + i * sizeof(u32), val[i]); qce_write_array() 48 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len) qce_clear_array() argument 53 qce_write(qce, offset + i * sizeof(u32), 0); qce_clear_array() 148 static u32 qce_config_reg(struct qce_device *qce, int little) qce_config_reg() argument 150 u32 beats = (qce->burst_size >> 3) - 1; qce_config_reg() 151 u32 pipe_pair = qce->pipe_pair_id; qce_config_reg() 197 static void qce_xtskey(struct qce_device *qce, const u8 *enckey, qce_xtskey() argument 206 qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen); qce_xtskey() 210 qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize); qce_xtskey() 213 static void qce_setup_config(struct qce_device *qce) qce_setup_config() argument 218 config = qce_config_reg(qce, 0); qce_setup_config() 221 qce_write(qce, REG_STATUS, 0); qce_setup_config() 222 qce_write(qce, REG_CONFIG, config); qce_setup_config() 225 static inline void qce_crypto_go(struct qce_device *qce) qce_crypto_go() argument 227 qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); qce_crypto_go() 237 struct qce_device *qce = tmpl->qce; qce_setup_regs_ahash() local 249 qce_setup_config(qce); qce_setup_regs_ahash() 252 qce_write(qce, REG_AUTH_SEG_CFG, 0); qce_setup_regs_ahash() 253 qce_write(qce, REG_ENCR_SEG_CFG, 0); qce_setup_regs_ahash() 254 qce_write(qce, REG_ENCR_SEG_SIZE, 0); qce_setup_regs_ahash() 255 qce_clear_array(qce, REG_AUTH_IV0, 16); qce_setup_regs_ahash() 256 qce_clear_array(qce, REG_AUTH_KEY0, 16); qce_setup_regs_ahash() 257 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); qce_setup_regs_ahash() 266 qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey, qce_setup_regs_ahash() 279 qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words); qce_setup_regs_ahash() 282 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); qce_setup_regs_ahash() 284 qce_write_array(qce, REG_AUTH_BYTECNT0, qce_setup_regs_ahash() 300 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); qce_setup_regs_ahash() 301 qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes); qce_setup_regs_ahash() 302 qce_write(qce, REG_AUTH_SEG_START, 0); qce_setup_regs_ahash() 303 qce_write(qce, REG_ENCR_SEG_CFG, 0); qce_setup_regs_ahash() 304 qce_write(qce, REG_SEG_SIZE, req->nbytes); qce_setup_regs_ahash() 307 config = qce_config_reg(qce, 1); qce_setup_regs_ahash() 308 qce_write(qce, REG_CONFIG, config); qce_setup_regs_ahash() 310 qce_crypto_go(qce); qce_setup_regs_ahash() 322 struct qce_device *qce = tmpl->qce; qce_setup_regs_ablkcipher() local 331 qce_setup_config(qce); qce_setup_regs_ablkcipher() 341 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); qce_setup_regs_ablkcipher() 353 qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen, qce_setup_regs_ablkcipher() 360 qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words); qce_setup_regs_ablkcipher() 368 qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words); qce_setup_regs_ablkcipher() 374 qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); qce_setup_regs_ablkcipher() 375 qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); qce_setup_regs_ablkcipher() 376 qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff); qce_setup_regs_ablkcipher() 379 qce_write(qce, REG_CNTR_MASK, ~0); qce_setup_regs_ablkcipher() 380 qce_write(qce, REG_CNTR_MASK0, ~0); qce_setup_regs_ablkcipher() 381 qce_write(qce, REG_CNTR_MASK1, ~0); qce_setup_regs_ablkcipher() 382 qce_write(qce, REG_CNTR_MASK2, ~0); qce_setup_regs_ablkcipher() 385 qce_write(qce, REG_SEG_SIZE, totallen); qce_setup_regs_ablkcipher() 388 config = qce_config_reg(qce, 1); qce_setup_regs_ablkcipher() 389 qce_write(qce, REG_CONFIG, config); qce_setup_regs_ablkcipher() 391 qce_crypto_go(qce); qce_setup_regs_ablkcipher() 412 int qce_check_status(struct qce_device *qce, u32 *status) qce_check_status() argument 416 *status = qce_read(qce, REG_STATUS); qce_check_status() 430 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step) qce_get_version() argument 434 val = qce_read(qce, REG_VERSION); qce_get_version()
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H A D | ablkcipher.c | 31 struct qce_device *qce = tmpl->qce; qce_ablkcipher_done() local 41 error = qce_dma_terminate_all(&qce->dma); qce_ablkcipher_done() 43 dev_dbg(qce->dev, "ablkcipher dma termination error (%d)\n", qce_ablkcipher_done() 47 qce_unmapsg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src, qce_ablkcipher_done() 49 qce_unmapsg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst, qce_ablkcipher_done() 54 error = qce_check_status(qce, &status); qce_ablkcipher_done() 56 dev_dbg(qce->dev, "ablkcipher operation error (%x)\n", status); qce_ablkcipher_done() 58 qce->async_req_done(tmpl->qce, error); qce_ablkcipher_done() 68 struct qce_device *qce = tmpl->qce; qce_ablkcipher_async_req_handle() local 102 sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); qce_ablkcipher_async_req_handle() 119 ret = qce_mapsg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst, qce_ablkcipher_async_req_handle() 125 ret = qce_mapsg(qce->dev, req->src, rctx->src_nents, dir_src, qce_ablkcipher_async_req_handle() 134 ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents, qce_ablkcipher_async_req_handle() 140 qce_dma_issue_pending(&qce->dma); qce_ablkcipher_async_req_handle() 149 qce_dma_terminate_all(&qce->dma); qce_ablkcipher_async_req_handle() 152 qce_unmapsg(qce->dev, req->src, rctx->src_nents, dir_src, qce_ablkcipher_async_req_handle() 155 qce_unmapsg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst, qce_ablkcipher_async_req_handle() 224 return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base); qce_ablkcipher_crypt() 275 .drv_name = "ecb-aes-qce", 284 .drv_name = "cbc-aes-qce", 293 .drv_name = "ctr-aes-qce", 302 .drv_name = "xts-aes-qce", 311 .drv_name = "ecb-des-qce", 320 .drv_name = "cbc-des-qce", 329 .drv_name = "ecb-3des-qce", 338 .drv_name = "cbc-3des-qce", 347 struct qce_device *qce) qce_ablkcipher_register_one() 385 tmpl->qce = qce; qce_ablkcipher_register_one() 390 dev_err(qce->dev, "%s registration failed\n", alg->cra_name); qce_ablkcipher_register_one() 395 dev_dbg(qce->dev, "%s is registered\n", alg->cra_name); qce_ablkcipher_register_one() 399 static void qce_ablkcipher_unregister(struct qce_device *qce) qce_ablkcipher_unregister() argument 410 static int qce_ablkcipher_register(struct qce_device *qce) qce_ablkcipher_register() argument 415 ret = qce_ablkcipher_register_one(&ablkcipher_def[i], qce); qce_ablkcipher_register() 422 qce_ablkcipher_unregister(qce); qce_ablkcipher_register() 346 qce_ablkcipher_register_one(const struct qce_ablkcipher_def *def, struct qce_device *qce) qce_ablkcipher_register_one() argument
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H A D | sha.c | 44 struct qce_device *qce = tmpl->qce; qce_ahash_done() local 45 struct qce_result_dump *result = qce->dma.result_buf; qce_ahash_done() 50 error = qce_dma_terminate_all(&qce->dma); qce_ahash_done() 52 dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error); qce_ahash_done() 54 qce_unmapsg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE, qce_ahash_done() 56 qce_unmapsg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE, 0); qce_ahash_done() 65 error = qce_check_status(qce, &status); qce_ahash_done() 67 dev_dbg(qce->dev, "ahash operation error (%x)\n", status); qce_ahash_done() 74 qce->async_req_done(tmpl->qce, error); qce_ahash_done() 83 struct qce_device *qce = tmpl->qce; qce_ahash_async_req_handle() local 97 ret = qce_mapsg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE, qce_ahash_async_req_handle() 102 sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ); qce_ahash_async_req_handle() 104 ret = qce_mapsg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE, 0); qce_ahash_async_req_handle() 108 ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents, qce_ahash_async_req_handle() 113 qce_dma_issue_pending(&qce->dma); qce_ahash_async_req_handle() 122 qce_dma_terminate_all(&qce->dma); qce_ahash_async_req_handle() 124 qce_unmapsg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE, 0); qce_ahash_async_req_handle() 126 qce_unmapsg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE, qce_ahash_async_req_handle() 238 struct qce_device *qce = tmpl->qce; qce_ahash_update() local 306 return qce->async_req_enqueue(tmpl->qce, &req->base); qce_ahash_update() 313 struct qce_device *qce = tmpl->qce; qce_ahash_final() local 329 return qce->async_req_enqueue(tmpl->qce, &req->base); qce_ahash_final() 336 struct qce_device *qce = tmpl->qce; qce_ahash_digest() local 348 return qce->async_req_enqueue(tmpl->qce, &req->base); qce_ahash_digest() 390 alg_name = "sha1-qce"; qce_ahash_hmac_setkey() 392 alg_name = "sha256-qce"; qce_ahash_hmac_setkey() 464 .drv_name = "sha1-qce", 473 .drv_name = "sha256-qce", 482 .drv_name = "hmac-sha1-qce", 491 .drv_name = "hmac-sha256-qce", 500 struct qce_device *qce) qce_ahash_register_one() 542 tmpl->qce = qce; qce_ahash_register_one() 547 dev_err(qce->dev, "%s registration failed\n", base->cra_name); qce_ahash_register_one() 552 dev_dbg(qce->dev, "%s is registered\n", base->cra_name); qce_ahash_register_one() 556 static void qce_ahash_unregister(struct qce_device *qce) qce_ahash_unregister() argument 567 static int qce_ahash_register(struct qce_device *qce) qce_ahash_register() argument 572 ret = qce_ahash_register_one(&ahash_def[i], qce); qce_ahash_register() 579 qce_ahash_unregister(qce); qce_ahash_register() 499 qce_ahash_register_one(const struct qce_ahash_def *def, struct qce_device *qce) qce_ahash_register_one() argument
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H A D | core.h | 49 int (*async_req_enqueue)(struct qce_device *qce, 51 void (*async_req_done)(struct qce_device *qce, int ret); 63 int (*register_algs)(struct qce_device *qce); 64 void (*unregister_algs)(struct qce_device *qce);
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H A D | common.h | 93 struct qce_device *qce; member in struct:qce_alg_template 97 int qce_check_status(struct qce_device *qce, u32 *status); 98 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);
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/linux-4.1.27/fs/ntfs/ |
H A D | quota.c | 40 QUOTA_CONTROL_ENTRY *qce; ntfs_mark_quotas_out_of_date() local 72 qce = (QUOTA_CONTROL_ENTRY*)ictx->data; ntfs_mark_quotas_out_of_date() 73 if (le32_to_cpu(qce->version) != QUOTA_VERSION) { ntfs_mark_quotas_out_of_date() 75 "supported.", le32_to_cpu(qce->version)); ntfs_mark_quotas_out_of_date() 78 ntfs_debug("Quota defaults flags = 0x%x.", le32_to_cpu(qce->flags)); ntfs_mark_quotas_out_of_date() 80 if (qce->flags & QUOTA_FLAG_OUT_OF_DATE) ntfs_mark_quotas_out_of_date() 86 if (!(qce->flags & (QUOTA_FLAG_TRACKING_ENABLED | ntfs_mark_quotas_out_of_date() 95 qce->flags |= QUOTA_FLAG_OUT_OF_DATE; ntfs_mark_quotas_out_of_date()
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/linux-4.1.27/drivers/crypto/ |
H A D | Makefile | 28 obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
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