| /linux-4.1.27/arch/powerpc/boot/dts/fsl/ |
| D | p4080si-post.dtsi | 366 pll2: pll2@840 { label
371 clock-output-names = "pll2", "pll2-div2";
404 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
405 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
413 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
414 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
422 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
423 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
431 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
432 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
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| D | t4240si-post.dtsi | 637 pll2: pll2@840 { label
642 clock-output-names = "pll2", "pll2-div2", "pll2-div4";
667 <&pll2 0>, <&pll2 1>, <&pll2 2>;
670 "pll2", "pll2-div2", "pll2-div4";
680 <&pll2 0>, <&pll2 1>, <&pll2 2>;
683 "pll2", "pll2-div2", "pll2-div4";
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| /linux-4.1.27/drivers/mfd/ |
| D | sm501.c | 117 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
122 pll2 = 288 * MHZ; in decode_div()
124 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
141 unsigned long pll2 = 0; in sm501_dump_clk() local
145 pll2 = 336 * MHZ; in sm501_dump_clk()
148 pll2 = 288 * MHZ; in sm501_dump_clk()
151 pll2 = 240 * MHZ; in sm501_dump_clk()
154 pll2 = 192 * MHZ; in sm501_dump_clk()
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
[all …]
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| /linux-4.1.27/Documentation/devicetree/bindings/clock/ |
| D | renesas,r8a73a4-cpg-clocks.txt | 17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
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| D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
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| D | prima2-clock.txt | 18 pll2 3
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| D | imx28-clock.txt | 17 pll2 3
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 205 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
215 pll2 = 0; in setPLL_double_highregs()
224 pll2 |= 0x011f; in setPLL_double_highregs()
230 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
263 nv_wr32(devinit, reg2, pll2); in setPLL_double_highregs()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
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| /linux-4.1.27/drivers/clk/mxs/ |
| D | clk-imx28.c | 139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
176 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
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| /linux-4.1.27/arch/arm/boot/dts/ |
| D | ste-nomadik-stn8815.dtsi | 218 pll2: pll2@0 { label
229 clocks = <&pll2>;
244 clocks = <&pll2>;
252 clocks = <&pll2>;
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| D | r8a73a4.dtsi | 502 clock-output-names = "main", "pll0", "pll1", "pll2",
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| D | sh73a0.dtsi | 585 clock-output-names = "main", "pll0", "pll1", "pll2",
|
| /linux-4.1.27/Documentation/devicetree/bindings/video/ |
| D | ti,dra7-dss.txt | 24 'pll1', 'pll2_clkctrl', 'pll2'
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| /linux-4.1.27/drivers/clk/sirf/ |
| D | clk-prima2.c | 62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
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| D | clk-atlas6.c | 63 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
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| /linux-4.1.27/drivers/clk/qcom/ |
| D | mmcc-msm8960.c | 87 static struct clk_pll pll2 = { variable
2369 [PLL2] = &pll2.clkr,
2529 [PLL2] = &pll2.clkr,
|