Searched refs:omap2_clk_readl (Results 1 – 8 of 8) sorted by relevance
| /linux-4.1.27/arch/arm/mach-omap2/ |
| D | dpll3xxx.c | 50 v = omap2_clk_readl(clk, dd->control_reg); in _omap3_dpll_write_clken()
69 while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
147 if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state) in _omap3_noncore_dpll_lock()
311 v = omap2_clk_readl(clk, dd->control_reg); in omap3_noncore_dpll_program()
318 v = omap2_clk_readl(clk, dd->mult_div1_reg); in omap3_noncore_dpll_program()
349 v = omap2_clk_readl(clk, dd->control_reg); in omap3_noncore_dpll_program()
634 v = omap2_clk_readl(clk, dd->autoidle_reg); in omap3_dpll_autoidle_read()
668 v = omap2_clk_readl(clk, dd->autoidle_reg); in omap3_dpll_allow_idle()
694 v = omap2_clk_readl(clk, dd->autoidle_reg); in omap3_dpll_deny_idle()
756 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc()
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| D | dpll44xx.c | 51 v = omap2_clk_readl(clk, clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
69 v = omap2_clk_readl(clk, clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
130 v = omap2_clk_readl(clk, dd->control_reg); in omap4_dpll_regm4xen_recalc()
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| D | clkt_iclk.c | 34 v = omap2_clk_readl(clk, r); in omap2_clkt_iclk_allow_idle()
48 v = omap2_clk_readl(clk, r); in omap2_clkt_iclk_deny_idle()
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| D | clock.c | 119 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) in omap2_clk_readl() function
212 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), in _wait_idlest_generic()
245 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) in _omap2_module_wait_ready()
411 v = omap2_clk_readl(clk, clk->enable_reg); in omap2_dflt_clk_enable()
417 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
455 v = omap2_clk_readl(clk, clk->enable_reg); in omap2_dflt_clk_disable()
556 v = omap2_clk_readl(clk, clk->enable_reg); in omap2_dflt_clk_is_enabled()
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| D | clkt_clksel.c | 100 v = omap2_clk_readl(clk, clk->clksel_reg); in _write_clksel_reg()
105 v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */ in _write_clksel_reg()
207 v = omap2_clk_readl(clk, clk->clksel_reg); in _read_divisor()
323 r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask; in omap2_clksel_find_parent_index()
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| D | clkt_dpll.c | 214 v = omap2_clk_readl(clk, dd->control_reg); in omap2_init_dpll_parent()
250 v = omap2_clk_readl(clk, dd->control_reg); in omap2_get_dpll_rate()
257 v = omap2_clk_readl(clk, dd->mult_div1_reg); in omap2_get_dpll_rate()
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| D | clock36xx.c | 57 orig_v = omap2_clk_readl(omap_clk, parent->reg); in omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
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| D | clock.h | 223 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
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