Searched refs:mult_div1_reg (Results 1 – 7 of 7) sorted by relevance
| /linux-4.1.27/drivers/clk/ti/ |
| D | dpll.c | 235 dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg); in ti_clk_register_dpll()
386 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1); in of_ti_dpll_setup()
396 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2); in of_ti_dpll_setup()
399 if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg)) in of_ti_dpll_setup()
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| D | clock.h | 136 u16 mult_div1_reg; member
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| D | clk-3xxx-legacy.c | 129 .mult_div1_reg = 0xd40,
300 .mult_div1_reg = 0xd44,
502 .mult_div1_reg = 0xd4c,
1267 .mult_div1_reg = 0x940,
2151 .mult_div1_reg = 0x40,
2512 .mult_div1_reg = 0xd44,
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| /linux-4.1.27/arch/arm/mach-omap2/ |
| D | clkt2xxx_dpllcore.c | 141 tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg); in omap2_reprogram_dpllcore()
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| D | dpll3xxx.c | 318 v = omap2_clk_readl(clk, dd->mult_div1_reg); in omap3_noncore_dpll_program()
345 omap2_clk_writel(v, clk, dd->mult_div1_reg); in omap3_noncore_dpll_program()
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| D | clkt_dpll.c | 257 v = omap2_clk_readl(clk, dd->mult_div1_reg); in omap2_get_dpll_rate()
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| /linux-4.1.27/include/linux/clk/ |
| D | ti.h | 69 void __iomem *mult_div1_reg; member
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