/linux-4.1.27/arch/sh/kernel/cpu/sh2/ |
H A D | entry.S | 46 mov.l r2,@-sp 47 mov.l r3,@-sp 49 mov.l $cpu_mode,r2 50 mov.l @r2,r0 51 mov.l @(5*4,r15),r3 ! previous SR 55 mov.l r3,@(5*4,r15) ! update SR 57 mov.l __md_bit,r0 58 mov.l r0,@r2 ! enter kernel mode 59 mov.l $current_thread_info,r2 60 mov.l @r2,r2 61 mov #(THREAD_SIZE >> 8),r0 64 mov r15,r2 ! r2 = user stack top 65 mov r0,r15 ! switch kernel stack 66 mov.l r1,@-r15 ! TRA 70 mov.l @(5*4,r2),r0 71 mov.l r0,@-r15 ! original SR 73 mov.l @(4*4,r2),r0 74 mov.l r0,@-r15 ! original PC 75 mov r2,r3 77 mov.l r3,@-r15 ! original SP 78 mov.l r14,@-r15 79 mov.l r13,@-r15 80 mov.l r12,@-r15 81 mov.l r11,@-r15 82 mov.l r10,@-r15 83 mov.l r9,@-r15 84 mov.l r8,@-r15 85 mov.l r7,@-r15 86 mov.l r6,@-r15 87 mov.l r5,@-r15 88 mov.l r4,@-r15 89 mov r1,r9 ! save TRA 90 mov r2,r8 ! copy user -> kernel stack 91 mov.l @(0,r8),r3 92 mov.l r3,@-r15 93 mov.l @(4,r8),r2 94 mov.l r2,@-r15 95 mov.l @(12,r8),r1 96 mov.l r1,@-r15 97 mov.l @(8,r8),r0 99 mov.l r0,@-r15 102 mov #(22-4-4-1)*4+4,r0 103 mov r15,r2 105 mov.l @r2+,r0 ! old R3 106 mov.l r0,@-r15 107 mov.l @r2+,r0 ! old R2 108 mov.l r0,@-r15 109 mov.l @(4,r2),r0 ! old R1 110 mov.l r0,@-r15 111 mov.l @r2,r0 ! old R0 112 mov.l r0,@-r15 114 mov.l @r2+,r3 ! old PC 115 mov.l @r2+,r0 ! old SR 117 mov.l r1,@-r2 ! TRA 121 mov.l r0,@-r2 ! save old SR 123 mov.l r3,@-r2 ! save old PC 124 mov r2,r0 126 mov.l r0,@-r2 ! save old SP 127 mov.l r14,@-r2 128 mov.l r13,@-r2 129 mov.l r12,@-r2 130 mov.l r11,@-r2 131 mov.l r10,@-r2 132 mov.l r9,@-r2 133 mov.l r8,@-r2 134 mov.l r7,@-r2 135 mov.l r6,@-r2 136 mov.l r5,@-r2 137 mov.l r4,@-r2 138 mov r1,r9 139 mov.l @(OFF_R0,r15),r0 140 mov.l @(OFF_R1,r15),r1 141 mov.l @(OFF_R2,r15),r2 142 mov.l @(OFF_R3,r15),r3 144 mov #64,r8 147 mov #32,r8 151 mov.l 4f,r8 152 mov r9,r4 155 mov.l @r8,r8 ! exception handler address 158 mov.l 8f,r8 ! unhandled exception 160 mov.l 5f,r10 165 mov r9,r4 166 mov r15,r5 167 mov.l 6f,r9 168 mov.l 7f,r8 180 mov #0x30,r8 187 mov r9,r8 192 mov r15,r0 197 mov r15,r0 198 mov.l @(OFF_SP,r0),r1 199 mov #OFF_SR,r2 200 mov.l @(r0,r2),r3 201 mov.l r3,@-r1 202 mov #OFF_SP,r2 203 mov.l @(r0,r2),r3 204 mov.l r3,@-r1 205 mov r15,r0 207 mov.l 1f,r2 208 mov.l @r2,r2 210 mov.l r2,@r0 211 mov.l r3,@(4,r0) 212 mov.l r1,@(8,r0) 213 mov.l @r15+, r0 214 mov.l @r15+, r1 215 mov.l @r15+, r2 216 mov.l @r15+, r3 217 mov.l @r15+, r4 218 mov.l @r15+, r5 219 mov.l @r15+, r6 220 mov.l @r15+, r7 221 mov.l @r15+, r8 222 mov.l @r15+, r9 223 mov.l @r15+, r10 224 mov.l @r15+, r11 225 mov.l @r15+, r12 226 mov.l @r15+, r13 227 mov.l @r15+, r14 230 mov.l @r15+,r15 238 mov r15,r4 ! regs 239 mov #OFF_PC,r0 240 mov.l @(r0,r15),r6 ! pc 241 mov.l 1f,r0 243 mov #0,r5 ! writeaccess is unknown 254 mov r15,r0 261 mov r15,r0 262 mov.l $cpu_mode,r2 263 mov #OFF_SR,r3 264 mov.l @(r0,r3),r1 265 mov.l __md_bit,r3 267 mov.l r3,@r2 270 mov.l @(OFF_SP,r0),r2 272 mov.l r2,@(OFF_SP,r0) ! point exception frame top 273 mov.l r1,@(4,r2) ! set sr 274 mov #OFF_PC,r3 275 mov.l @(r0,r3),r1 276 mov.l r1,@r2 ! set pc 278 mov.l $current_thread_info,r1 279 mov.l r0,@r1 280 mov.l @r15+,r0 281 mov.l @r15+,r1 282 mov.l @r15+,r2 283 mov.l @r15+,r3 284 mov.l @r15+,r4 285 mov.l @r15+,r5 286 mov.l @r15+,r6 287 mov.l @r15+,r7 288 mov.l @r15+,r8 289 mov.l @r15+,r9 290 mov.l @r15+,r10 291 mov.l @r15+,r11 292 mov.l @r15+,r12 293 mov.l @r15+,r13 294 mov.l @r15+,r14 295 mov.l @r15,r15
|
H A D | ex.S | 21 mov.l r1,@-sp 23 mov #no,r1 27 mov.l r0,@-sp 28 mov.l $exception_handler,r0
|
/linux-4.1.27/arch/sh/kernel/ |
H A D | relocate_kernel.S | 22 mov.l 10f, r0 /* PAGE_SIZE */ 26 mov.l r15, @-r0 27 mov r0, r15 28 mov.l r14, @-r15 29 mov.l r13, @-r15 30 mov.l r12, @-r15 31 mov.l r11, @-r15 32 mov.l r10, @-r15 33 mov.l r9, @-r15 34 mov.l r8, @-r15 46 mov.l 12f, r9 50 mov.l r7, @-r15 51 mov.l r6, @-r15 52 mov.l r5, @-r15 53 mov.l r4, @-r15 54 mov.l r3, @-r15 55 mov.l r2, @-r15 56 mov.l r1, @-r15 57 mov.l r0, @-r15 60 mov.l 12f, r9 65 mov.l r7, @-r15 66 mov.l r6, @-r15 67 mov.l r5, @-r15 68 mov.l r4, @-r15 69 mov.l r3, @-r15 70 mov.l r2, @-r15 71 mov.l r1, @-r15 72 mov.l r0, @-r15 74 mov.l r4, @-r15 /* save indirection page again */ 80 mov.l r15, @r0 /* save pointer to stack */ 85 mov.l 11f, r15 /* get pointer to stack */ 86 mov.l @r15+, r4 /* restore r4 to get indirection page */ 92 mov.l 12f, r9 97 mov.l @r15+, r0 98 mov.l @r15+, r1 99 mov.l @r15+, r2 100 mov.l @r15+, r3 101 mov.l @r15+, r4 102 mov.l @r15+, r5 103 mov.l @r15+, r6 104 mov.l @r15+, r7 107 mov.l 12f, r9 111 mov.l @r15+, r0 112 mov.l @r15+, r1 113 mov.l @r15+, r2 114 mov.l @r15+, r3 115 mov.l @r15+, r4 116 mov.l @r15+, r5 117 mov.l @r15+, r6 118 mov.l @r15+, r7 121 mov.l 12f, r9 137 mov.l @r15+, r8 138 mov.l @r15+, r9 139 mov.l @r15+, r10 140 mov.l @r15+, r11 141 mov.l @r15+, r12 142 mov.l @r15+, r13 143 mov.l @r15+, r14 144 mov.l @r15+, r15 150 mov r4,r0 /* cmd = indirection_page */ 152 mov.l @r4+,r0 /* cmd = *ind++ */ 155 mov r0,r2 156 mov #-16,r1 163 mov r2,r5 169 mov r2,r4 181 mov.l 10f,r3 /* PAGE_SIZE */ 193 mov.l @(0, r2), r8 194 mov.l @(0, r5), r1 195 mov.l r8, @(0, r5) 196 mov.l r1, @(0, r2) 198 mov.l @(4, r2), r8 199 mov.l @(4, r5), r1 200 mov.l r8, @(4, r5) 201 mov.l r1, @(4, r2) 203 mov.l @(8, r2), r8 204 mov.l @(8, r5), r1 205 mov.l r8, @(8, r5) 206 mov.l r1, @(8, r2) 208 mov.l @(12, r2), r8 209 mov.l @(12, r5), r1 210 mov.l r8, @(12, r5) 211 mov.l r1, @(12, r2)
|
H A D | entry-common.S | 61 mov.l 1f, r0 84 mov #OFF_SR, r0 85 mov.l @(r0,r15), r0 ! get status register 97 mov.l @(TI_PRE_COUNT,r8), r0 ! current_thread_info->preempt_count 101 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags 105 mov #OFF_SR, r0 106 mov.l @(r0,r15), r0 ! get status register 111 mov.l 1f, r0 129 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags 143 mov r15, r4 144 mov r12, r5 ! set arg1(save_r0) 145 mov r0, r6 147 mov.l 2f, r1 148 mov.l 3f, r0 152 mov.l 1f, r1 158 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags 178 mov r15, r4 179 mov.l 8f, r0 ! do_syscall_trace_leave 188 mov r15, r4 189 mov.l 7f, r11 ! Call do_syscall_trace_enter which notifies 192 mov.l r0, @(OFF_R0,r15) ! Save return value 200 mov.l @(OFF_R4,r15), r4 ! arg0 201 mov.l @(OFF_R5,r15), r5 202 mov.l @(OFF_R6,r15), r6 203 mov.l @(OFF_R7,r15), r7 ! arg3 204 mov.l @(OFF_R3,r15), r3 ! syscall_nr 206 mov.l 2f, r10 ! Number of syscalls 209 mov #-ENOSYS, r0 211 mov.l r0, @(OFF_R0,r15) ! Return value 214 mov #OFF_SR, r0 215 mov.l @(r0,r15), r0 ! get status register 227 mov.l 3f, r0 237 mov #-ENOSYS, r0 239 mov.l r0, @(OFF_R0,r15) ! Return value 251 mov r8, r0 253 mov.l 1f, r8 255 mov.l @r8, r8 293 mov.l 1f, r8 295 mov r0, r4 302 mov.l 1f, r8 304 mov r0, r4 305 mov.l @(OFF_R5,r15), r5 ! fn 307 mov.l @(OFF_R4,r15), r4 ! arg 321 mov.l 1f, r9 322 mov.l @r9, r8 ! Read from TRA (Trap Address) Register 325 mov #OFF_TRA, r10 327 mov.l r8, @r10 ! set TRA value to tra 332 mov #((0x20 << 2) - 1), r9 342 mov.l @(TI_FLAGS,r8), r8 343 mov #(_TIF_WORK_SYSCALL_MASK & 0xff), r10 344 mov #(_TIF_WORK_SYSCALL_MASK >> 8), r9 351 mov.l 2f, r8 ! Number of syscalls 357 mov.l 3f, r8 ! Load the address of sys_call_table 359 mov.l @r3, r8 360 mov.l @(OFF_R2,r15), r2 361 mov.l @(OFF_R1,r15), r1 362 mov.l @(OFF_R0,r15), r0 363 mov.l r2, @-r15 364 mov.l r1, @-r15 365 mov.l r0, @-r15 369 mov.l @(OFF_R0,r15), r12 ! save r0 370 mov.l r0, @(OFF_R0,r15) ! save the return value 377 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags 379 mov #(_TIF_ALLWORK_MASK >> 8), r1
|
H A D | io.c | 32 "mov.l @%7+, r0 \n\t" memcpy_fromio() 33 "mov.l @%7+, %2 \n\t" memcpy_fromio() 35 "mov.l @%7+, %3 \n\t" memcpy_fromio() 36 "mov.l @%7+, %4 \n\t" memcpy_fromio() 37 "mov.l @%7+, %5 \n\t" memcpy_fromio() 38 "mov.l @%7+, %6 \n\t" memcpy_fromio() 39 "mov.l @%7+, r7 \n\t" memcpy_fromio() 40 "mov.l @%7+, r0 \n\t" memcpy_fromio() 41 "mov.l %2, @(0x04,%0) \n\t" memcpy_fromio() 42 "mov #0x20, %2 \n\t" memcpy_fromio() 43 "mov.l %3, @(0x08,%0) \n\t" memcpy_fromio() 45 "mov.l %4, @(0x0c,%0) \n\t" memcpy_fromio() 47 "mov.l %5, @(0x10,%0) \n\t" memcpy_fromio() 48 "mov.l %6, @(0x14,%0) \n\t" memcpy_fromio() 49 "mov.l r7, @(0x18,%0) \n\t" memcpy_fromio() 50 "mov.l r0, @(0x1c,%0) \n\t" memcpy_fromio()
|
H A D | head_32.S | 24 mov.l label, reg; \ 62 mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF 66 mov #0, r0 81 mov.l 2f, r0 82 mov r0, r15 ! Set initial r15 (stack pointer) 84 mov.l 7f, r0 137 mov.l .LMMUCR, r1 /* Flush the TLB */ 138 mov.l @r1, r0 140 mov.l r0, @r1 142 mov.l .LMEMORY_SIZE, r5 144 mov #PMB_E_SHIFT, r0 145 mov #0x1, r4 148 mov.l .LFIRST_DATA_ENTRY, r0 149 mov.l .LPMB_DATA, r1 150 mov.l .LFIRST_ADDR_ENTRY, r2 151 mov.l .LPMB_ADDR, r3 164 mov #0, r10 165 mov #NR_PMB_ENTRIES, r9 167 mov r1, r7 /* temporary PMB_DATA iter */ 171 mov.l .LPMB_DATA_MASK, r11 172 mov.l @r7, r8 187 mov r5, r7 /* cached_to_uncached */ 188 mov #0, r10 194 mov #(PMB_SZ_16M >> 2), r9 197 mov #(PMB_UB >> 8), r8 202 mov.l r8, @r1 203 mov r2, r8 205 mov.l r8, @r3 218 mov #(size >> 4), r6; \ 225 mov #(PMB_SZ_##size##M >> 2), r9; \ 231 mov #PMB_C, r8; \ 234 mov.l r8, @r1; \ 235 mov.l r2, @r3; \ 261 mov.l .Lcached_to_uncached, r0 262 mov.l r7, @r0 264 mov.l .Luncached_size, r0 265 mov #1, r7 268 mov.l r7, @r0 277 mov #0, r1 278 mov #NR_PMB_ENTRIES, r0 281 mov.l r1, @r3 /* Clear PMB_ADDR entry */ 287 mov.l 6f, r0 301 mov.l 3f, r0 306 mov.l 3f, r1 308 mov.l 4f, r2 309 mov #0, r0 312 mov.l r0,@-r2 318 mov.l 6f, r0 325 mov.l 5f, r0
|
/linux-4.1.27/arch/sh/lib/ |
H A D | copy_page.S | 27 mov.l r8,@-r15 28 mov.l r10,@-r15 29 mov.l r11,@-r15 30 mov r4,r10 31 mov r5,r11 32 mov r5,r8 33 mov #(PAGE_SIZE >> 10), r0 38 1: mov.l @r11+,r0 39 mov.l @r11+,r1 40 mov.l @r11+,r2 41 mov.l @r11+,r3 42 mov.l @r11+,r4 43 mov.l @r11+,r5 44 mov.l @r11+,r6 45 mov.l @r11+,r7 49 mov.l r0,@r10 52 mov.l r7,@-r10 53 mov.l r6,@-r10 54 mov.l r5,@-r10 55 mov.l r4,@-r10 56 mov.l r3,@-r10 57 mov.l r2,@-r10 58 mov.l r1,@-r10 63 mov.l @r15+,r11 64 mov.l @r15+,r10 65 mov.l @r15+,r8 85 mov #11,r0 86 mov r4,r3 92 mov.l r11,@-r15 94 mov.l r10,@-r15 96 mov.l r9,@-r15 98 mov.l r8,@-r15 104 EX( mov.b @r5+,r1 ) 107 EX( mov.b r1,@r4 ) 112 2: mov #3,r1 113 mov r6, r2 118 mov.l @(r0,r1),r1 142 EX_NO_POP( mov.b @r5+,r0 ) 144 EX_NO_POP( mov.b r0,@r4 ) 148 1: mov #0,r0 ! normal return 154 mov.l 8000f,r1 155 mov r3,r0 169 mov #(32+32-4), r0 183 EX( mov.l @r5+,r1 ) 185 EX( mov.l r1,@r4 ) 190 EX( mov.l @r5+,r0 ) 191 EX( mov.l @r5+,r1 ) 192 EX( mov.l @r5+,r2 ) 193 EX( mov.l @r5+,r7 ) 194 EX( mov.l @r5+,r8 ) 195 EX( mov.l @r5+,r9 ) 196 EX( mov.l @r5+,r10 ) 197 EX( mov.l @r5+,r11 ) 201 EX( mov.l r0,@r4 ) 204 EX( mov.l r1,@(4,r4) ) 205 mov #32, r0 206 EX( mov.l r2,@(8,r4) ) 208 EX( mov.l r7,@(12,r4) ) 209 EX( mov.l r8,@(16,r4) ) 210 EX( mov.l r9,@(20,r4) ) 211 EX( mov.l r10,@(24,r4) ) 212 EX( mov.l r11,@(28,r4) ) 216 1: mov r6, r0 221 EX( mov.l @r5+,r1 ) 223 EX( mov.l r1,@r4 ) 233 mov r2,r7 237 mov #7,r0 243 EX( mov.l @r5+,r0 ) 244 EX( mov.l @r5+,r1 ) 245 EX( mov.l @r5+,r8 ) 246 EX( mov.l @r5+,r9 ) 247 EX( mov.l @r5+,r10 ) 248 EX( mov.w r0,@r4 ) 255 EX( mov.l r0,@r4 ) 256 EX( mov.l r1,@(4,r4) ) 257 EX( mov.l r8,@(8,r4) ) 258 EX( mov.l r9,@(12,r4) ) 260 EX( mov.l @r5+,r1 ) 261 EX( mov.l @r5+,r8 ) 262 EX( mov.l @r5+,r0 ) 267 EX( mov.l r10,@(16,r4) ) 268 EX( mov.l r1,@(20,r4) ) 269 EX( mov.l r8,@(24,r4) ) 270 EX( mov.w r0,@(28,r4) ) 274 EX( mov.l @(28,r5),r0 ) 275 EX( mov.l @(24,r5),r8 ) 276 EX( mov.l @(20,r5),r9 ) 277 EX( mov.l @(16,r5),r10 ) 278 EX( mov.w r0,@(30,r4) ) 283 EX( mov.l r0,@(28,r4) ) 284 EX( mov.l r8,@(24,r4) ) 285 EX( mov.l r9,@(20,r4) ) 287 EX( mov.l @(12,r5),r0 ) 288 EX( mov.l @(8,r5),r8 ) 290 EX( mov.l @(4,r5),r9 ) 291 mov.l r10,@(16,r4) 292 EX( mov.l @r5,r10 ) 296 EX( mov.l r0,@(12,r4) ) 297 EX( mov.l r8,@(8,r4) ) 299 EX( mov.l r9,@(4,r4) ) 300 EX( mov.w r0,@(2,r4) ) 310 EX( mov.l @r5+,r0 ) 313 EX( mov.w r0,@r4 ) 315 EX( mov.w r0,@(2,r4) ) 317 EX( mov.w r0,@(2,r4) ) 319 EX( mov.w r0,@r4 ) 332 EX( mov.l @r5+,r0 ) 335 EX( mov.b r0,@r4 ) 338 EX( mov.w r0,@r4 ) 340 EX( mov.b r0,@(2,r4) ) 344 EX( mov.b r0,@(3,r4) ) 347 EX( mov.b r7,@r4 ) 349 EX( mov.w r0,@r4 ) 356 mov r6,r0 360 mov r0,r6 363 EX( mov.b @r5+,r0 ) 365 EX( mov.b r0,@r4 ) 370 mov #0,r0 ! normal return 377 mov.l 8000f,r1 378 mov r3,r0 385 mov.l @r15+,r8 386 mov.l @r15+,r9 387 mov.l @r15+,r10 389 mov.l @r15+,r11
|
H A D | memcpy.S | 18 mov r4,r0 21 mov #12,r1 34 mov r5,r1 35 mov #3,r2 38 mov r0,r3 ! Save the value on R0 to R3 41 mov.l @r0,r1 43 mov r3,r0 ! and back to R0 52 7: mov r4,r2 56 mov.b @(r0,r5),r1 58 mov.b r1,@-r0 68 mov r0,r3 75 mov.b @(r0,r5),r1 77 mov.b r1,@-r0 81 mov r4,r2 83 3: mov.l @(r0,r5),r1 86 mov.l r1,@-r0 100 mov r0,r3 106 mov.b @(r0,r5),r1 108 mov.b r1,@-r0 111 mov.l @(r0,r5),r1 113 mov r4,r2 117 3: mov r1,r3 ! RQPO 120 mov.l @(r0,r5),r1 ! NMLK 121 mov r1,r6 126 mov.l r3,@-r0 128 3: mov r1,r3 ! OPQR 131 mov.l @(r0,r5),r1 ! KLMN 132 mov r1,r6 137 mov.l r3,@-r0 155 mov.b @(r0,r5),r1 156 mov.b r1,@-r0 160 mov r4,r2 163 3: mov.w @(r0,r5),r1 166 mov.w r1,@-r0 172 mov.b @(r0,r5),r1 174 mov.b r1,@-r0 181 mov r0,r3 187 mov.b @(r0,r5),r1 189 mov.b r1,@-r0 193 mov.l @(r0,r5),r1 195 mov r4,r2 199 3: mov r1,r3 ! RQPO 201 mov.l @(r0,r5),r1 ! NMLK 202 mov r1,r6 208 mov.l r3,@-r0 210 3: mov r1,r3 ! OPQR 212 mov.l @(r0,r5),r1 ! KLMN 213 mov r1,r6 219 mov.l r3,@-r0
|
H A D | io.c | 29 "mov.l @%7, r0 \n\t" __raw_readsl() 30 "mov.l @%7, %2 \n\t" __raw_readsl() 34 "mov.l r0, @%0 \n\t" __raw_readsl() 36 "mov.l @%7, %3 \n\t" __raw_readsl() 37 "mov.l @%7, %4 \n\t" __raw_readsl() 38 "mov.l @%7, %5 \n\t" __raw_readsl() 39 "mov.l @%7, %6 \n\t" __raw_readsl() 40 "mov.l @%7, r7 \n\t" __raw_readsl() 41 "mov.l @%7, r0 \n\t" __raw_readsl() 42 "mov.l %2, @(0x04,%0) \n\t" __raw_readsl() 43 "mov #0x20>>2, %2 \n\t" __raw_readsl() 44 "mov.l %3, @(0x08,%0) \n\t" __raw_readsl() 46 "mov.l %4, @(0x0c,%0) \n\t" __raw_readsl() 48 "mov.l %5, @(0x10,%0) \n\t" __raw_readsl() 49 "mov.l %6, @(0x14,%0) \n\t" __raw_readsl() 50 "mov.l r7, @(0x18,%0) \n\t" __raw_readsl() 51 "mov.l r0, @(0x1c,%0) \n\t" __raw_readsl() 73 "mov.l @%0+, %1 \n\t" __raw_writesl() 76 " mov.l %1, @%4 \n\t" __raw_writesl()
|
H A D | memmove.S | 19 mov.l 2f,r0 28 mov r5,r0 30 mov #12,r1 44 mov r4,r1 45 mov #3,r2 48 mov r0,r3 ! Save the value on R0 to R3 51 mov.l @r0,r1 53 mov r3,r0 ! and back to R0 62 8: mov.b @r0+,r1 65 mov.b r1,@(r0,r4) 81 mov r0,r3 86 mov #4,r2 89 mov.b @r0+,r1 91 mov.b r1,@(r0,r4) 96 3: mov.l @r0+,r1 99 mov.l r1,@(r0,r4) 114 mov r0,r3 119 mov #4,r2 122 mov.b @r0+,r1 124 mov.b r1,@(r0,r4) 128 mov.l @(r0,r4),r1 134 3: mov r1,r3 ! JIHG 136 mov.l @r0+,r1 ! NMLK 137 mov r1,r2 143 mov.l r3,@(r0,r4) 146 3: mov r1,r3 ! GHIJ 148 mov.l @r0+,r1 ! KLMN 149 mov r1,r2 155 mov.l r3,@(r0,r4) 175 mov.b @r0+,r1 176 mov.b r1,@(r0,r4) 182 3: mov.w @r0+,r1 185 mov.w r1,@(r0,r4) 192 mov.b @r0,r1 193 mov.b r1,@(r0,r4) 202 mov r0,r3 207 mov #4,r2 210 mov.b @r0+,r1 212 mov.b r1,@(r0,r4) 215 mov.l @(r0,r4),r1 222 3: mov r1,r3 ! JIHG 225 mov.l @r0+,r1 ! NMLK 226 mov r1,r2 231 mov.l r3,@(r0,r4) 235 3: mov r1,r3 ! GHIJ 238 mov.l @r0+,r1 ! KLMN 239 mov r1,r2 244 mov.l r3,@(r0,r4)
|
H A D | checksum.S | 51 mov r4, r0 54 mov r4, r7 ! Keep a copy to check for alignment 63 mov.b @r4+, r0 66 mov r6, r0 71 mov r4, r0 83 mov.w @r4+, r0 90 mov r5, r1 91 mov #-5, r0 98 mov.l @r4+, r0 99 mov.l @r4+, r2 100 mov.l @r4+, r3 102 mov.l @r4+, r0 104 mov.l @r4+, r2 106 mov.l @r4+, r3 108 mov.l @r4+, r0 110 mov.l @r4+, r2 121 mov r5, r0 126 mov r0, r1 128 mov #0, r2 131 mov.l @r4+, r2 140 mov #3, r0 144 mov #2, r1 147 mov.w @r4+, r0 155 mov.b @r4+, r0 162 mov #0, r0 166 mov r7, r0 169 mov r6, r0 176 mov r6, r0 217 mov.l r5,@-r15 218 mov.l r6,@-r15 220 mov #3,r0 ! Check src and dest are equally aligned 221 mov r4,r1 229 mov #2,r0 238 mov r6,r2 242 mov r6,r2 249 SRC( mov.b @r4+,r1 ) 250 SRC( mov.b @r4+,r0 ) 252 DST( mov.b r1,@r5 ) 253 DST( mov.b r0,@(1,r5) ) 269 mov #0,r0 272 mov r2, r0 282 SRC( mov.w @r4+,r0 ) 283 DST( mov.w r0,@r5 ) 287 mov #0,r0 290 mov r6,r2 291 mov #-5,r0 298 SRC( mov.l @r4+,r0 ) 299 SRC( mov.l @r4+,r1 ) 301 DST( mov.l r0,@r5 ) 302 DST( mov.l r1,@(4,r5) ) 305 SRC( mov.l @r4+,r0 ) 306 SRC( mov.l @r4+,r1 ) 308 DST( mov.l r0,@(8,r5) ) 309 DST( mov.l r1,@(12,r5) ) 312 SRC( mov.l @r4+,r0 ) 313 SRC( mov.l @r4+,r1 ) 315 DST( mov.l r0,@(16,r5) ) 316 DST( mov.l r1,@(20,r5) ) 319 SRC( mov.l @r4+,r0 ) 320 SRC( mov.l @r4+,r1 ) 322 DST( mov.l r0,@(24,r5) ) 323 DST( mov.l r1,@(28,r5) ) 330 mov #0,r0 333 2: mov r2,r6 334 mov #0x1c,r0 341 SRC( mov.l @r4+,r0 ) 343 DST( mov.l r0,@r5 ) 349 mov #0,r0 351 4: mov r2,r6 352 mov #3,r0 356 mov #2,r1 359 SRC( mov.w @r4+,r0 ) 360 DST( mov.w r0,@r5 ) 369 SRC( mov.b @r4+,r0 ) 370 DST( mov.b r0,@r5 ) 376 mov #0,r0 385 mov.l @(8,r15),r0 ! src_err_ptr 386 mov #-EFAULT,r1 387 mov.l r1,@r0 391 mov.l @(4,r15),r5 ! dst 392 mov.l @r15,r6 ! len 393 mov #0,r7 394 1: mov.b r7,@r5 398 mov.l 8000f,r0 405 mov.l @(12,r15),r0 ! dst_err_ptr 406 mov #-EFAULT,r1 407 mov.l r1,@r0 408 mov.l 8001f,r0 417 mov r7,r0
|
H A D | movmem.S | 52 mov.l @(48,r5),r0 55 mov.l @(60,r5),r0 57 mov.l r0,@(60,r4) 59 mov.l @(56,r5),r0 61 mov.l r0,@(56,r4) 63 mov.l @(52,r5),r0 65 mov.l r0,@(52,r4) 75 mov.l r0,@(56,r4) 76 mov.l @(52,r5),r0 78 mov.l r0,@(52,r4) 85 mov.l @(60,r5),r0 86 mov.l r0,@(60,r4) 91 mov.l @(56,r5),r0 92 mov.l r0,@(56,r4) 97 mov.l @(52,r5),r0 98 mov.l r0,@(52,r4) 103 mov.l @(48,r5),r0 104 mov.l r0,@(48,r4) 109 mov.l @(44,r5),r0 110 mov.l r0,@(44,r4) 115 mov.l @(40,r5),r0 116 mov.l r0,@(40,r4) 121 mov.l @(36,r5),r0 122 mov.l r0,@(36,r4) 127 mov.l @(32,r5),r0 128 mov.l r0,@(32,r4) 133 mov.l @(28,r5),r0 134 mov.l r0,@(28,r4) 139 mov.l @(24,r5),r0 140 mov.l r0,@(24,r4) 145 mov.l @(20,r5),r0 146 mov.l r0,@(20,r4) 151 mov.l @(16,r5),r0 152 mov.l r0,@(16,r4) 157 mov.l @(12,r5),r0 158 mov.l r0,@(12,r4) 163 mov.l @(8,r5),r0 164 mov.l r0,@(8,r4) 169 mov.l @(4,r5),r0 170 mov.l r0,@(4,r4) 175 mov.l @(0,r5),r0 177 mov.l r0,@(0,r4) 193 mov.l r0,@(16,r4) 195 mov.l r1,@(20,r4) 200 mov.l @r5+,r0 202 mov.l @r5+,r1 205 mov.l @r5+,r1 207 mov.l @r5+,r2 208 mov.l @r5+,r3 209 mov.l r1,@(4,r4) 210 mov.l r2,@(8,r4) 213 mov.l r3,@(12,r4) 215 mov.l @r5+,r0 217 mov.l @r5+,r1 220 mov.l @r5+,r2 221 mov.l @r5+,r3 222 mov.l r0,@r4 224 mov.l r1,@(4,r4) 226 mov.l r2,@(8,r4) 228 mov.l r3,@(12,r4) 232 mov.l @r5,r0 233 mov.l @(4,r5),r1 234 mov.l @(8,r5),r2 235 mov.l r0,@r4 236 mov.l r1,@(4,r4) 238 mov.l r2,@(8,r4)
|
H A D | mcount.S | 16 mov.l r4, @-r15; \ 17 mov.l r5, @-r15; \ 18 mov.l r6, @-r15; \ 19 mov.l r7, @-r15; \ 22 mov.l @(20,r15),r4; \ 27 mov.l @r15+, r7; \ 28 mov.l @r15+, r6; \ 29 mov.l @r15+, r5; \ 31 mov.l @r15+, r4 45 mov #(THREAD_SIZE >> 10), r0; \ 50 mov #-1, r1; \ 54 mov #TI_SIZE, r3; \ 55 mov #(STACK_WARN >> 8), r2; \ 64 mov.l .L_ebss, r1; \ 69 mov.l .L_init_thread_union, r1; \ 100 mov.l .Lftrace_stub, r6 102 mov.l .Lftrace_trace_function, r6 103 mov.l ftrace_stub, r7 106 mov.l @r6, r6 113 mov.l .Lftrace_graph_return, r6 114 mov.l .Lftrace_stub, r7 118 mov.l .Lftrace_graph_caller, r0 123 mov.l .Lftrace_graph_entry, r6 124 mov.l .Lftrace_graph_entry_stub, r7 128 mov.l .Lftrace_graph_caller, r0 159 mov.l .Lskip_trace, r0 174 mov.l .Lftrace_stub, r6 206 mov.l 2f, r1 215 mov #20, r0 217 mov r0, r4 219 mov.l .Lprepare_ftrace_return, r0 235 mov.l r0, @-r15 236 mov.l r1, @-r15 238 mov #0, r4 240 mov.l .Lftrace_return_to_handler, r0 249 mov.l @r15+, r1 251 mov.l @r15+, r0 263 mov.l .Ldump_stack, r0 267 mov.l .Lpanic, r0 269 mov.l .Lpanic_s, r4
|
H A D | udivsi3_i4i.S | 63 mov.w c128_w, r1 65 mov r4,r0 73 mov r5,r1 75 mov.l r4,@-r15 77 mov.l r1,@-r15 86 mov.b @(r0,r5),r1 88 mov.l r4,@-r15 90 mov.b @(r0,r5),r1 91 mov.l r5,@-r15 94 mov.l @(r0,r1),r1 95 mov r5,r0 99 mov.b @(r0,r5),r1 101 mov r4,r0 102 mov.l @r15+,r5 106 mov.l @r15+,r4 114 mov.l @r15+,r5 116 mov.l @r15+,r4 126 mov r5,r1 129 mov.l r4,@-r15 131 mov.l r1,@-r15 134 mov.l zero_l,r1 138 mov.l r1,@-r15 140 mov.w m256_w,r1 142 mov.b r0,@(L_LSWMSB,r15) 153 mov.l r4,@-r15 157 mov.l r5,@-r15 160 mov r0,r1 162 mov r4,r0 164 mov r5,r4 170 mov.l @r15+,r5 172 mov.l @r15+,r4 185 mov.l r4,@-r15 187 mov.w c128_w, r1 190 mov.l r5,@-r15 199 mov r4,r0 209 mov.l zero_l,r1 212 mov.l r1,@-r15 216 mov.b r0,@(L_MSWLSB,r15) 222 mov.b r0,@(L_LSWMSB,r15) 227 mov.l @r15+,r4 ! zero-extension and swap using LS unit. 229 mov.l @r15+,r5 231 mov.l @r15+,r4 238 mov.b @(r0,r5),r1 241 mov.l @(r0,r1),r1 244 mov.b @(r0,r5),r1 245 mov.l @r15+,r5 249 mov.l @r15+,r4 256 mov.l r5,@-r15 264 mov r4,r0 269 mov.l zero_l,r1 272 mov.l r1,@-r15 276 mov.b r0,@(L_MSWLSB,r15) 282 mov.b r0,@(L_LSWMSB,r15) 287 mov.l @r15+,r4 ! zero-extension and swap using LS unit. 289 mov.l @r15+,r5 292 mov.l @r15+,r4 301 mov.l zero_l,r1 305 mov.l r1,@-r15 307 mov.w m256_w,r1 309 mov.b r0,@(L_LSWMSB,r15) 321 mov r4,r1 323 mov r5,r4 327 mov.l @r15+,r5
|
H A D | udivsi3_i4i-Os.S | 49 mov.l r4,@-r15 56 mov.l r5,@-r15 73 mov.l @r15+,r5 75 mov.l @r15+,r4 94 mov.l r5,@-r15 102 mov.l @r15+,r5 103 mov.l @r15+,r4 113 mov.l r4,@-r15 115 mov.l r5,@-r15 135 mov r0,r1
|
/linux-4.1.27/arch/x86/lib/ |
H A D | memcpy_32.c | 46 "mov %1, %3\n\t" memmove() 58 "mov 0*4(%1), %3\n\t" memmove() 59 "mov 1*4(%1), %4\n\t" memmove() 60 "mov %3, 0*4(%2)\n\t" memmove() 61 "mov %4, 1*4(%2)\n\t" memmove() 62 "mov 2*4(%1), %3\n\t" memmove() 63 "mov 3*4(%1), %4\n\t" memmove() 64 "mov %3, 2*4(%2)\n\t" memmove() 65 "mov %4, 3*4(%2)\n\t" memmove() 77 "mov -4(%1, %0), %3\n\t" memmove() 81 "mov %3, (%4)\n\t" memmove() 88 "mov (%1), %3\n\t" memmove() 89 "mov %2, %4\n\t" memmove() 95 "mov %3,(%4)\n\t" memmove() 106 "mov %1, %3\n\t" memmove() 125 "mov -1*4(%1), %3\n\t" memmove() 126 "mov -2*4(%1), %4\n\t" memmove() 127 "mov %3, -1*4(%2)\n\t" memmove() 128 "mov %4, -2*4(%2)\n\t" memmove() 129 "mov -3*4(%1), %3\n\t" memmove() 130 "mov -4*4(%1), %4\n\t" memmove() 131 "mov %3, -3*4(%2)\n\t" memmove() 132 "mov %4, -4*4(%2)\n\t" memmove() 150 "mov 0*4(%1), %3\n\t" memmove() 151 "mov 1*4(%1), %4\n\t" memmove() 152 "mov -2*4(%1, %0), %5\n\t" memmove() 153 "mov -1*4(%1, %0), %1\n\t" memmove() 155 "mov %3, 0*4(%2)\n\t" memmove() 156 "mov %4, 1*4(%2)\n\t" memmove() 157 "mov %5, -2*4(%2, %0)\n\t" memmove() 158 "mov %1, -1*4(%2, %0)\n\t" memmove() 168 "mov 0*4(%1), %3\n\t" memmove() 169 "mov -1*4(%1, %0), %4\n\t" memmove() 170 "mov %3, 0*4(%2)\n\t" memmove() 171 "mov %4, -1*4(%2, %0)\n\t" memmove()
|
H A D | putuser.S | 52 mov TI_addr_limit(%_ASM_BX),%_ASM_BX 64 mov TI_addr_limit(%_ASM_BX),%_ASM_BX 76 mov TI_addr_limit(%_ASM_BX),%_ASM_BX 81 4: mov %_ASM_AX,(%_ASM_CX)
|
/linux-4.1.27/arch/sh/kernel/cpu/shmobile/ |
H A D | sleep.S | 34 mov.l r4, @(SH_SLEEP_MODE, r5) 38 mov.l r0, @(SH_SLEEP_VBR, r5) 45 mov.l r0, @(SH_SLEEP_SPC, r5) 49 mov.l r0, @(SH_SLEEP_SR, r5) 52 mov.l @(SH_SLEEP_MODE, r5), r0 57 mov.l r14, @-r15 58 mov.l r13, @-r15 59 mov.l r12, @-r15 60 mov.l r11, @-r15 61 mov.l r10, @-r15 62 mov.l r9, @-r15 63 mov.l r8, @-r15 66 mov.l rb_bit, r9 69 mov #0, r10 75 mov.l rb_bit, r10 77 mov #-1, r9 83 mov.l rb_bit, r9 86 mov #0, r10 91 mov.l r15, @(SH_SLEEP_SP, r5) 92 mov r5, r15 96 mov #SH_SLEEP_REG_STBCR, r0 99 mov.l @(SH_SLEEP_MODE, r5), r0 105 mov #SH_SLEEP_REG_PTEH, r0 108 mov #SH_SLEEP_REG_PTEL, r0 111 mov #SH_SLEEP_REG_TTB, r0 114 mov #SH_SLEEP_REG_TEA, r0 117 mov #SH_SLEEP_REG_MMUCR, r0 120 mov #SH_SLEEP_REG_PTEA, r0 123 mov #SH_SLEEP_REG_PASCR, r0 126 mov #SH_SLEEP_REG_IRMCR, r0 130 mov #SH_SLEEP_REG_MMUCR, r0 131 mov #4, r1 132 mov.l r1, @r0 137 mov #SH_SLEEP_REG_CCR, r0 140 mov #SH_SLEEP_REG_RAMCR, r0 143 mov #SH_SLEEP_REG_CCR, r0 144 mov #0, r1 145 mov.l r1, @r0 150 mov.l @(SH_SLEEP_MODE, r5), r0 154 mov.l @(SH_SLEEP_SF_PRE, r5), r0 159 mov.l @(SH_SLEEP_MODE, r5), r0 165 mov #0x80, r1 173 mov #SH_SLEEP_REG_BAR, r0 174 mov.l @(SH_SLEEP_RESUME, r5), r1 175 mov.l r1, @r0 179 mov #0x20, r1 187 mov #0x10, r1 192 mov #0x00, r1 197 mov #SH_SLEEP_REG_STBCR, r0 198 mov.l r1, @r0 206 mov.l @(r0, r5), r1 208 mov.l @r1, r1 210 mov.l r1, @(r0, r5) 217 mov.l @(r0, r5), r0 230 mov.l r7, @-r15 231 mov.l r6, @-r15 232 mov.l r5, @-r15 233 mov.l r4, @-r15 234 mov.l r3, @-r15 235 mov.l r2, @-r15 236 mov.l r1, @-r15 238 mov.l r0, @-r15 253 mov.l 1f, k0 260 mov.l @(SH_SLEEP_SR, k1), k0 267 mov.l @(SH_SLEEP_SPC, r5), r0 271 mov.l @(SH_SLEEP_VBR, r5), r0 275 mov.l @(SH_SLEEP_SR, r5), r0 279 mov.l @(SH_SLEEP_SP, r5), r15 283 mov #SH_SLEEP_REG_STBCR, r0 286 mov.l @(SH_SLEEP_MODE, r5), r0 290 mov.l @(SH_SLEEP_SF_POST, r5), r0 296 mov.l @(SH_SLEEP_MODE, r5), r0 302 mov #SH_SLEEP_REG_PTEH, r0 305 mov #SH_SLEEP_REG_PTEL, r0 308 mov #SH_SLEEP_REG_TTB, r0 311 mov #SH_SLEEP_REG_TEA, r0 314 mov #SH_SLEEP_REG_PTEA, r0 317 mov #SH_SLEEP_REG_PASCR, r0 320 mov #SH_SLEEP_REG_IRMCR, r0 323 mov #SH_SLEEP_REG_MMUCR, r0 328 mov #SH_SLEEP_REG_RAMCR, r0 332 mov #SH_SLEEP_REG_CCR, r0 338 mov.l @(SH_SLEEP_MODE, r5), r0 343 mov.l _rb_bit, r10 345 mov #-1, r9 351 mov.l _rb_bit, r9 354 mov #0, r10 360 mov.l @r15+, r8 361 mov.l @r15+, r9 362 mov.l @r15+, r10 363 mov.l @r15+, r11 364 mov.l @r15+, r12 365 mov.l @r15+, r13 366 mov.l @r15+, r14 375 mov.l @(r0, r5), r1 378 mov.l @(r0, r5), r0 379 mov.l r1, @r0 392 mov.l @r15+, r0 393 mov.l @r15+, r1 394 mov.l @r15+, r2 395 mov.l @r15+, r3 396 mov.l @r15+, r4 397 mov.l @r15+, r5 398 mov.l @r15+, r6 400 mov.l @r15+, r7
|
/linux-4.1.27/arch/m68k/ifpsp060/src/ |
H A D | itest.S | 61 mov.l %d1,-(%sp) 126 mov.l &0x2,EAMEM(%a6) 170 mov.l &0x99999999,%d2 171 mov.l &0x88888888,%d3 173 mov.w &0x0004,ICCR(%a6) 174 mov.w &0x0000,%cc 179 mov.w %cc,SCCR(%a6) 193 mov.l &0x77777777,%d1 194 mov.l &0x99999999,%d2 195 mov.l &0x00000000,%d3 197 mov.w &0x0004,ICCR(%a6) 198 mov.w &0x0000,%cc 203 mov.w %cc,SCCR(%a6) 217 mov.l &0x00000010,%d1 218 mov.l &0x66666666,%d2 220 mov.w &0x0000,ICCR(%a6) 221 mov.w &0x0000,%cc 226 mov.w %cc,SCCR(%a6) 228 mov.l &0x00000006,IREGS+0x8(%a6) 239 mov.l &0x55555555,%d1 240 mov.l &0x00000000,%d2 241 mov.l &0x00000003,%d3 243 mov.w &0x0000,ICCR(%a6) 244 mov.w &0x0000,%cc 249 mov.w %cc,SCCR(%a6) 251 mov.l &0x00000000,IREGS+0x8(%a6) 252 mov.l &0xffffffff,IREGS+0xc(%a6) 263 mov.l &0x40000000,%d1 264 mov.l &0x00000000,%d2 265 mov.l &0x00000004,%d3 267 mov.w &0x0000,ICCR(%a6) 268 mov.w &0x0000,%cc 273 mov.w %cc,SCCR(%a6) 275 mov.l &0x00000001,IREGS+0x8(%a6) 276 mov.l &0x00000000,IREGS+0xc(%a6) 287 mov.l &0xffffffff,%d1 288 mov.l &0x00000000,%d2 289 mov.l &0xffffffff,%d3 291 mov.w &0x0008,ICCR(%a6) 292 mov.w &0x0000,%cc 297 mov.w %cc,SCCR(%a6) 299 mov.l &0xfffffffe,IREGS+0x8(%a6) 300 mov.l &0x00000001,IREGS+0xc(%a6) 311 mov.l &0x80000000,%d1 312 mov.l &0x00000000,%d2 313 mov.l &0xffffffff,%d3 315 mov.w &0x00000,ICCR(%a6) 316 mov.w &0x0000,%cc 321 mov.w %cc,SCCR(%a6) 323 mov.l &0x00000000,IREGS+0x8(%a6) 324 mov.l &0x80000000,IREGS+0xc(%a6) 335 mov.l &0x80000000,%d1 336 mov.l &0x00000000,%d2 337 mov.l &0x00000001,%d3 339 mov.w &0x0008,ICCR(%a6) 340 mov.w &0x0000,%cc 345 mov.w %cc,SCCR(%a6) 347 mov.l &0xffffffff,IREGS+0x8(%a6) 348 mov.l &0x80000000,IREGS+0xc(%a6) 359 mov.l &0x00000001,%d1 360 mov.l &0x00000000,%d2 361 mov.l &0x80000000,%d3 363 mov.w &0x0008,ICCR(%a6) 364 mov.w &0x0000,%cc 369 mov.w %cc,SCCR(%a6) 371 mov.l &0xffffffff,IREGS+0x8(%a6) 372 mov.l &0x80000000,IREGS+0xc(%a6) 378 mov.l TESTCTR(%a6),%d1 397 mov.w &0xaaaa,%d0 401 mov.w &0x001f,ICCR(%a6) 402 mov.w &0x001f,%cc 407 mov.w %cc,SCCR(%a6) 410 mov.b 0x2(%a0),%d1 412 mov.b 0x0(%a0),%d1 430 mov.w &0xaaaa,%d0 435 mov.w &0x001f,ICCR(%a6) 436 mov.w &0x001f,%cc 441 mov.w %cc,SCCR(%a6) 465 mov.w &0xaaaa,%d0 469 mov.w &0x0000,ICCR(%a6) 470 mov.w &0x0000,%cc 475 mov.w %cc,SCCR(%a6) 478 mov.b 0x2(%a0),%d1 480 mov.b 0x0(%a0),%d1 498 mov.b &0xaa,0x0(%a0) 499 mov.b &0xaa,0x2(%a0) 501 mov.w &0x001f,ICCR(%a6) 502 mov.w &0x001f,%cc 507 mov.w %cc,SCCR(%a6) 509 mov.w &0xaaaa,IREGS+0x2(%a6) 511 mov.w &0xaaaa,%d1 529 mov.l &0xaaaaaaaa,%d0 535 mov.w &0x001f,ICCR(%a6) 536 mov.w &0x001f,%cc 541 mov.w %cc,SCCR(%a6) 544 mov.b 0x6(%a0),%d1 546 mov.b 0x4(%a0),%d1 548 mov.b 0x2(%a0),%d1 550 mov.b 0x0(%a0),%d1 568 mov.l &0xaaaaaaaa,%d0 574 mov.w &0x001f,ICCR(%a6) 575 mov.w &0x001f,%cc 580 mov.w %cc,SCCR(%a6) 605 mov.b &0xaa,0x0(%a0) 606 mov.b &0xaa,0x2(%a0) 607 mov.b &0xaa,0x4(%a0) 608 mov.b &0xaa,0x6(%a0) 610 mov.w &0x001f,ICCR(%a6) 611 mov.w &0x001f,%cc 616 mov.w %cc,SCCR(%a6) 618 mov.l &0xaaaaaaaa,IREGS(%a6) 620 mov.l &0xaaaaaaaa,%d1 638 mov.w &0xaaaa,%d7 642 mov.w &0x001f,ICCR(%a6) 643 mov.w &0x001f,%cc 648 mov.w %cc,SCCR(%a6) 651 mov.b 0x2(%a0),%d1 653 mov.b 0x0(%a0),%d1 671 mov.b &0xaa,0x0(%a0) 672 mov.b &0xaa,0x2(%a0) 674 mov.w &0x001f,ICCR(%a6) 675 mov.w &0x001f,%cc 680 mov.w %cc,SCCR(%a6) 682 mov.w &0xaaaa,IREGS+30(%a6) 684 mov.w &0xaaaa,%d1 702 mov.w &0xaaaa,%d0 706 mov.w &0x001f,ICCR(%a6) 707 mov.w &0x001f,%cc 712 mov.w %cc,SCCR(%a6) 715 mov.b 0x2(%a0),%d1 717 mov.b 0x0(%a0),%d1 735 mov.w &0xaaaa,%d0 739 mov.w &0x001f,ICCR(%a6) 740 mov.w &0x1f,%cc 745 mov.w %cc,SCCR(%a6) 748 mov.b 0x2+0x8(%a0),%d1 750 mov.b 0x0+0x8(%a0),%d1 768 mov.b &0xaa,0x0+0x8(%a0) 769 mov.b &0xaa,0x2+0x8(%a0) 771 mov.w &0x001f,ICCR(%a6) 772 mov.w &0x1f,%cc 777 mov.w %cc,SCCR(%a6) 779 mov.w &0xaaaa,IREGS+0x2(%a6) 781 mov.w &0xaaaa,%d1 799 mov.l &0xaaaaaaaa,%d0 805 mov.w &0x001f,ICCR(%a6) 806 mov.w &0x1f,%cc 811 mov.w %cc,SCCR(%a6) 814 mov.b 0x6+0x8(%a0),%d1 816 mov.b 0x4+0x8(%a0),%d1 818 mov.b 0x2+0x8(%a0),%d1 820 mov.b 0x0+0x8(%a0),%d1 838 mov.b &0xaa,0x0+0x8(%a0) 839 mov.b &0xaa,0x2+0x8(%a0) 840 mov.b &0xaa,0x4+0x8(%a0) 841 mov.b &0xaa,0x6+0x8(%a0) 843 mov.w &0x001f,ICCR(%a6) 844 mov.w &0x1f,%cc 849 mov.w %cc,SCCR(%a6) 851 mov.l &0xaaaaaaaa,IREGS(%a6) 853 mov.l &0xaaaaaaaa,%d1 871 mov.w &0xaaaa,%d0 875 mov.w &0x001f,ICCR(%a6) 876 mov.w &0x1f,%cc 881 mov.w %cc,SCCR(%a6) 884 mov.b 0x2-0x8(%a0),%d1 886 mov.b 0x0-0x8(%a0),%d1 904 mov.b &0xaa,0x0-0x8(%a0) 905 mov.b &0xaa,0x2-0x8(%a0) 907 mov.w &0x001f,ICCR(%a6) 908 mov.w &0x1f,%cc 913 mov.w %cc,SCCR(%a6) 915 mov.w &0xaaaa,IREGS+0x2(%a6) 917 mov.w &0xaaaa,%d1 935 mov.l &0xaaaaaaaa,%d0 941 mov.w &0x001f,ICCR(%a6) 942 mov.w &0x1f,%cc 947 mov.w %cc,SCCR(%a6) 950 mov.b 0x6-0x8(%a0),%d1 952 mov.b 0x4-0x8(%a0),%d1 954 mov.b 0x2-0x8(%a0),%d1 956 mov.b 0x0-0x8(%a0),%d1 974 mov.b &0xaa,0x0-0x8(%a0) 975 mov.b &0xaa,0x2-0x8(%a0) 976 mov.b &0xaa,0x4-0x8(%a0) 977 mov.b &0xaa,0x8-0x8(%a0) 979 mov.w &0x001f,ICCR(%a6) 980 mov.w &0x1f,%cc 985 mov.w %cc,SCCR(%a6) 987 mov.l &0xaaaaaaaa,IREGS(%a6) 989 mov.l &0xaaaaaaaa,%d1 998 mov.l TESTCTR(%a6),%d1 1014 # mov.l &0x99999999,%d2 1015 # mov.l &0x88888888,%d3 1017 # mov.w &0x001e,ICCR(%a6) 1018 # mov.w &0x001f,%cc 1023 # mov.w %cc,SCCR(%a6) 1035 mov.l &0x00000001,%d1 1036 mov.l &0x00000000,%d2 1037 mov.l &0x00000000,%d3 1039 mov.w &0x0014,ICCR(%a6) 1040 mov.w &0x001f,%cc 1045 mov.w %cc,SCCR(%a6) 1057 mov.l &0x44444444,%d1 1058 mov.l &0x00000000,%d2 1059 mov.l &0x55555555,%d3 1061 mov.w &0x0010,ICCR(%a6) 1062 mov.w &0x001f,%cc 1067 mov.w %cc,SCCR(%a6) 1069 mov.l &0x11111111,IREGS+0x8(%a6) 1070 mov.l &0x00000001,IREGS+0xc(%a6) 1081 mov.l &0x55555555,%d1 1082 mov.l &0x00000000,%d2 1083 mov.l &0x44444444,%d3 1085 mov.w &0x0014,ICCR(%a6) 1086 mov.w &0x001f,%cc 1091 mov.w %cc,SCCR(%a6) 1093 mov.l &0x44444444,IREGS+0x8(%a6) 1094 mov.l &0x00000000,IREGS+0xc(%a6) 1105 mov.l &0x11111111,%d1 1106 mov.l &0x44444444,%d2 1107 mov.l &0x44444444,%d3 1109 mov.w &0x001e,ICCR(%a6) 1110 mov.w &0x001d,%cc 1115 mov.w %cc,SCCR(%a6) 1127 mov.l &0xfffffffe,%d1 1128 mov.l &0x00000001,%d2 1129 mov.l &0x00000002,%d3 1131 mov.w &0x001e,ICCR(%a6) 1132 mov.w &0x001d,%cc 1137 mov.w %cc,SCCR(%a6) 1149 mov.l &0xfffffffe,%d1 1150 mov.l &0x00000001,%d2 1151 mov.l &0x00000000,%d3 1153 mov.w &0x0018,ICCR(%a6) 1154 mov.w &0x001d,%cc 1159 mov.w %cc,SCCR(%a6) 1161 mov.l &0x00000000,IREGS+0x8(%a6) 1162 mov.l &0x80000000,IREGS+0xc(%a6) 1173 mov.l &0x00000002,%d1 1174 mov.l &0x00000001,%d2 1175 mov.l &0x00000000,%d3 1177 mov.w &0x001e,ICCR(%a6) 1178 mov.w &0x001d,%cc 1183 mov.w %cc,SCCR(%a6) 1195 mov.l &0xffffffff,%d1 1196 mov.l &0xfffffffe,%d2 1197 mov.l &0xffffffff,%d3 1199 mov.w &0x0008,ICCR(%a6) 1200 mov.w &0x0000,%cc 1205 mov.w %cc,SCCR(%a6) 1217 mov.l &0xffffffff,%d1 1218 mov.l &0xfffffffe,%d2 1219 mov.l &0xffffffff,%d3 1221 mov.w &0x0008,ICCR(%a6) 1222 mov.w &0x0000,%cc 1227 mov.w %cc,SCCR(%a6) 1229 mov.l &0xffffffff,IREGS+0x8(%a6) 1240 mov.l &0x0000ffff,%d1 1241 mov.l &0x00000001,%d2 1242 mov.l &0x55555555,%d3 1244 mov.w &0x0000,ICCR(%a6) 1245 mov.w &0x0000,%cc 1250 mov.w %cc,SCCR(%a6) 1252 mov.l &0x0000aaab,IREGS+0x8(%a6) 1253 mov.l &0x00015556,IREGS+0xc(%a6) 1259 mov.l TESTCTR(%a6),%d1 1276 mov.w &0xaaaa,(%a0) 1278 mov.w &0xaaaa,%d1 1279 mov.w &0xbbbb,%d2 1281 mov.w &0x0014,ICCR(%a6) 1282 mov.w &0x0010,%cc 1287 mov.w %cc,SCCR(%a6) 1288 mov.w (%a0),%d3 1289 mov.w &0xbbbb,IREGS+0xc+0x2(%a6) 1303 mov.w &0xeeee,(%a0) 1305 mov.w &0x0000aaaa,%d1 1306 mov.w &0x0000bbbb,%d2 1308 mov.w &0x0000,ICCR(%a6) 1309 mov.w &0x0000,%cc 1314 mov.w %cc,SCCR(%a6) 1315 mov.w (%a0),%d3 1316 mov.w &0xeeee,IREGS+0x4+0x2(%a6) 1317 mov.w &0xeeee,IREGS+0xc+0x2(%a6) 1331 mov.l &0xaaaaaaaa,(%a0) 1333 mov.l &0xaaaaaaaa,%d1 1334 mov.l &0xbbbbbbbb,%d2 1336 mov.w &0x0004,ICCR(%a6) 1337 mov.w &0x0000,%cc 1342 mov.w %cc,SCCR(%a6) 1343 mov.l (%a0),%d3 1344 mov.l &0xbbbbbbbb,IREGS+0xc(%a6) 1358 mov.l &0xeeeeeeee,(%a0) 1360 mov.l &0xaaaaaaaa,%d1 1361 mov.l &0xbbbbbbbb,%d2 1363 mov.w &0x0000,ICCR(%a6) 1364 mov.w &0x0000,%cc 1369 mov.w %cc,SCCR(%a6) 1370 mov.l (%a0),%d3 1371 mov.l &0xeeeeeeee,IREGS+0x4(%a6) 1372 mov.l &0xeeeeeeee,IREGS+0xc(%a6) 1386 mov.l &0xaaaaaaaa,(%a0) 1388 mov.l &0xaaaaaaaa,%d1 1389 mov.l &0xbbbbbbbb,%d2 1391 mov.w &0x0004,ICCR(%a6) 1392 mov.w &0x0000,%cc 1397 mov.w %cc,SCCR(%a6) 1398 mov.l (%a0),%d3 1399 mov.l &0xbbbbbbbb,IREGS+0xc(%a6) 1413 mov.l &0x7fffffff,(%a0) 1415 mov.l &0x80000000,%d1 1416 mov.l &0xbbbbbbbb,%d2 1418 mov.w &0x001b,ICCR(%a6) 1419 mov.w &0x0010,%cc 1424 mov.w %cc,SCCR(%a6) 1425 mov.l (%a0),%d3 1426 mov.l &0x7fffffff,IREGS+0x4(%a6) 1427 mov.l &0x7fffffff,IREGS+0xc(%a6) 1434 mov.l TESTCTR(%a6),%d1 1452 mov.l &0xaaaaaaaa,(%a0) 1453 mov.l &0xbbbbbbbb,(%a1) 1455 mov.l &0xaaaaaaaa,%d1 1456 mov.l &0xbbbbbbbb,%d2 1457 mov.l &0xcccccccc,%d3 1458 mov.l &0xdddddddd,%d4 1460 mov.w &0x0014,ICCR(%a6) 1461 mov.w &0x0010,%cc 1466 mov.w %cc,SCCR(%a6) 1467 mov.l (%a0),%d5 1468 mov.l (%a1),%d6 1469 mov.l &0xcccccccc,IREGS+0x14(%a6) 1470 mov.l &0xdddddddd,IREGS+0x18(%a6) 1485 mov.l &0xaaaaaaaa,(%a0) 1486 mov.l &0xbbbbbbbb,(%a1) 1488 mov.l &0xaaaaaaaa,%d1 1489 mov.l &0xbbbbbbbb,%d2 1490 mov.l &0xcccccccc,%d3 1491 mov.l &0xdddddddd,%d4 1493 mov.w &0x0014,ICCR(%a6) 1494 mov.w &0x0010,%cc 1499 mov.w %cc,SCCR(%a6) 1500 mov.l (%a0),%d5 1501 mov.l (%a1),%d6 1502 mov.l &0xcccccccc,IREGS+0x14(%a6) 1503 mov.l &0xdddddddd,IREGS+0x18(%a6) 1518 mov.l &0xaaaaaaaa,(%a0) 1519 mov.l &0xbbbbbbbb,(%a1) 1521 mov.l &0xaaaaaaaa,%d1 1522 mov.l &0xbbbbbbbb,%d2 1523 mov.l &0xcccccccc,%d3 1524 mov.l &0xdddddddd,%d4 1526 mov.w &0x0014,ICCR(%a6) 1527 mov.w &0x0010,%cc 1532 mov.w %cc,SCCR(%a6) 1533 mov.l (%a0),%d5 1534 mov.l (%a1),%d6 1535 mov.l &0xcccccccc,IREGS+0x14(%a6) 1536 mov.l &0xdddddddd,IREGS+0x18(%a6) 1551 mov.l &0xeeeeeeee,(%a0) 1552 mov.l &0xbbbbbbbb,(%a1) 1554 mov.l &0xaaaaaaaa,%d1 1555 mov.l &0xbbbbbbbb,%d2 1556 mov.l &0xcccccccc,%d3 1557 mov.l &0xdddddddd,%d4 1559 mov.w &0x0000,ICCR(%a6) 1560 mov.w &0x0000,%cc 1565 mov.w %cc,SCCR(%a6) 1566 mov.l (%a0),%d5 1567 mov.l (%a1),%d6 1568 mov.l &0xeeeeeeee,IREGS+0x4(%a6) 1569 mov.l &0xbbbbbbbb,IREGS+0x8(%a6) 1570 mov.l &0xeeeeeeee,IREGS+0x14(%a6) 1571 mov.l &0xbbbbbbbb,IREGS+0x18(%a6) 1586 mov.l &0xeeeeeeee,(%a0) 1587 mov.l &0xbbbbbbbb,(%a1) 1589 mov.l &0xaaaaaaaa,%d1 1590 mov.l &0xbbbbbbbb,%d2 1591 mov.l &0xcccccccc,%d3 1592 mov.l &0xdddddddd,%d4 1594 mov.w &0x0000,ICCR(%a6) 1595 mov.w &0x0000,%cc 1600 mov.w %cc,SCCR(%a6) 1601 mov.l (%a0),%d5 1602 mov.l (%a1),%d6 1603 mov.l &0xeeeeeeee,IREGS+0x4(%a6) 1604 mov.l &0xbbbbbbbb,IREGS+0x8(%a6) 1605 mov.l &0xeeeeeeee,IREGS+0x14(%a6) 1606 mov.l &0xbbbbbbbb,IREGS+0x18(%a6) 1621 mov.l &0xeeeeeeee,(%a0) 1622 mov.l &0xbbbbbbbb,(%a1) 1624 mov.l &0xaaaaaaaa,%d1 1625 mov.l &0xbbbbbbbb,%d2 1626 mov.l &0xcccccccc,%d3 1627 mov.l &0xdddddddd,%d4 1629 mov.w &0x0000,ICCR(%a6) 1630 mov.w &0x0000,%cc 1635 mov.w %cc,SCCR(%a6) 1636 mov.l (%a0),%d5 1637 mov.l (%a1),%d6 1638 mov.l &0xeeeeeeee,IREGS+0x4(%a6) 1639 mov.l &0xbbbbbbbb,IREGS+0x8(%a6) 1640 mov.l &0xeeeeeeee,IREGS+0x14(%a6) 1641 mov.l &0xbbbbbbbb,IREGS+0x18(%a6) 1656 mov.l &0xaaaaaaaa,(%a0) 1657 mov.l &0xeeeeeeee,(%a1) 1659 mov.l &0xaaaaaaaa,%d1 1660 mov.l &0xbbbbbbbb,%d2 1661 mov.l &0xcccccccc,%d3 1662 mov.l &0xdddddddd,%d4 1664 mov.w &0x0000,ICCR(%a6) 1665 mov.w &0x0000,%cc 1670 mov.w %cc,SCCR(%a6) 1671 mov.l (%a0),%d5 1672 mov.l (%a1),%d6 1673 mov.l &0xaaaaaaaa,IREGS+0x4(%a6) 1674 mov.l &0xeeeeeeee,IREGS+0x8(%a6) 1675 mov.l &0xaaaaaaaa,IREGS+0x14(%a6) 1676 mov.l &0xeeeeeeee,IREGS+0x18(%a6) 1691 mov.l &0xaaaaaaaa,(%a0) 1692 mov.l &0xeeeeeeee,(%a1) 1694 mov.l &0xaaaaaaaa,%d1 1695 mov.l &0xbbbbbbbb,%d2 1696 mov.l &0xcccccccc,%d3 1697 mov.l &0xdddddddd,%d4 1699 mov.w &0x0000,ICCR(%a6) 1700 mov.w &0x0000,%cc 1705 mov.w %cc,SCCR(%a6) 1706 mov.l (%a0),%d5 1707 mov.l (%a1),%d6 1708 mov.l &0xaaaaaaaa,IREGS+0x4(%a6) 1709 mov.l &0xeeeeeeee,IREGS+0x8(%a6) 1710 mov.l &0xaaaaaaaa,IREGS+0x14(%a6) 1711 mov.l &0xeeeeeeee,IREGS+0x18(%a6) 1726 mov.l &0xaaaaaaaa,(%a0) 1727 mov.l &0x7fffffff,(%a1) 1729 mov.l &0xaaaaaaaa,%d1 1730 mov.l &0x80000000,%d2 1731 mov.l &0xcccccccc,%d3 1732 mov.l &0xdddddddd,%d4 1734 mov.w &0x000b,ICCR(%a6) 1735 mov.w &0x0000,%cc 1740 mov.w %cc,SCCR(%a6) 1741 mov.l (%a0),%d5 1742 mov.l (%a1),%d6 1743 mov.l &0xaaaaaaaa,IREGS+0x4(%a6) 1744 mov.l &0x7fffffff,IREGS+0x8(%a6) 1745 mov.l &0xaaaaaaaa,IREGS+0x14(%a6) 1746 mov.l &0x7fffffff,IREGS+0x18(%a6) 1762 mov.w &0xaaaa,(%a0) 1763 mov.w &0xbbbb,(%a1) 1765 mov.w &0xaaaa,%d1 1766 mov.w &0xbbbb,%d2 1767 mov.w &0xcccc,%d3 1768 mov.w &0xdddd,%d4 1770 mov.w &0x0014,ICCR(%a6) 1771 mov.w &0x0010,%cc 1776 mov.w %cc,SCCR(%a6) 1777 mov.w (%a0),%d5 1778 mov.w (%a1),%d6 1779 mov.w &0xcccc,IREGS+0x14+0x2(%a6) 1780 mov.w &0xdddd,IREGS+0x18+0x2(%a6) 1795 mov.w &0xaaaa,(%a0) 1796 mov.w &0xbbbb,(%a1) 1798 mov.w &0xaaaa,%d1 1799 mov.w &0xbbbb,%d2 1800 mov.w &0xcccc,%d3 1801 mov.w &0xdddd,%d4 1803 mov.w &0x0004,ICCR(%a6) 1804 mov.w &0x0000,%cc 1809 mov.w %cc,SCCR(%a6) 1810 mov.w (%a0),%d5 1811 mov.w (%a1),%d6 1812 mov.w &0xcccc,IREGS+0x14+0x2(%a6) 1813 mov.w &0xdddd,IREGS+0x18+0x2(%a6) 1828 mov.w &0xeeee,(%a0) 1829 mov.w &0xbbbb,(%a1) 1831 mov.w &0xaaaa,%d1 1832 mov.w &0xbbbb,%d2 1833 mov.w &0xcccc,%d3 1834 mov.w &0xdddd,%d4 1836 mov.w &0x0000,ICCR(%a6) 1837 mov.w &0x0000,%cc 1842 mov.w %cc,SCCR(%a6) 1843 mov.w (%a0),%d5 1844 mov.w (%a1),%d6 1845 mov.w &0xeeee,IREGS+0x4+0x2(%a6) 1846 mov.w &0xbbbb,IREGS+0x8+0x2(%a6) 1847 mov.w &0xeeee,IREGS+0x14+0x2(%a6) 1848 mov.w &0xbbbb,IREGS+0x18+0x2(%a6) 1863 mov.w &0xeeee,(%a0) 1864 mov.w &0xbbbb,(%a1) 1866 mov.w &0xaaaa,%d1 1867 mov.w &0xbbbb,%d2 1868 mov.w &0xcccc,%d3 1869 mov.w &0xdddd,%d4 1871 mov.w &0x0000,ICCR(%a6) 1872 mov.w &0x0000,%cc 1877 mov.w %cc,SCCR(%a6) 1878 mov.w (%a0),%d5 1879 mov.w (%a1),%d6 1880 mov.w &0xeeee,IREGS+0x4+0x2(%a6) 1881 mov.w &0xbbbb,IREGS+0x8+0x2(%a6) 1882 mov.w &0xeeee,IREGS+0x14+0x2(%a6) 1883 mov.w &0xbbbb,IREGS+0x18+0x2(%a6) 1898 mov.w &0xaaaa,(%a0) 1899 mov.w &0xeeee,(%a1) 1901 mov.w &0xaaaa,%d1 1902 mov.w &0xbbbb,%d2 1903 mov.w &0xcccc,%d3 1904 mov.w &0xdddd,%d4 1906 mov.w &0x0000,ICCR(%a6) 1907 mov.w &0x0000,%cc 1912 mov.w %cc,SCCR(%a6) 1913 mov.w (%a0),%d5 1914 mov.w (%a1),%d6 1915 mov.w &0xaaaa,IREGS+0x4+0x2(%a6) 1916 mov.w &0xeeee,IREGS+0x8+0x2(%a6) 1917 mov.w &0xaaaa,IREGS+0x14+0x2(%a6) 1918 mov.w &0xeeee,IREGS+0x18+0x2(%a6) 1933 mov.w &0xaaaa,(%a0) 1934 mov.w &0x7fff,(%a1) 1936 mov.w &0xaaaa,%d1 1937 mov.w &0x8000,%d2 1938 mov.w &0xcccc,%d3 1939 mov.w &0xdddd,%d4 1941 mov.w &0x001b,ICCR(%a6) 1942 mov.w &0x0010,%cc 1947 mov.w %cc,SCCR(%a6) 1948 mov.w (%a0),%d5 1949 mov.w (%a1),%d6 1950 mov.w &0xaaaa,IREGS+0x4+0x2(%a6) 1951 mov.w &0x7fff,IREGS+0x8+0x2(%a6) 1952 mov.w &0xaaaa,IREGS+0x14+0x2(%a6) 1953 mov.w &0x7fff,IREGS+0x18+0x2(%a6) 1960 mov.l TESTCTR(%a6),%d1 1976 mov.w &0x2040,DATA(%a6) 1977 mov.l &0x11111120,%d1 1979 mov.w &0x0004,ICCR(%a6) 1980 mov.w &0x0000,%cc 1985 mov.w %cc,SCCR(%a6) 1997 mov.w &0x2040,DATA(%a6) 1998 mov.l &0x00000040,%a1 2000 mov.w &0x0004,ICCR(%a6) 2001 mov.w &0x0000,%cc 2006 mov.w %cc,SCCR(%a6) 2018 mov.w &0x2040,DATA(%a6) 2019 mov.l &0x11111130,%d1 2021 mov.w &0x0000,ICCR(%a6) 2022 mov.w &0x0000,%cc 2027 mov.w %cc,SCCR(%a6) 2039 mov.w &0x2040,DATA(%a6) 2040 mov.l &0x00000010,%a1 2042 mov.w &0x0001,ICCR(%a6) 2043 mov.w &0x0000,%cc 2048 mov.w %cc,SCCR(%a6) 2060 mov.w &0x2040,DATA(%a6) 2061 mov.l &0x11111150,%d1 2063 mov.w &0x0001,ICCR(%a6) 2064 mov.w &0x0000,%cc 2069 mov.w %cc,SCCR(%a6) 2081 mov.w &0x2040,DATA(%a6) 2082 mov.l &0x00000090,%a1 2084 mov.w &0x0001,ICCR(%a6) 2085 mov.w &0x0000,%cc 2090 mov.w %cc,SCCR(%a6) 2103 mov.l &0x2000a000,DATA(%a6) 2104 mov.l &0x11112000,%d1 2106 mov.w &0x0004,ICCR(%a6) 2107 mov.w &0x0000,%cc 2112 mov.w %cc,SCCR(%a6) 2124 mov.l &0x2000a000,DATA(%a6) 2125 mov.l &0xffffa000,%a1 2127 mov.w &0x0004,ICCR(%a6) 2128 mov.w &0x0000,%cc 2133 mov.w %cc,SCCR(%a6) 2145 mov.l &0x2000a000,DATA(%a6) 2146 mov.l &0x11113000,%d1 2148 mov.w &0x0000,ICCR(%a6) 2149 mov.w &0x0000,%cc 2154 mov.w %cc,SCCR(%a6) 2166 mov.l &0x2000a000,DATA(%a6) 2167 mov.l &0xffff9000,%a1 2169 mov.w &0x0000,ICCR(%a6) 2170 mov.w &0x0000,%cc 2175 mov.w %cc,SCCR(%a6) 2187 mov.l &0x2000a000,DATA(%a6) 2188 mov.l &0x11111000,%d1 2190 mov.w &0x0001,ICCR(%a6) 2191 mov.w &0x0000,%cc 2196 mov.w %cc,SCCR(%a6) 2208 mov.l &0x2000a000,DATA(%a6) 2209 mov.l &0xffffb000,%a1 2211 mov.w &0x0001,ICCR(%a6) 2212 mov.w &0x0000,%cc 2217 mov.w %cc,SCCR(%a6) 2230 mov.l &0xa0000000,DATA(%a6) 2231 mov.l &0xc0000000,DATA+0x4(%a6) 2232 mov.l &0xa0000000,%d1 2234 mov.w &0x000c,ICCR(%a6) 2235 mov.w &0x0008,%cc 2240 mov.w %cc,SCCR(%a6) 2252 mov.l &0xa0000000,DATA(%a6) 2253 mov.l &0xc0000000,DATA+0x4(%a6) 2254 mov.l &0xc0000000,%a1 2256 mov.w &0x000c,ICCR(%a6) 2257 mov.w &0x0008,%cc 2262 mov.w %cc,SCCR(%a6) 2274 mov.l &0xa0000000,DATA(%a6) 2275 mov.l &0xc0000000,DATA+0x4(%a6) 2276 mov.l &0xb0000000,%d1 2278 mov.w &0x0008,ICCR(%a6) 2279 mov.w &0x0008,%cc 2284 mov.w %cc,SCCR(%a6) 2296 mov.l &0xa0000000,DATA(%a6) 2297 mov.l &0xc0000000,DATA+0x4(%a6) 2298 mov.l &0x10000000,%a1 2300 mov.w &0x0009,ICCR(%a6) 2301 mov.w &0x0008,%cc 2306 mov.w %cc,SCCR(%a6) 2318 mov.l &0xa0000000,DATA(%a6) 2319 mov.l &0xc0000000,DATA+0x4(%a6) 2320 mov.l &0x90000000,%d1 2322 mov.w &0x0009,ICCR(%a6) 2323 mov.w &0x0008,%cc 2328 mov.w %cc,SCCR(%a6) 2340 mov.l &0xa0000000,DATA(%a6) 2341 mov.l &0xc0000000,DATA+0x4(%a6) 2342 mov.l &0xd0000000,%a1 2344 mov.w &0x0009,ICCR(%a6) 2345 mov.w &0x0008,%cc 2350 mov.w %cc,SCCR(%a6) 2363 mov.w &0xa040,DATA(%a6) 2364 mov.l &0x111111a0,%d1 2366 mov.w &0x0004,ICCR(%a6) 2367 mov.w &0x0000,%cc 2372 mov.w %cc,SCCR(%a6) 2384 mov.w &0xa040,DATA(%a6) 2385 mov.l &0x00000040,%a1 2387 mov.w &0x0004,ICCR(%a6) 2388 mov.w &0x0000,%cc 2393 mov.w %cc,SCCR(%a6) 2405 mov.w &0xa040,DATA(%a6) 2406 mov.l &0x111111b0,%d1 2408 mov.w &0x0000,ICCR(%a6) 2409 mov.w &0x0000,%cc 2414 mov.w %cc,SCCR(%a6) 2426 mov.w &0xa040,DATA(%a6) 2427 mov.l &0x00000010,%a1 2429 mov.w &0x0000,ICCR(%a6) 2430 mov.w &0x0000,%cc 2435 mov.w %cc,SCCR(%a6) 2447 mov.w &0xa040,DATA(%a6) 2448 mov.l &0x11111190,%d1 2450 mov.w &0x0001,ICCR(%a6) 2451 mov.w &0x0000,%cc 2456 mov.w %cc,SCCR(%a6) 2468 mov.w &0xa040,DATA(%a6) 2469 mov.l &0x00000050,%a1 2471 mov.w &0x0001,ICCR(%a6) 2472 mov.w &0x0000,%cc 2477 mov.w %cc,SCCR(%a6) 2490 mov.w &0xa0c0,DATA(%a6) 2491 mov.l &0x111111a0,%d1 2493 mov.w &0x0004,ICCR(%a6) 2494 mov.w &0x0000,%cc 2499 mov.w %cc,SCCR(%a6) 2511 mov.w &0xa0c0,DATA(%a6) 2512 mov.l &0xffffffc0,%a1 2514 mov.w &0x0004,ICCR(%a6) 2515 mov.w &0x0000,%cc 2520 mov.w %cc,SCCR(%a6) 2532 mov.w &0xa0c0,DATA(%a6) 2533 mov.l &0x111111b0,%d1 2535 mov.w &0x0000,ICCR(%a6) 2536 mov.w &0x0000,%cc 2541 mov.w %cc,SCCR(%a6) 2553 mov.w &0xa0c0,DATA(%a6) 2554 mov.l &0x11111190,%a1 2556 mov.w &0x0001,ICCR(%a6) 2557 mov.w &0x0000,%cc 2562 mov.w %cc,SCCR(%a6) 2574 mov.w &0xa0c0,DATA(%a6) 2575 mov.l &0x111111d0,%d1 2577 mov.w &0x0001,ICCR(%a6) 2578 mov.w &0x0000,%cc 2583 mov.w %cc,SCCR(%a6) 2595 mov.w &0xa0c0,DATA(%a6) 2596 mov.l &0x00000050,%a1 2598 mov.w &0x001b,ICCR(%a6) 2599 mov.w &0x001f,%cc 2604 mov.w %cc,SCCR(%a6) 2611 mov.l TESTCTR(%a6),%d1 2627 mov.l &0x00000002,%d3 2630 mov.w &0x0000,ICCR(%a6) 2631 mov.w &0x0000,%cc 2636 mov.w %cc,SCCR(%a6) 2638 mov.l &0x00000004,IREGS+0xc(%a6) 2650 mov.l &0x00000002,%d3 2653 mov.w &0x0000,ICCR(%a6) 2654 mov.w &0x0000,%cc 2659 mov.w %cc,SCCR(%a6) 2661 mov.l &0x00000004,IREGS+0xc(%a6) 2663 mov.l %a0,IREGS+0x20(%a6) 2674 mov.l &0x00000002,%d3 2677 mov.w &0x0000,ICCR(%a6) 2678 mov.w &0x0000,%cc 2683 mov.w %cc,SCCR(%a6) 2685 mov.l &0x00000004,IREGS+0xc(%a6) 2687 mov.l %a0,IREGS+0x20(%a6) 2699 mov.l &0x00000002,%d3 2702 mov.w &0x0000,ICCR(%a6) 2703 mov.w &0x0000,%cc 2708 mov.w %cc,SCCR(%a6) 2710 mov.l &0x00000004,IREGS+0xc(%a6) 2722 mov.l &0x00000002,%d3 2725 mov.w &0x0000,ICCR(%a6) 2726 mov.w &0x0000,%cc 2731 mov.w %cc,SCCR(%a6) 2733 mov.l &0x00000004,IREGS+0xc(%a6) 2745 # mov.l &0x00000002,%d3 2747 # mov.w &0x0000,ICCR(%a6) 2748 # mov.w &0x0000,%cc 2753 # mov.w %cc,SCCR(%a6) 2755 # mov.l &0x00000004,IREGS+0xc(%a6) 2767 # mov.l &0x00000002,%d3 2769 # mov.w &0x0000,ICCR(%a6) 2770 # mov.w &0x0000,%cc 2775 # mov.w %cc,SCCR(%a6) 2777 # mov.l &0x00000004,IREGS+0xc(%a6) 2789 mov.l &0x00000002,%d3 2791 mov.w &0x0000,ICCR(%a6) 2792 mov.w &0x0000,%cc 2797 mov.w %cc,SCCR(%a6) 2799 mov.l &0x00000004,IREGS+0xc(%a6) 2815 mov.l &0x00000002,%d3 2817 mov.w &0x0000,ICCR(%a6) 2818 mov.w &0x0000,%cc 2823 mov.w %cc,SCCR(%a6) 2825 mov.l &0x00000004,IREGS+0xc(%a6) 2836 mov.l &0x00000002,%d3 2839 mov.w &0x0000,ICCR(%a6) 2840 mov.w &0x0000,%cc 2845 mov.w %cc,SCCR(%a6) 2847 mov.l &0x00000004,IREGS+0xc(%a6) 2849 mov.l %a0,IREGS+0x24(%a6) 2860 mov.l &0x00000002,%d3 2863 mov.w &0x0000,ICCR(%a6) 2864 mov.w &0x0000,%cc 2869 mov.w %cc,SCCR(%a6) 2871 mov.l &0x00000004,IREGS+0xc(%a6) 2873 mov.l %a0,IREGS+0x28(%a6) 2884 mov.l &0x00000002,%d3 2887 mov.w &0x0000,ICCR(%a6) 2888 mov.w &0x0000,%cc 2893 mov.w %cc,SCCR(%a6) 2895 mov.l &0x00000004,IREGS+0xc(%a6) 2897 mov.l %a0,IREGS+0x2c(%a6) 2908 mov.l &0x00000002,%d3 2911 mov.w &0x0000,ICCR(%a6) 2912 mov.w &0x0000,%cc 2917 mov.w %cc,SCCR(%a6) 2919 mov.l &0x00000004,IREGS+0xc(%a6) 2921 mov.l %a0,IREGS+0x30(%a6) 2932 mov.l &0x00000002,%d3 2935 mov.w &0x0000,ICCR(%a6) 2936 mov.w &0x0000,%cc 2941 mov.w %cc,SCCR(%a6) 2943 mov.l &0x00000004,IREGS+0xc(%a6) 2945 mov.l %a0,IREGS+0x34(%a6) 2956 mov.l %a6,%a1 2959 mov.l &0x00000002,%d3 2962 mov.w &0x0000,ICCR(%a1) 2963 mov.w &0x0000,%cc 2968 mov.w %cc,SCCR(%a1) 2970 mov.l &0x00000004,IREGS+0xc(%a1) 2972 mov.l %a0,IREGS+0x38(%a1) 2974 mov.l %a1,%a6 2985 mov.l &0x00000002,%d3 2986 mov.l %a7,%a0 2989 mov.w &0x0000,ICCR(%a6) 2990 mov.w &0x0000,%cc 2995 mov.w %cc,SCCR(%a6) 2997 mov.l &0x00000004,IREGS+0xc(%a6) 2999 mov.l %a1,IREGS+0x3c(%a6) 3001 mov.l %a0,%a7 3012 mov.l &0x00000002,%d3 3014 mov.l &-0x10,%d4 3016 mov.w &0x0000,ICCR(%a6) 3017 mov.w &0x0000,%cc 3022 mov.w %cc,SCCR(%a6) 3024 mov.l &0x00000004,IREGS+0xc(%a6) 3036 mov.l &0x00000002,%d3 3038 mov.l &-0x8,%d4 3040 mov.w &0x0000,ICCR(%a6) 3041 mov.w &0x0000,%cc 3046 mov.w %cc,SCCR(%a6) 3048 mov.l &0x00000004,IREGS+0xc(%a6) 3060 mov.l &0x00000002,%d3 3062 mov.l &-0x4,%d4 3064 mov.w &0x0000,ICCR(%a6) 3065 mov.w &0x0000,%cc 3070 mov.w %cc,SCCR(%a6) 3072 mov.l &0x00000004,IREGS+0xc(%a6) 3084 mov.l &0x00000002,%d3 3086 mov.l &-0x2,%d4 3088 mov.w &0x0000,ICCR(%a6) 3089 mov.w &0x0000,%cc 3094 mov.w %cc,SCCR(%a6) 3096 mov.l &0x00000004,IREGS+0xc(%a6) 3108 mov.l &0x00000002,%d3 3110 mov.l &-0x10,%d4 3112 mov.w &0x0000,ICCR(%a6) 3113 mov.w &0x0000,%cc 3118 mov.w %cc,SCCR(%a6) 3120 mov.l &0x00000004,IREGS+0xc(%a6) 3132 mov.l &0x00000002,%d3 3134 mov.l &-0x8,%d4 3136 mov.w &0x0000,ICCR(%a6) 3137 mov.w &0x0000,%cc 3142 mov.w %cc,SCCR(%a6) 3144 mov.l &0x00000004,IREGS+0xc(%a6) 3156 mov.l &0x00000002,%d3 3158 mov.l &-0x4,%d4 3160 mov.w &0x0000,ICCR(%a6) 3161 mov.w &0x0000,%cc 3166 mov.w %cc,SCCR(%a6) 3168 mov.l &0x00000004,IREGS+0xc(%a6) 3180 mov.l &0x00000002,%d3 3182 mov.l &-0x2,%d4 3184 mov.w &0x0000,ICCR(%a6) 3185 mov.w &0x0000,%cc 3190 mov.w %cc,SCCR(%a6) 3192 mov.l &0x00000004,IREGS+0xc(%a6) 3204 mov.l &0x00000002,%d3 3206 mov.l &-0x2,%a4 3208 mov.w &0x0000,ICCR(%a6) 3209 mov.w &0x0000,%cc 3214 mov.w %cc,SCCR(%a6) 3216 mov.l &0x00000004,IREGS+0xc(%a6) 3228 mov.l &0x00000002,%d3 3230 mov.l &0x2,%a4 3232 mov.w &0x0000,ICCR(%a6) 3233 mov.w &0x0000,%cc 3238 mov.w %cc,SCCR(%a6) 3240 mov.l &0x00000004,IREGS+0xc(%a6) 3252 mov.l &0x00000002,%d3 3254 mov.l &-0x10,%d4 3256 mov.w &0x0000,ICCR(%a6) 3257 mov.w &0x0000,%cc 3262 mov.w %cc,SCCR(%a6) 3264 mov.l &0x00000004,IREGS+0xc(%a6) 3276 mov.l &0x00000002,%d3 3278 mov.l &-0x10,%d4 3280 mov.w &0x0000,ICCR(%a6) 3281 mov.w &0x0000,%cc 3286 mov.w %cc,SCCR(%a6) 3288 mov.l &0x00000004,IREGS+0xc(%a6) 3300 mov.l &0x00000002,%d3 3302 mov.l &-0x10,%d4 3304 mov.w &0x0000,ICCR(%a6) 3305 mov.w &0x0000,%cc 3310 mov.w %cc,SCCR(%a6) 3312 mov.l &0x00000004,IREGS+0xc(%a6) 3324 mov.l &0x00000002,%d3 3326 mov.l &-0x10,%d4 3328 mov.w &0x0000,ICCR(%a6) 3329 mov.w &0x0000,%cc 3334 mov.w %cc,SCCR(%a6) 3336 mov.l &0x00000004,IREGS+0xc(%a6) 3348 mov.l &0x00000002,%d3 3350 mov.l &-0x10,%d4 3352 mov.w &0x0000,ICCR(%a6) 3353 mov.w &0x0000,%cc 3358 mov.w %cc,SCCR(%a6) 3360 mov.l &0x00000004,IREGS+0xc(%a6) 3371 mov.l %a6,%a1 3374 mov.l &0x00000002,%d3 3376 mov.l &-0x10,%d4 3378 mov.w &0x0000,ICCR(%a1) 3379 mov.w &0x0000,%cc 3384 mov.w %cc,SCCR(%a1) 3386 mov.l &0x00000004,IREGS+0xc(%a1) 3388 mov.l %a1,%a6 3400 mov.l &0x00000002,%d3 3401 mov.l %a7,%a0 3403 mov.l &-0x10,%d4 3405 mov.w &0x0000,ICCR(%a6) 3406 mov.w &0x0000,%cc 3411 mov.w %cc,SCCR(%a6) 3413 mov.l &0x00000004,IREGS+0xc(%a6) 3415 mov.l %a0,%a7 3426 mov.l &0x00000002,%d3 3429 mov.w &0x0000,ICCR(%a6) 3430 mov.w &0x0000,%cc 3435 mov.w %cc,SCCR(%a6) 3437 mov.l &0x00000004,IREGS+0xc(%a6) 3449 mov.l &0x00000002,%d3 3452 mov.w &0x0000,ICCR(%a6) 3453 mov.w &0x0000,%cc 3458 mov.w %cc,SCCR(%a6) 3460 mov.l &0x00000004,IREGS+0xc(%a6) 3472 mov.l &0x00000002,%d3 3475 mov.w &0x0000,ICCR(%a6) 3476 mov.w &0x0000,%cc 3481 mov.w %cc,SCCR(%a6) 3483 mov.l &0x00000004,IREGS+0xc(%a6) 3495 mov.l &0x00000002,%d3 3498 mov.w &0x0000,ICCR(%a6) 3499 mov.w &0x0000,%cc 3504 mov.w %cc,SCCR(%a6) 3506 mov.l &0x00000004,IREGS+0xc(%a6) 3518 mov.l &0x00000002,%d3 3521 mov.w &0x0000,ICCR(%a6) 3522 mov.w &0x0000,%cc 3527 mov.w %cc,SCCR(%a6) 3529 mov.l &0x00000004,IREGS+0xc(%a6) 3540 mov.l %a6,%a1 3543 mov.l &0x00000002,%d3 3546 mov.w &0x0000,ICCR(%a1) 3547 mov.w &0x0000,%cc 3552 mov.w %cc,SCCR(%a1) 3554 mov.l &0x00000004,IREGS+0xc(%a1) 3556 mov.l %a1,%a6 3568 mov.l &0x00000002,%d3 3569 mov.l %a7,%a0 3572 mov.w &0x0000,ICCR(%a6) 3573 mov.w &0x0000,%cc 3578 mov.w %cc,SCCR(%a6) 3580 mov.l &0x00000004,IREGS+0xc(%a6) 3582 mov.l %a0,%a7 3593 mov.l &0x00000002,%d3 3596 mov.w &0x0000,ICCR(%a6) 3597 mov.w &0x0000,%cc 3602 mov.w %cc,SCCR(%a6) 3604 mov.l &0x00000004,IREGS+0xc(%a6) 3606 mov.l %a0,IREGS+0x24(%a6) 3618 mov.l &0x00000002,%d3 3621 mov.w &0x0000,ICCR(%a6) 3622 mov.w &0x0000,%cc 3627 mov.w %cc,SCCR(%a6) 3629 mov.l &0x00000004,IREGS+0xc(%a6) 3631 mov.l %a0,IREGS+0x28(%a6) 3643 mov.l &0x00000002,%d3 3646 mov.w &0x0000,ICCR(%a6) 3647 mov.w &0x0000,%cc 3652 mov.w %cc,SCCR(%a6) 3654 mov.l &0x00000004,IREGS+0xc(%a6) 3656 mov.l %a0,IREGS+0x2c(%a6) 3668 mov.l &0x00000002,%d3 3671 mov.w &0x0000,ICCR(%a6) 3672 mov.w &0x0000,%cc 3677 mov.w %cc,SCCR(%a6) 3679 mov.l &0x00000004,IREGS+0xc(%a6) 3681 mov.l %a0,IREGS+0x30(%a6) 3693 mov.l &0x00000002,%d3 3696 mov.w &0x0000,ICCR(%a6) 3697 mov.w &0x0000,%cc 3702 mov.w %cc,SCCR(%a6) 3704 mov.l &0x00000004,IREGS+0xc(%a6) 3706 mov.l %a0,IREGS+0x34(%a6) 3717 mov.l %a6,%a1 3720 mov.l &0x00000002,%d3 3723 mov.w &0x0000,ICCR(%a1) 3724 mov.w &0x0000,%cc 3729 mov.w %cc,SCCR(%a1) 3731 mov.l &0x00000004,IREGS+0xc(%a1) 3733 mov.l %a0,IREGS+0x38(%a1) 3735 mov.l %a1,%a6 3747 mov.l &0x00000002,%d3 3748 mov.l %a7,%a0 3751 mov.w &0x0000,ICCR(%a6) 3752 mov.w &0x0000,%cc 3757 mov.w %cc,SCCR(%a6) 3759 mov.l &0x00000004,IREGS+0xc(%a6) 3761 mov.l %a1,IREGS+0x3c(%a6) 3763 mov.l %a0,%a7 3774 mov.l &0x00000002,%d3 3777 mov.w &0x0000,ICCR(%a6) 3778 mov.w &0x0000,%cc 3783 mov.w %cc,SCCR(%a6) 3785 mov.l &0x00000004,IREGS+0xc(%a6) 3797 mov.l &0x00000002,%d3 3800 mov.w &0x0000,ICCR(%a6) 3801 mov.w &0x0000,%cc 3806 mov.w %cc,SCCR(%a6) 3808 mov.l &0x00000004,IREGS+0xc(%a6) 3820 mov.l &0x00000002,%d3 3823 mov.w &0x0000,ICCR(%a6) 3824 mov.w &0x0000,%cc 3829 mov.w %cc,SCCR(%a6) 3831 mov.l &0x00000004,IREGS+0xc(%a6) 3843 mov.l &0x00000002,%d3 3846 mov.w &0x0000,ICCR(%a6) 3847 mov.w &0x0000,%cc 3852 mov.w %cc,SCCR(%a6) 3854 mov.l &0x00000004,IREGS+0xc(%a6) 3866 mov.l &0x00000002,%d3 3869 mov.w &0x0000,ICCR(%a6) 3870 mov.w &0x0000,%cc 3875 mov.w %cc,SCCR(%a6) 3877 mov.l &0x00000004,IREGS+0xc(%a6) 3888 mov.l %a6,%a1 3891 mov.l &0x00000002,%d3 3894 mov.w &0x0000,ICCR(%a1) 3895 mov.w &0x0000,%cc 3900 mov.w %cc,SCCR(%a1) 3902 mov.l &0x00000004,IREGS+0xc(%a1) 3904 mov.l %a1,%a6 3916 mov.l &0x00000002,%d3 3917 mov.l %a7,%a0 3920 mov.w &0x0000,ICCR(%a6) 3921 mov.w &0x0000,%cc 3926 mov.w %cc,SCCR(%a6) 3928 mov.l &0x00000004,IREGS+0xc(%a6) 3930 mov.l %a0,%a7 3941 mov.l &0x00000002,%d3 3944 mov.w &0x0000,ICCR(%a6) 3945 mov.w &0x0000,%cc 3950 mov.w %cc,SCCR(%a6) 3952 mov.l &0x00000004,IREGS+0xc(%a6) 3969 mov.l &0x00000002,%d3 3971 mov.w &0x0000,ICCR(%a6) 3972 mov.w &0x0000,%cc 3977 mov.w %cc,SCCR(%a6) 3979 mov.l &0x00000004,IREGS+0xc(%a6) 3991 mov.l &0x00000002,%d3 3993 mov.l &-0x10,%d4 3995 mov.w &0x0000,ICCR(%a6) 3996 mov.w &0x0000,%cc 4001 mov.w %cc,SCCR(%a6) 4003 mov.l &0x00000004,IREGS+0xc(%a6) 4015 mov.l &0x00000002,%d3 4017 mov.l &-0x8,%d4 4019 mov.w &0x0000,ICCR(%a6) 4020 mov.w &0x0000,%cc 4025 mov.w %cc,SCCR(%a6) 4027 mov.l &0x00000004,IREGS+0xc(%a6) 4039 mov.l &0x00000002,%d3 4041 mov.l &-0x4,%d4 4043 mov.w &0x0000,ICCR(%a6) 4044 mov.w &0x0000,%cc 4049 mov.w %cc,SCCR(%a6) 4051 mov.l &0x00000004,IREGS+0xc(%a6) 4063 mov.l &0x00000002,%d3 4065 mov.l &-0x2,%d4 4067 mov.w &0x0000,ICCR(%a6) 4068 mov.w &0x0000,%cc 4073 mov.w %cc,SCCR(%a6) 4075 mov.l &0x00000004,IREGS+0xc(%a6) 4087 mov.l &0x00000002,%d3 4089 mov.l &-0x10,%d4 4091 mov.w &0x0000,ICCR(%a6) 4092 mov.w &0x0000,%cc 4097 mov.w %cc,SCCR(%a6) 4099 mov.l &0x00000004,IREGS+0xc(%a6) 4111 mov.l &0x00000002,%d3 4113 mov.l &-0x8,%d4 4115 mov.w &0x0000,ICCR(%a6) 4116 mov.w &0x0000,%cc 4121 mov.w %cc,SCCR(%a6) 4123 mov.l &0x00000004,IREGS+0xc(%a6) 4135 mov.l &0x00000002,%d3 4137 mov.l &-0x4,%d4 4139 mov.w &0x0000,ICCR(%a6) 4140 mov.w &0x0000,%cc 4145 mov.w %cc,SCCR(%a6) 4147 mov.l &0x00000004,IREGS+0xc(%a6) 4159 mov.l &0x00000002,%d3 4161 mov.l &-0x2,%d4 4163 mov.w &0x0000,ICCR(%a6) 4164 mov.w &0x0000,%cc 4169 mov.w %cc,SCCR(%a6) 4171 mov.l &0x00000004,IREGS+0xc(%a6) 4183 mov.l &0x00000002,%d3 4185 mov.l &0x2,%a4 4187 mov.w &0x0000,ICCR(%a6) 4188 mov.w &0x0000,%cc 4193 mov.w %cc,SCCR(%a6) 4195 mov.l &0x00000004,IREGS+0xc(%a6) 4207 mov.l &0x00000002,%d3 4209 mov.l &0x2,%a4 4211 mov.w &0x0000,ICCR(%a6) 4212 mov.w &0x0000,%cc 4217 mov.w %cc,SCCR(%a6) 4219 mov.l &0x00000004,IREGS+0xc(%a6) 4231 mov.l &0x00000002,%d3 4233 mov.l %a3,%a4 4236 mov.w &0x0000,ICCR(%a6) 4237 mov.w &0x0000,%cc 4242 mov.w %cc,SCCR(%a6) 4244 mov.l &0x00000004,IREGS+0xc(%a6) 4256 mov.l &0x00000002,%d3 4258 mov.l &0x2,%a4 4260 mov.w &0x0000,ICCR(%a6) 4261 mov.w &0x0000,%cc 4266 mov.w %cc,SCCR(%a6) 4268 mov.l &0x00000004,IREGS+0xc(%a6) 4284 mov.l &0x00000002,%d3 4286 mov.l &-0x10,%d4 4288 mov.w &0x0000,ICCR(%a6) 4289 mov.w &0x0000,%cc 4294 mov.w %cc,SCCR(%a6) 4296 mov.l &0x00000004,IREGS+0xc(%a6) 4312 mov.l &0x00000002,%d3 4314 mov.l &-0x8,%d4 4316 mov.w &0x0000,ICCR(%a6) 4317 mov.w &0x0000,%cc 4322 mov.w %cc,SCCR(%a6) 4324 mov.l &0x00000004,IREGS+0xc(%a6) 4340 mov.l &0x00000002,%d3 4342 mov.l &-0x4,%d4 4344 mov.w &0x0000,ICCR(%a6) 4345 mov.w &0x0000,%cc 4350 mov.w %cc,SCCR(%a6) 4352 mov.l &0x00000004,IREGS+0xc(%a6) 4368 mov.l &0x00000002,%d3 4370 mov.l &-0x2,%d4 4372 mov.w &0x0000,ICCR(%a6) 4373 mov.w &0x0000,%cc 4378 mov.w %cc,SCCR(%a6) 4380 mov.l &0x00000004,IREGS+0xc(%a6) 4396 mov.l &0x00000002,%d3 4398 mov.l &-0x10,%d4 4400 mov.w &0x0000,ICCR(%a6) 4401 mov.w &0x0000,%cc 4406 mov.w %cc,SCCR(%a6) 4408 mov.l &0x00000004,IREGS+0xc(%a6) 4424 mov.l &0x00000002,%d3 4426 mov.l &-0x8,%d4 4428 mov.w &0x0000,ICCR(%a6) 4429 mov.w &0x0000,%cc 4434 mov.w %cc,SCCR(%a6) 4436 mov.l &0x00000004,IREGS+0xc(%a6) 4452 mov.l &0x00000002,%d3 4454 mov.l &-0x4,%d4 4456 mov.w &0x0000,ICCR(%a6) 4457 mov.w &0x0000,%cc 4462 mov.w %cc,SCCR(%a6) 4464 mov.l &0x00000004,IREGS+0xc(%a6) 4480 mov.l &0x00000002,%d3 4482 mov.l &-0x2,%d4 4484 mov.w &0x0000,ICCR(%a6) 4485 mov.w &0x0000,%cc 4490 mov.w %cc,SCCR(%a6) 4492 mov.l &0x00000004,IREGS+0xc(%a6) 4508 mov.l &0x00000002,%d3 4510 mov.l &-0x2,%a4 4512 mov.w &0x0000,ICCR(%a6) 4513 mov.w &0x0000,%cc 4518 mov.w %cc,SCCR(%a6) 4520 mov.l &0x00000004,IREGS+0xc(%a6) 4536 mov.l &0x00000002,%d3 4538 mov.l &0x2,%a4 4540 mov.w &0x0000,ICCR(%a6) 4541 mov.w &0x0000,%cc 4546 mov.w %cc,SCCR(%a6) 4548 mov.l &0x00000004,IREGS+0xc(%a6) 4560 # mov.l &0x00000002,%d3 4562 # mov.l %a3,%a4 4565 # mov.w &0x0000,ICCR(%a6) 4566 # mov.w &0x0000,%cc 4571 # mov.w %cc,SCCR(%a6) 4573 # mov.l &0x00000004,IREGS+0xc(%a6) 4585 mov.l &0x00000002,%d3 4587 mov.l &0x2,%a4 4589 mov.w &0x0000,ICCR(%a6) 4590 mov.w &0x0000,%cc 4595 mov.w %cc,SCCR(%a6) 4597 mov.l &0x00000004,IREGS+0xc(%a6) 4618 mov.l &0x00000002,%d3 4620 mov.l &-0x10,%d4 4622 mov.w &0x0000,ICCR(%a6) 4623 mov.w &0x0000,%cc 4628 mov.w %cc,SCCR(%a6) 4630 mov.l &0x00000004,IREGS+0xc(%a6) 4646 mov.l &0x00000002,%d3 4648 mov.l &-0x8,%d4 4650 mov.w &0x0000,ICCR(%a6) 4651 mov.w &0x0000,%cc 4656 mov.w %cc,SCCR(%a6) 4658 mov.l &0x00000004,IREGS+0xc(%a6) 4674 mov.l &0x00000002,%d3 4676 mov.l &-0x4,%d4 4678 mov.w &0x0000,ICCR(%a6) 4679 mov.w &0x0000,%cc 4684 mov.w %cc,SCCR(%a6) 4686 mov.l &0x00000004,IREGS+0xc(%a6) 4702 mov.l &0x00000002,%d3 4704 mov.l &-0x2,%d4 4706 mov.w &0x0000,ICCR(%a6) 4707 mov.w &0x0000,%cc 4712 mov.w %cc,SCCR(%a6) 4714 mov.l &0x00000004,IREGS+0xc(%a6) 4730 mov.l &0x00000002,%d3 4732 mov.l &-0x10,%d4 4734 mov.w &0x0000,ICCR(%a6) 4735 mov.w &0x0000,%cc 4740 mov.w %cc,SCCR(%a6) 4742 mov.l &0x00000004,IREGS+0xc(%a6) 4758 mov.l &0x00000002,%d3 4760 mov.l &-0x8,%d4 4762 mov.w &0x0000,ICCR(%a6) 4763 mov.w &0x0000,%cc 4768 mov.w %cc,SCCR(%a6) 4770 mov.l &0x00000004,IREGS+0xc(%a6) 4786 mov.l &0x00000002,%d3 4788 mov.l &-0x4,%d4 4790 mov.w &0x0000,ICCR(%a6) 4791 mov.w &0x0000,%cc 4796 mov.w %cc,SCCR(%a6) 4798 mov.l &0x00000004,IREGS+0xc(%a6) 4814 mov.l &0x00000002,%d3 4816 mov.l &-0x2,%d4 4818 mov.w &0x0000,ICCR(%a6) 4819 mov.w &0x0000,%cc 4824 mov.w %cc,SCCR(%a6) 4826 mov.l &0x00000004,IREGS+0xc(%a6) 4838 mov.l &0x00000002,%d3 4840 mov.l &-0x2,%d4 4842 mov.w &0x0000,ICCR(%a6) 4843 mov.w &0x0000,%cc 4848 mov.w %cc,SCCR(%a6) 4850 mov.l &0x00000004,IREGS+0xc(%a6) 4867 mov.l &0x00000002,%d3 4870 mov.l %a3,(%a4) 4871 mov.l &-0x10,%d4 4873 mov.w &0x0000,ICCR(%a6) 4874 mov.w &0x0000,%cc 4879 mov.w %cc,SCCR(%a6) 4881 mov.l &0x00000004,IREGS+0xc(%a6) 4893 mov.l &0x00000002,%d3 4896 mov.l %a3,(%a4) 4897 mov.l &-0x8,%d4 4899 mov.w &0x0000,ICCR(%a6) 4900 mov.w &0x0000,%cc 4905 mov.w %cc,SCCR(%a6) 4907 mov.l &0x00000004,IREGS+0xc(%a6) 4919 mov.l &0x00000002,%d3 4922 mov.l %a3,(%a4) 4923 mov.l &-0x4,%d4 4925 mov.w &0x0000,ICCR(%a6) 4926 mov.w &0x0000,%cc 4931 mov.w %cc,SCCR(%a6) 4933 mov.l &0x00000004,IREGS+0xc(%a6) 4945 mov.l &0x00000002,%d3 4948 mov.l %a3,(%a4) 4949 mov.l &-0x2,%d4 4951 mov.w &0x0000,ICCR(%a6) 4952 mov.w &0x0000,%cc 4957 mov.w %cc,SCCR(%a6) 4959 mov.l &0x00000004,IREGS+0xc(%a6) 4971 mov.l &0x00000002,%d3 4974 mov.l %a3,(%a4) 4975 mov.l &-0x10,%d4 4977 mov.w &0x0000,ICCR(%a6) 4978 mov.w &0x0000,%cc 4983 mov.w %cc,SCCR(%a6) 4985 mov.l &0x00000004,IREGS+0xc(%a6) 4997 mov.l &0x00000002,%d3 5000 mov.l %a3,(%a4) 5001 mov.l &-0x8,%d4 5003 mov.w &0x0000,ICCR(%a6) 5004 mov.w &0x0000,%cc 5009 mov.w %cc,SCCR(%a6) 5011 mov.l &0x00000004,IREGS+0xc(%a6) 5023 mov.l &0x00000002,%d3 5026 mov.l %a3,(%a4) 5027 mov.l &-0x4,%d4 5029 mov.w &0x0000,ICCR(%a6) 5030 mov.w &0x0000,%cc 5035 mov.w %cc,SCCR(%a6) 5037 mov.l &0x00000004,IREGS+0xc(%a6) 5049 mov.l &0x00000002,%d3 5052 mov.l %a3,(%a4) 5053 mov.l &-0x2,%d4 5055 mov.w &0x0000,ICCR(%a6) 5056 mov.w &0x0000,%cc 5061 mov.w %cc,SCCR(%a6) 5063 mov.l &0x00000004,IREGS+0xc(%a6) 5075 mov.l &0x00000002,%d3 5078 mov.l %a3,(%a4) 5079 mov.l &-0x2,%d4 5081 mov.w &0x0000,ICCR(%a6) 5082 mov.w &0x0000,%cc 5087 mov.w %cc,SCCR(%a6) 5089 mov.l &0x00000004,IREGS+0xc(%a6) 5101 mov.l &0x00000002,%d3 5104 mov.l %a3,(%a4) 5105 mov.l &-0x2,%d4 5107 mov.w &0x0000,ICCR(%a6) 5108 mov.w &0x0000,%cc 5113 mov.w %cc,SCCR(%a6) 5115 mov.l &0x00000004,IREGS+0xc(%a6) 5127 mov.l &0x00000002,%d3 5130 mov.l %a3,(%a4) 5131 mov.l &-0x2,%d4 5133 mov.w &0x0000,ICCR(%a6) 5134 mov.w &0x0000,%cc 5139 mov.w %cc,SCCR(%a6) 5141 mov.l &0x00000004,IREGS+0xc(%a6) 5153 mov.l &0x00000002,%d3 5156 mov.l %a3,(%a4) 5157 mov.l &-0x10,%d4 5160 mov.w &0x0000,ICCR(%a6) 5161 mov.w &0x0000,%cc 5166 mov.w %cc,SCCR(%a6) 5168 mov.l &0x00000004,IREGS+0xc(%a6) 5180 # mov.l &0x00000002,%d3 5183 # mov.l %a3,(%a4) 5184 # mov.l &-0x10,%d4 5186 # mov.w &0x0000,ICCR(%a6) 5187 # mov.w &0x0000,%cc 5192 # mov.w %cc,SCCR(%a6) 5194 # mov.l &0x00000004,IREGS+0xc(%a6) 5205 mov.l %a6,%a1 5208 mov.l &0x00000002,%d3 5211 mov.l %a3,(%a4) 5212 mov.l &-0x2,%a6 5214 mov.w &0x0000,ICCR(%a1) 5215 mov.w &0x0000,%cc 5220 mov.w %cc,SCCR(%a1) 5222 mov.l &0x00000004,IREGS+0xc(%a1) 5224 mov.l %a1,%a6 5235 mov.l %a6,%a1 5238 mov.l &0x00000002,%d3 5241 mov.l %a3,(%a4) 5242 mov.l &0x2,%a6 5244 mov.w &0x0000,ICCR(%a1) 5245 mov.w &0x0000,%cc 5250 mov.w %cc,SCCR(%a1) 5252 mov.l &0x00000004,IREGS+0xc(%a1) 5254 mov.l %a1,%a6 5266 mov.l &0x00000002,%d3 5269 mov.l %a3,(%a4) 5271 mov.l &0x10,%d4 5273 mov.w &0x0000,ICCR(%a6) 5274 mov.w &0x0000,%cc 5279 mov.w %cc,SCCR(%a6) 5281 mov.l &0x00000004,IREGS+0xc(%a6) 5293 mov.l &0x00000002,%d3 5296 mov.l %a3,(%a4) 5298 mov.l &0x8,%d4 5300 mov.w &0x0000,ICCR(%a6) 5301 mov.w &0x0000,%cc 5306 mov.w %cc,SCCR(%a6) 5308 mov.l &0x00000004,IREGS+0xc(%a6) 5320 mov.l &0x00000002,%d3 5323 mov.l %a3,(%a4) 5325 mov.l &0x4,%d4 5327 mov.w &0x0000,ICCR(%a6) 5328 mov.w &0x0000,%cc 5333 mov.w %cc,SCCR(%a6) 5335 mov.l &0x00000004,IREGS+0xc(%a6) 5347 mov.l &0x00000002,%d3 5350 mov.l %a3,(%a4) 5352 mov.l &0x2,%d4 5354 mov.w &0x0000,ICCR(%a6) 5355 mov.w &0x0000,%cc 5360 mov.w %cc,SCCR(%a6) 5362 mov.l &0x00000004,IREGS+0xc(%a6) 5374 mov.l &0x00000002,%d3 5377 mov.l %a3,(%a4) 5379 mov.l &0x10,%d4 5381 mov.w &0x0000,ICCR(%a6) 5382 mov.w &0x0000,%cc 5387 mov.w %cc,SCCR(%a6) 5389 mov.l &0x00000004,IREGS+0xc(%a6) 5401 mov.l &0x00000002,%d3 5404 mov.l %a3,(%a4) 5406 mov.l &0x8,%d4 5408 mov.w &0x0000,ICCR(%a6) 5409 mov.w &0x0000,%cc 5414 mov.w %cc,SCCR(%a6) 5416 mov.l &0x00000004,IREGS+0xc(%a6) 5428 mov.l &0x00000002,%d3 5431 mov.l %a3,(%a4) 5433 mov.l &0x4,%d4 5435 mov.w &0x0000,ICCR(%a6) 5436 mov.w &0x0000,%cc 5441 mov.w %cc,SCCR(%a6) 5443 mov.l &0x00000004,IREGS+0xc(%a6) 5455 mov.l &0x00000002,%d3 5458 mov.l %a3,(%a4) 5460 mov.l &0x2,%d4 5462 mov.w &0x0000,ICCR(%a6) 5463 mov.w &0x0000,%cc 5468 mov.w %cc,SCCR(%a6) 5470 mov.l &0x00000004,IREGS+0xc(%a6) 5482 mov.l &0x00000002,%d3 5485 mov.l %a3,(%a4) 5487 mov.l &0x2,%d4 5489 mov.w &0x0000,ICCR(%a6) 5490 mov.w &0x0000,%cc 5495 mov.w %cc,SCCR(%a6) 5497 mov.l &0x00000004,IREGS+0xc(%a6) 5509 mov.l &0x00000002,%d3 5512 mov.l %a3,(%a4) 5513 mov.l &0x2,%d4 5515 mov.w &0x0000,ICCR(%a6) 5516 mov.w &0x0000,%cc 5521 mov.w %cc,SCCR(%a6) 5523 mov.l &0x00000004,IREGS+0xc(%a6) 5534 mov.l %a7,%a0 5536 mov.l &0x00000002,%d3 5539 mov.l %a3,(%a7) 5540 mov.l &0x20,%d4 5542 mov.w &0x0000,ICCR(%a6) 5543 mov.w &0x0000,%cc 5548 mov.w %cc,SCCR(%a6) 5550 mov.l &0x00000004,IREGS+0xc(%a6) 5552 mov.l %a0,%a7 5563 # mov.l &0x00000002,%d3 5566 # mov.l %a3,(%a4) 5567 # mov.l &0x2,%d4 5569 # mov.w &0x0000,ICCR(%a6) 5570 # mov.w &0x0000,%cc 5575 # mov.w %cc,SCCR(%a6) 5577 # mov.l &0x00000004,IREGS+0xc(%a6) 5588 mov.l %a6,%a1 5591 mov.l &0x00000002,%d3 5594 mov.l %a3,(%a6) 5596 mov.l &-0x2,%a5 5598 mov.w &0x0000,ICCR(%a1) 5599 mov.w &0x0000,%cc 5604 mov.w %cc,SCCR(%a1) 5606 mov.l &0x00000004,IREGS+0xc(%a1) 5608 mov.l %a1,%a6 5614 mov.l TESTCTR(%a6),%d1 5624 mov.l &0x00000002,%d3 5627 mov.l %a3,(%a4) 5628 mov.l &-0x10,%d4 5630 mov.w &0x0000,ICCR(%a6) 5631 mov.w &0x0000,%cc 5636 mov.w %cc,SCCR(%a6) 5638 mov.l &0x00000004,IREGS+0xc(%a6) 5650 mov.l &0x00000002,%d3 5653 mov.l %a3,(%a4) 5654 mov.l &-0x8,%d4 5656 mov.w &0x0000,ICCR(%a6) 5657 mov.w &0x0000,%cc 5662 mov.w %cc,SCCR(%a6) 5664 mov.l &0x00000004,IREGS+0xc(%a6) 5676 mov.l &0x00000002,%d3 5679 mov.l %a3,(%a4) 5680 mov.l &-0x4,%d4 5682 mov.w &0x0000,ICCR(%a6) 5683 mov.w &0x0000,%cc 5688 mov.w %cc,SCCR(%a6) 5690 mov.l &0x00000004,IREGS+0xc(%a6) 5702 mov.l &0x00000002,%d3 5705 mov.l %a3,(%a4) 5706 mov.l &-0x2,%d4 5708 mov.w &0x0000,ICCR(%a6) 5709 mov.w &0x0000,%cc 5714 mov.w %cc,SCCR(%a6) 5716 mov.l &0x00000004,IREGS+0xc(%a6) 5728 mov.l &0x00000002,%d3 5731 mov.l %a3,(%a4) 5732 mov.l &-0x10,%d4 5734 mov.w &0x0000,ICCR(%a6) 5735 mov.w &0x0000,%cc 5740 mov.w %cc,SCCR(%a6) 5742 mov.l &0x00000004,IREGS+0xc(%a6) 5754 mov.l &0x00000002,%d3 5757 mov.l %a3,(%a4) 5758 mov.l &-0x8,%d4 5760 mov.w &0x0000,ICCR(%a6) 5761 mov.w &0x0000,%cc 5766 mov.w %cc,SCCR(%a6) 5768 mov.l &0x00000004,IREGS+0xc(%a6) 5780 mov.l &0x00000002,%d3 5783 mov.l %a3,(%a4) 5784 mov.l &-0x4,%d4 5786 mov.w &0x0000,ICCR(%a6) 5787 mov.w &0x0000,%cc 5792 mov.w %cc,SCCR(%a6) 5794 mov.l &0x00000004,IREGS+0xc(%a6) 5806 mov.l &0x00000002,%d3 5809 mov.l %a3,(%a4) 5810 mov.l &-0x2,%d4 5812 mov.w &0x0000,ICCR(%a6) 5813 mov.w &0x0000,%cc 5818 mov.w %cc,SCCR(%a6) 5820 mov.l &0x00000004,IREGS+0xc(%a6) 5832 mov.l &0x00000002,%d3 5835 mov.l %a3,(%a4) 5836 mov.l &-0x2,%d4 5838 mov.w &0x0000,ICCR(%a6) 5839 mov.w &0x0000,%cc 5843 mov.w %cc,SCCR(%a6) 5845 mov.l &0x00000004,IREGS+0xc(%a6) 5857 mov.l &0x00000002,%d3 5860 mov.l %a3,(%a4) 5861 mov.l &-0x2,%d4 5863 mov.w &0x0000,ICCR(%a6) 5864 mov.w &0x0000,%cc 5869 mov.w %cc,SCCR(%a6) 5871 mov.l &0x00000004,IREGS+0xc(%a6) 5883 mov.l &0x00000002,%d3 5886 mov.l %a3,(%a4) 5887 mov.l %a4,%d4 5889 mov.w &0x0000,ICCR(%a6) 5890 mov.w &0x0000,%cc 5895 mov.w %cc,SCCR(%a6) 5897 mov.l &0x00000004,IREGS+0xc(%a6) 5909 mov.l &0x00000002,%d3 5912 mov.l %a3,(%a4) 5913 mov.l &-0x10,%d4 5916 mov.w &0x0000,ICCR(%a6) 5917 mov.w &0x0000,%cc 5922 mov.w %cc,SCCR(%a6) 5924 mov.l &0x00000004,IREGS+0xc(%a6) 5934 mov.l &0x00000002,%d3 5937 mov.l %a3,(%a4) 5938 mov.l &-0x10,%d4 5940 mov.w &0x0000,ICCR(%a6) 5941 mov.w &0x0000,%cc 5946 mov.w %cc,SCCR(%a6) 5948 mov.l &0x00000004,IREGS+0xc(%a6) 5960 mov.l &0x00000002,%d3 5963 mov.l %a3,(%a4) 5964 mov.l &0x2,%a6 5966 mov.w &0x0000,ICCR(%a6) 5967 mov.w &0x0000,%cc 5972 mov.w %cc,SCCR(%a6) 5974 mov.l &0x00000004,IREGS+0xc(%a6) 5985 mov.l %a7,%a0 5987 mov.l &0x00000002,%d3 5990 mov.l %a3,(%a4) 5991 mov.l &0x2,%a7 5993 mov.w &0x0000,ICCR(%a6) 5994 mov.w &0x0000,%cc 5999 mov.w %cc,SCCR(%a6) 6001 mov.l &0x00000004,IREGS+0xc(%a6) 6003 mov.l %a0,%a7 6014 mov.l &0x00000002,%d3 6017 mov.l %a3,(%a4) 6019 mov.l &0x10,%d4 6021 mov.w &0x0000,ICCR(%a6) 6022 mov.w &0x0000,%cc 6027 mov.w %cc,SCCR(%a6) 6029 mov.l &0x00000004,IREGS+0xc(%a6) 6041 mov.l &0x00000002,%d3 6044 mov.l %a3,(%a4) 6046 mov.l &0x8,%d4 6048 mov.w &0x0000,ICCR(%a6) 6049 mov.w &0x0000,%cc 6054 mov.w %cc,SCCR(%a6) 6056 mov.l &0x00000004,IREGS+0xc(%a6) 6068 mov.l &0x00000002,%d3 6071 mov.l %a3,(%a4) 6073 mov.l &0x4,%d4 6075 mov.w &0x0000,ICCR(%a6) 6076 mov.w &0x0000,%cc 6081 mov.w %cc,SCCR(%a6) 6083 mov.l &0x00000004,IREGS+0xc(%a6) 6095 mov.l &0x00000002,%d3 6098 mov.l %a3,(%a4) 6100 mov.l &0x2,%d4 6102 mov.w &0x0000,ICCR(%a6) 6103 mov.w &0x0000,%cc 6108 mov.w %cc,SCCR(%a6) 6110 mov.l &0x00000004,IREGS+0xc(%a6) 6122 mov.l &0x00000002,%d3 6125 mov.l %a3,(%a4) 6127 mov.l &0x10,%d4 6129 mov.w &0x0000,ICCR(%a6) 6130 mov.w &0x0000,%cc 6135 mov.w %cc,SCCR(%a6) 6137 mov.l &0x00000004,IREGS+0xc(%a6) 6149 mov.l &0x00000002,%d3 6152 mov.l %a3,(%a4) 6154 mov.l &0x8,%d4 6156 mov.w &0x0000,ICCR(%a6) 6157 mov.w &0x0000,%cc 6162 mov.w %cc,SCCR(%a6) 6164 mov.l &0x00000004,IREGS+0xc(%a6) 6176 mov.l &0x00000002,%d3 6179 mov.l %a3,(%a4) 6181 mov.l &0x4,%d4 6183 mov.w &0x0000,ICCR(%a6) 6184 mov.w &0x0000,%cc 6189 mov.w %cc,SCCR(%a6) 6191 mov.l &0x00000004,IREGS+0xc(%a6) 6203 mov.l &0x00000002,%d3 6206 mov.l %a3,(%a4) 6208 mov.l &0x2,%d4 6210 mov.w &0x0000,ICCR(%a6) 6211 mov.w &0x0000,%cc 6216 mov.w %cc,SCCR(%a6) 6218 mov.l &0x00000004,IREGS+0xc(%a6) 6230 mov.l &0x00000002,%d3 6233 mov.l %a3,(%a4) 6235 mov.l &0x2,%d4 6237 mov.w &0x0000,ICCR(%a6) 6238 mov.w &0x0000,%cc 6243 mov.w %cc,SCCR(%a6) 6245 mov.l &0x00000004,IREGS+0xc(%a6) 6257 mov.l &0x00000002,%d3 6260 mov.l %a3,(%a4) 6261 mov.l &0x2,%d4 6263 mov.w &0x0000,ICCR(%a6) 6264 mov.w &0x0000,%cc 6269 mov.w %cc,SCCR(%a6) 6271 mov.l &0x00000004,IREGS+0xc(%a6) 6283 mov.l &0x00000002,%d3 6286 mov.l %a3,(%a4) 6287 mov.l &0x4,%d4 6289 mov.w &0x0000,ICCR(%a6) 6290 mov.w &0x0000,%cc 6295 mov.w %cc,SCCR(%a6) 6297 mov.l &0x00000004,IREGS+0xc(%a6) 6308 mov.l %a7,%a0 6310 mov.l &0x00000002,%d3 6313 mov.l %a3,(%a6) 6315 mov.l &-0x2,%a7 6317 mov.w &0x0000,ICCR(%a6) 6318 mov.w &0x0000,%cc 6323 mov.w %cc,SCCR(%a6) 6325 mov.l &0x00000004,IREGS+0xc(%a6) 6327 mov.l %a0,%a7 6340 mov.l &14,%d0 6346 mov.w ICCR(%a6),%d0 6347 mov.w SCCR(%a6),%d1 6359 mov.l TESTCTR(%a6),%d1 6373 mov.l %d0,-(%sp) 6374 mov.l (TESTTOP-0x80+0x0,%pc),%d0 6376 mov.l 0x4(%sp),%d0 6380 mov.l %d0,-(%sp) 6381 mov.l (TESTTOP-0x80+0x4,%pc),%d0 6383 mov.l 0x4(%sp),%d0
|
H A D | ftest.S | 77 mov.l %d1,-(%sp) 243 mov.w &0x0000,ICCR(%a6) 248 mov.l &0x40000000,DATA+0x0(%a6) 249 mov.l &0xc90fdaa2,DATA+0x4(%a6) 250 mov.l &0x2168c235,DATA+0x8(%a6) 252 mov.w &0x0000,%cc 256 mov.w %cc,SCCR(%a6) 261 mov.l &0xbfbf0000,IFPREGS+0x0(%a6) 262 mov.l &0x80000000,IFPREGS+0x4(%a6) 263 mov.l &0x00000000,IFPREGS+0x8(%a6) 264 mov.l &0x08000208,IFPCREGS+0x4(%a6) 266 mov.l %a0,IFPCREGS+0x8(%a6) 283 mov.w &0x0000,ICCR(%a6) 288 mov.l &0x3ffe0000,DATA+0x0(%a6) 289 mov.l &0xc90fdaa2,DATA+0x4(%a6) 290 mov.l &0x2168c235,DATA+0x8(%a6) 292 mov.w &0x0000,%cc 296 mov.w %cc,SCCR(%a6) 301 mov.l &0x3fff0000,IFPREGS+0x0(%a6) 302 mov.l &0x80000000,IFPREGS+0x4(%a6) 303 mov.l &0x00000000,IFPREGS+0x8(%a6) 304 mov.l &0x00000208,IFPCREGS+0x4(%a6) 306 mov.l %a0,IFPCREGS+0x8(%a6) 324 mov.w &0x0000,ICCR(%a6) 329 mov.w &0x0000,%cc 333 mov.w %cc,SCCR(%a6) 338 mov.l &0x40000000,IFPREGS+0x0(%a6) 339 mov.l &0x935d8ddd,IFPREGS+0x4(%a6) 340 mov.l &0xaaa8ac17,IFPREGS+0x8(%a6) 341 mov.l &0x00000208,IFPCREGS+0x4(%a6) 343 mov.l %a0,IFPCREGS+0x8(%a6) 362 mov.l &0x00,%d7 364 mov.w &0x0000,ICCR(%a6) 369 mov.w &0x0000,%cc 373 mov.w %cc,SCCR(%a6) 377 mov.l &0x0f008080,IFPCREGS+0x4(%a6) 379 mov.l %a0,IFPCREGS+0x8(%a6) 398 mov.l &0x2,%d7 400 mov.w &0x0000,ICCR(%a6) 405 mov.w &0x0000,%cc 409 mov.w %cc,SCCR(%a6) 413 mov.w &0xffff,IREGS+28+2(%a6) 414 mov.l &0x0f008080,IFPCREGS+0x4(%a6) 416 mov.l %a0,IFPCREGS+0x8(%a6) 436 mov.w &0x0000,ICCR(%a6) 441 mov.w &0x0000,%cc 445 mov.w %cc,SCCR(%a6) 449 mov.l &0x0f008080,IFPCREGS+0x4(%a6) 451 mov.l %a0,IFPCREGS+0x8(%a6) 477 mov.w &0x0000,ICCR(%a6) 484 mov.w &0x0000,%cc 488 mov.w %cc,SCCR(%a6) 493 mov.l &0xc0010000,IFPREGS+0x0(%a6) 494 mov.l &0x80000000,IFPREGS+0x4(%a6) 495 mov.l &0x00000000,IFPREGS+0x8(%a6) 496 mov.l &0x08000000,IFPCREGS+0x4(%a6) 498 mov.l %a0,IFPCREGS+0x8(%a6) 515 mov.w &0x0000,ICCR(%a6) 520 mov.w &0x0000,%cc 524 mov.w %cc,SCCR(%a6) 529 mov.l &0x3e660000,IFPREGS+0x0(%a6) 530 mov.l &0xd0ed23e8,IFPREGS+0x4(%a6) 531 mov.l &0xd14035bc,IFPREGS+0x8(%a6) 532 mov.l &0x00000108,IFPCREGS+0x4(%a6) 534 mov.l %a0,IFPCREGS+0x8(%a6) 551 mov.w &0x0000,ICCR(%a6) 552 mov.w &0x0000,%cc 559 mov.w %cc,SCCR(%a6) 563 mov.l &0x0000fff0,IFPCREGS+0x0(%a6) 564 mov.l &0x0ffffff8,IFPCREGS+0x4(%a6) 581 mov.w &0x0000,ICCR(%a6) 582 mov.w &0x0000,%cc 589 mov.w %cc,SCCR(%a6) 593 mov.l &0x0000fff0,IFPCREGS+0x0(%a6) 594 mov.l &0xffffffff,IFPCREGS+0x8(%a6) 611 mov.w &0x0000,ICCR(%a6) 612 mov.w &0x0000,%cc 619 mov.w %cc,SCCR(%a6) 623 mov.l &0x0ffffff8,IFPCREGS+0x4(%a6) 624 mov.l &0xffffffff,IFPCREGS+0x8(%a6) 641 mov.w &0x0000,ICCR(%a6) 642 mov.w &0x0000,%cc 649 mov.w %cc,SCCR(%a6) 653 mov.l &0x0000fff0,IFPCREGS+0x0(%a6) 654 mov.l &0x0ffffff8,IFPCREGS+0x4(%a6) 655 mov.l &0xffffffff,IFPCREGS+0x8(%a6) 683 mov.l &0xffffffaa,%d0 685 mov.w &0x0000,ICCR(%a6) 691 mov.w &0x0000,%cc 695 mov.w %cc,SCCR(%a6) 750 mov.l &0xffffffaa,%d0 752 mov.w &0x0000,ICCR(%a6) 757 mov.w &0x0000,%cc 761 mov.w %cc,SCCR(%a6) 793 mov.l &0xffffff00,%d0 795 mov.w &0x0000,ICCR(%a6) 801 mov.w &0x0000,%cc 805 mov.w %cc,SCCR(%a6) 837 mov.w &0x0000,ICCR(%a6) 843 mov.l &0x7ffe0000,DATA+0x0(%a6) 844 mov.l &0x80000000,DATA+0x4(%a6) 845 mov.l &0x00000000,DATA+0x8(%a6) 847 mov.w &0x0000,%cc 851 mov.w %cc,SCCR(%a6) 856 mov.l &0x7fff0000,IFPREGS+0x0(%a6) 857 mov.l &0x00000000,IFPREGS+0x4(%a6) 858 mov.l &0x00000000,IFPREGS+0x8(%a6) 859 mov.l &0x02001048,IFPCREGS+0x4(%a6) 861 mov.l %a0,IFPCREGS+0x8(%a6) 888 mov.w &0x0000,ICCR(%a6) 895 mov.l &0x7ffe0000,DATA+0x0(%a6) 896 mov.l &0x80000000,DATA+0x4(%a6) 897 mov.l &0x00000000,DATA+0x8(%a6) 899 mov.w &0x0000,%cc 903 mov.w %cc,SCCR(%a6) 908 mov.l &0x7fff0000,IFPREGS+0x0(%a6) 909 mov.l &0x00000000,IFPREGS+0x4(%a6) 910 mov.l &0x00000000,IFPREGS+0x8(%a6) 911 mov.l &0x02001048,IFPCREGS+0x4(%a6) 913 mov.l %a0,IFPCREGS+0x8(%a6) 940 mov.w &0x0000,ICCR(%a6) 946 mov.l &0x00000000,DATA+0x0(%a6) 947 mov.l &0x80000000,DATA+0x4(%a6) 948 mov.l &0x00000000,DATA+0x8(%a6) 951 mov.w &0x0000,%cc 955 mov.w %cc,SCCR(%a6) 960 mov.l &0x00000000,IFPREGS+0x0(%a6) 961 mov.l &0x40000000,IFPREGS+0x4(%a6) 962 mov.l &0x00000000,IFPREGS+0x8(%a6) 963 mov.l &0x00000800,IFPCREGS+0x4(%a6) 965 mov.l %a0,IFPCREGS+0x8(%a6) 992 mov.w &0x0000,ICCR(%a6) 997 mov.l &0x00000000,DATA+0x0(%a6) 998 mov.l &0x80000000,DATA+0x4(%a6) 999 mov.l &0x00000000,DATA+0x8(%a6) 1002 mov.w &0x0000,%cc 1006 mov.w %cc,SCCR(%a6) 1011 mov.l &0x00000000,IFPREGS+0x0(%a6) 1012 mov.l &0x40000000,IFPREGS+0x4(%a6) 1013 mov.l &0x00000000,IFPREGS+0x8(%a6) 1014 mov.l &0x00000800,IFPCREGS+0x4(%a6) 1016 mov.l %a0,IFPCREGS+0x8(%a6) 1042 mov.w &0x0000,ICCR(%a6) 1048 mov.l &0x50000000,DATA+0x0(%a6) 1049 mov.l &0x80000000,DATA+0x4(%a6) 1050 mov.l &0x00000000,DATA+0x8(%a6) 1053 mov.w &0x0000,%cc 1057 mov.w %cc,SCCR(%a6) 1062 mov.l &0x50000000,IFPREGS+0x0(%a6) 1063 mov.l &0x80000000,IFPREGS+0x4(%a6) 1064 mov.l &0x00000000,IFPREGS+0x8(%a6) 1065 mov.l &0x00000208,IFPCREGS+0x4(%a6) 1067 mov.l %a0,IFPCREGS+0x8(%a6) 1093 mov.w &0x0000,ICCR(%a6) 1099 mov.l &0xffff0000,DATA+0x0(%a6) 1100 mov.l &0x00000000,DATA+0x4(%a6) 1101 mov.l &0x00000001,DATA+0x8(%a6) 1104 mov.w &0x0000,%cc 1108 mov.w %cc,SCCR(%a6) 1113 mov.l &0xffff0000,IFPREGS+0x0(%a6) 1114 mov.l &0x00000000,IFPREGS+0x4(%a6) 1115 mov.l &0x00000001,IFPREGS+0x8(%a6) 1116 mov.l &0x09004080,IFPCREGS+0x4(%a6) 1118 mov.l %a0,IFPCREGS+0x8(%a6) 1144 mov.w &0x0000,ICCR(%a6) 1150 mov.l &0xffff0000,DATA+0x0(%a6) 1151 mov.l &0x00000000,DATA+0x4(%a6) 1152 mov.l &0x00000000,DATA+0x8(%a6) 1155 mov.w &0x0000,%cc 1159 mov.w %cc,SCCR(%a6) 1164 mov.l &0xffff0000,IFPREGS+0x0(%a6) 1165 mov.l &0x00000000,IFPREGS+0x4(%a6) 1166 mov.l &0x00000000,IFPREGS+0x8(%a6) 1167 mov.l &0x01002080,IFPCREGS+0x4(%a6) 1169 mov.l %a0,IFPCREGS+0x8(%a6) 1195 mov.w &0x0000,ICCR(%a6) 1201 mov.l &0x40000000,DATA+0x0(%a6) 1202 mov.l &0x80000000,DATA+0x4(%a6) 1203 mov.l &0x00000000,DATA+0x8(%a6) 1206 mov.w &0x0000,%cc 1210 mov.w %cc,SCCR(%a6) 1215 mov.l &0x40000000,IFPREGS+0x0(%a6) 1216 mov.l &0x80000000,IFPREGS+0x4(%a6) 1217 mov.l &0x00000000,IFPREGS+0x8(%a6) 1218 mov.l &0x02000410,IFPCREGS+0x4(%a6) 1220 mov.l %a0,IFPCREGS+0x8(%a6) 1247 mov.w &0x0000,ICCR(%a6) 1252 mov.l &0xc03f0000,DATA+0x0(%a6) 1253 mov.l &0x00000000,DATA+0x4(%a6) 1254 mov.l &0x00000001,DATA+0x8(%a6) 1256 mov.w &0x0000,%cc 1260 mov.w %cc,SCCR(%a6) 1265 mov.l &0xc0010000,IFPREGS+0x0(%a6) 1266 mov.l &0x80000000,IFPREGS+0x4(%a6) 1267 mov.l &0x00000000,IFPREGS+0x8(%a6) 1268 mov.l &0x08000000,IFPCREGS+0x4(%a6) 1270 mov.l %a0,IFPCREGS+0x8(%a6) 1288 mov.w &0x0000,ICCR(%a6) 1293 mov.l &0x80000000,DATA+0x0(%a6) 1294 mov.l &0x01000000,DATA+0x4(%a6) 1295 mov.l &0x00000000,DATA+0x8(%a6) 1298 mov.w &0x0000,%cc 1302 mov.w %cc,SCCR(%a6) 1307 mov.l &0x80170000,IFPREGS+0x0(%a6) 1308 mov.l &0xfffffffe,IFPREGS+0x4(%a6) 1309 mov.l &0x00000000,IFPREGS+0x8(%a6) 1310 mov.l &0x08000000,IFPCREGS+0x4(%a6) 1312 mov.l %a0,IFPCREGS+0x8(%a6) 1330 mov.w &0x0000,ICCR(%a6) 1335 mov.l &0xc1230001,DATA+0x0(%a6) 1336 mov.l &0x23456789,DATA+0x4(%a6) 1337 mov.l &0x12345678,DATA+0x8(%a6) 1339 mov.w &0x0000,%cc 1343 mov.w %cc,SCCR(%a6) 1348 mov.l &0x3e660000,IFPREGS+0x0(%a6) 1349 mov.l &0xd0ed23e8,IFPREGS+0x4(%a6) 1350 mov.l &0xd14035bc,IFPREGS+0x8(%a6) 1351 mov.l &0x00000108,IFPCREGS+0x4(%a6) 1353 mov.l %a0,IFPCREGS+0x8(%a6) 1372 mov.l &14,%d0 1378 mov.w ICCR(%a6),%d0 1379 mov.w SCCR(%a6),%d1 1391 mov.l TESTCTR(%a6),%d1 1398 mov.l &23,%d0 1443 mov.l %d0,-(%sp) 1444 mov.l (TESTTOP-0x80+0x0,%pc),%d0 1446 mov.l 0x4(%sp),%d0 1450 mov.l %d0,-(%sp) 1451 mov.l (TESTTOP-0x80+0x4,%pc),%d0 1453 mov.l 0x4(%sp),%d0
|
H A D | isp.S | 98 mov.l %d0,-(%sp) 99 mov.l (_060ISP_TABLE-0x80+_off_chk,%pc),%d0 101 mov.l 0x4(%sp),%d0 106 mov.l %d0,-(%sp) 107 mov.l (_060ISP_TABLE-0x80+_off_divbyzero,%pc),%d0 109 mov.l 0x4(%sp),%d0 114 mov.l %d0,-(%sp) 115 mov.l (_060ISP_TABLE-0x80+_off_trace,%pc),%d0 117 mov.l 0x4(%sp),%d0 122 mov.l %d0,-(%sp) 123 mov.l (_060ISP_TABLE-0x80+_off_access,%pc),%d0 125 mov.l 0x4(%sp),%d0 130 mov.l %d0,-(%sp) 131 mov.l (_060ISP_TABLE-0x80+_off_done,%pc),%d0 133 mov.l 0x4(%sp),%d0 140 mov.l %d0,-(%sp) 141 mov.l (_060ISP_TABLE-0x80+_off_cas,%pc),%d0 143 mov.l 0x4(%sp),%d0 148 mov.l %d0,-(%sp) 149 mov.l (_060ISP_TABLE-0x80+_off_cas2,%pc),%d0 151 mov.l 0x4(%sp),%d0 156 mov.l %d0,-(%sp) 157 mov.l (_060ISP_TABLE-0x80+_off_lock,%pc),%d0 159 mov.l 0x4(%sp),%d0 164 mov.l %d0,-(%sp) 165 mov.l (_060ISP_TABLE-0x80+_off_unlock,%pc),%d0 167 mov.l 0x4(%sp),%d0 174 mov.l %d0,-(%sp) 175 mov.l (_060ISP_TABLE-0x80+_off_imr,%pc),%d0 177 mov.l 0x4(%sp),%d0 182 mov.l %d0,-(%sp) 183 mov.l (_060ISP_TABLE-0x80+_off_dmr,%pc),%d0 185 mov.l 0x4(%sp),%d0 190 mov.l %d0,-(%sp) 191 mov.l (_060ISP_TABLE-0x80+_off_dmw,%pc),%d0 193 mov.l 0x4(%sp),%d0 198 mov.l %d0,-(%sp) 199 mov.l (_060ISP_TABLE-0x80+_off_irw,%pc),%d0 201 mov.l 0x4(%sp),%d0 206 mov.l %d0,-(%sp) 207 mov.l (_060ISP_TABLE-0x80+_off_irl,%pc),%d0 209 mov.l 0x4(%sp),%d0 214 mov.l %d0,-(%sp) 215 mov.l (_060ISP_TABLE-0x80+_off_drb,%pc),%d0 217 mov.l 0x4(%sp),%d0 222 mov.l %d0,-(%sp) 223 mov.l (_060ISP_TABLE-0x80+_off_drw,%pc),%d0 225 mov.l 0x4(%sp),%d0 230 mov.l %d0,-(%sp) 231 mov.l (_060ISP_TABLE-0x80+_off_drl,%pc),%d0 233 mov.l 0x4(%sp),%d0 238 mov.l %d0,-(%sp) 239 mov.l (_060ISP_TABLE-0x80+_off_dwb,%pc),%d0 241 mov.l 0x4(%sp),%d0 246 mov.l %d0,-(%sp) 247 mov.l (_060ISP_TABLE-0x80+_off_dww,%pc),%d0 249 mov.l 0x4(%sp),%d0 254 mov.l %d0,-(%sp) 255 mov.l (_060ISP_TABLE-0x80+_off_dwl,%pc),%d0 257 mov.l 0x4(%sp),%d0 402 mov.l (%a6),EXC_A6(%a6) # store a6 407 mov.l %usp,%a0 # fetch user stack pointer 408 mov.l %a0,EXC_A7(%a6) # store a7 412 mov.l %a0,EXC_A7(%a6) # store corrected sp 419 mov.w EXC_ISR(%a6),EXC_CC(%a6) # store cc copy on stack 420 mov.l EXC_IPC(%a6),EXC_EXTWPTR(%a6) # store extwptr on stack 426 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 429 mov.l %d0,EXC_OPWORD(%a6) # store extword on stack 549 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 576 mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes 584 mov.l EXC_A7(%a6),%a0 # fetch user stack pointer 585 mov.l %a0,%usp # restore it 593 mov.l EXC_EXTWPTR(%a6),EXC_IPC(%a6) # new pc on stack frame 594 mov.l EXC_A6(%a6),(%a6) # prepare new a6 for unlink 624 mov.l EXC_A6(%a6),-0x4(%a6) 625 mov.w EXC_ISR(%a6),0x0(%a6) 626 mov.l EXC_IPC(%a6),0x8(%a6) 627 mov.l EXC_EXTWPTR(%a6),0x2(%a6) 628 mov.w &0x2024,0x6(%a6) 653 mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes 656 mov.w EXC_ISR(%a6),(%a6) # put new SR on stack 657 mov.l EXC_IPC(%a6),0x8(%a6) # put "Current PC" on stack 658 mov.l EXC_EXTWPTR(%a6),0x2(%a6) # put "Next PC" on stack 659 mov.w &0x2018,0x6(%a6) # put Vector Offset on stack 661 mov.l EXC_A6(%a6),%a6 # restore a6 687 mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes 690 mov.w EXC_ISR(%a6),(%a6) # put new SR on stack 691 mov.l EXC_IPC(%a6),0x8(%a6) # put "Current PC" on stack 692 mov.l EXC_EXTWPTR(%a6),0x2(%a6) # put "Next PC" on stack 693 mov.w &0x2014,0x6(%a6) # put Vector Offset on stack 695 mov.l EXC_A6(%a6),%a6 # restore a6 724 mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes 727 mov.l EXC_IPC(%a6),0xc(%a6) # put "Current PC" on stack 728 mov.w &0x2014,0xa(%a6) # put Vector Offset on stack 729 mov.l EXC_EXTWPTR(%a6),0x6(%a6) # put "Next PC" on stack 731 mov.l EXC_A6(%a6),%a6 # restore a6 762 mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes 765 mov.l EXC_IPC(%a6),0xc(%a6) # put "Current PC" on stack 766 mov.w &0x2024,0xa(%a6) # put Vector Offset on stack 767 mov.l EXC_EXTWPTR(%a6),0x6(%a6) # put "Next PC" on stack 769 mov.l EXC_A6(%a6),%a6 # restore a6 789 mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes 792 mov.w &0x00f4,0xe(%a6) # put Vector Offset on stack 793 mov.l EXC_EXTWPTR(%a6),0xa(%a6) # put "Next PC" on stack 794 mov.w EXC_ISR(%a6),0x8(%a6) # put SR on stack 796 mov.l EXC_A6(%a6),%a6 # restore a6 806 mov.l %a0,(%a6) # save address 807 mov.l %d0,-0x4(%a6) # save partial fslw 812 mov.l 0xc(%sp),-(%sp) # move voff,hi(pc) 813 mov.l 0x4(%sp),0x10(%sp) # store fslw 814 mov.l 0xc(%sp),0x4(%sp) # store sr,lo(pc) 815 mov.l 0x8(%sp),0xc(%sp) # store address 816 mov.l (%sp)+,0x4(%sp) # store voff,hi(pc) 817 mov.w &0x4008,0x6(%sp) # store new voff 832 mov.l 0x8(%sp),(%sp) # store sr,lo(pc) 833 mov.w 0xc(%sp),0x4(%sp) # store hi(pc) 834 mov.w &0x4008,0x6(%sp) # store new voff 835 mov.l 0x2(%sp),0x8(%sp) # store address (=pc) 836 mov.l &0x09428001,0xc(%sp) # store fslw 851 mov.b EXC_SAVREG(%a6),%d0 # regno to restore 852 mov.l EXC_SAVVAL(%a6),(EXC_AREGS,%a6,%d0.l*4) # restore value 914 mov.l %d0,%a0 # move # bytes to a0 917 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word 918 mov.w %d0,%d1 # make a copy 924 mov.w (tbl_ea_mode.b,%pc,%d0.w*2), %d0 # fetch jmp distance 1005 mov.l EXC_A0(%a6),%a0 # Get current a0 1009 mov.l EXC_A1(%a6),%a0 # Get current a1 1013 mov.l EXC_A2(%a6),%a0 # Get current a2 1017 mov.l EXC_A3(%a6),%a0 # Get current a3 1021 mov.l EXC_A4(%a6),%a0 # Get current a4 1025 mov.l EXC_A5(%a6),%a0 # Get current a5 1029 mov.l EXC_A6(%a6),%a0 # Get current a6 1033 mov.l EXC_A7(%a6),%a0 # Get current a7 1040 mov.l %a0,%d0 # copy no. bytes 1041 mov.l EXC_A0(%a6),%a0 # load current value 1043 mov.l %d0,EXC_A0(%a6) # save incremented value 1045 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error 1046 mov.b &0x0,EXC_SAVREG(%a6) # save regno, too 1047 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1051 mov.l %a0,%d0 # copy no. bytes 1052 mov.l EXC_A1(%a6),%a0 # load current value 1054 mov.l %d0,EXC_A1(%a6) # save incremented value 1056 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error 1057 mov.b &0x1,EXC_SAVREG(%a6) # save regno, too 1058 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1062 mov.l %a0,%d0 # copy no. bytes 1063 mov.l EXC_A2(%a6),%a0 # load current value 1065 mov.l %d0,EXC_A2(%a6) # save incremented value 1067 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error 1068 mov.b &0x2,EXC_SAVREG(%a6) # save regno, too 1069 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1073 mov.l %a0,%d0 # copy no. bytes 1074 mov.l EXC_A3(%a6),%a0 # load current value 1076 mov.l %d0,EXC_A3(%a6) # save incremented value 1078 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error 1079 mov.b &0x3,EXC_SAVREG(%a6) # save regno, too 1080 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1084 mov.l %a0,%d0 # copy no. bytes 1085 mov.l EXC_A4(%a6),%a0 # load current value 1087 mov.l %d0,EXC_A4(%a6) # save incremented value 1089 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error 1090 mov.b &0x4,EXC_SAVREG(%a6) # save regno, too 1091 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1095 mov.l %a0,%d0 # copy no. bytes 1096 mov.l EXC_A5(%a6),%a0 # load current value 1098 mov.l %d0,EXC_A5(%a6) # save incremented value 1100 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error 1101 mov.b &0x5,EXC_SAVREG(%a6) # save regno, too 1102 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1106 mov.l %a0,%d0 # copy no. bytes 1107 mov.l EXC_A6(%a6),%a0 # load current value 1109 mov.l %d0,EXC_A6(%a6) # save incremented value 1111 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error 1112 mov.b &0x6,EXC_SAVREG(%a6) # save regno, too 1113 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1117 mov.b &mia7_flg,SPCOND_FLG(%a6) # set "special case" flag 1119 mov.l %a0,%d0 # copy no. bytes 1120 mov.l EXC_A7(%a6),%a0 # load current value 1122 mov.l %d0,EXC_A7(%a6) # save incremented value 1129 mov.l EXC_A0(%a6),%d0 # Get current a0 1130 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1132 mov.l %d0,EXC_A0(%a6) # Save decr value 1133 mov.l %d0,%a0 1135 mov.b &0x0,EXC_SAVREG(%a6) # save regno, too 1136 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1140 mov.l EXC_A1(%a6),%d0 # Get current a1 1141 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1143 mov.l %d0,EXC_A1(%a6) # Save decr value 1144 mov.l %d0,%a0 1146 mov.b &0x1,EXC_SAVREG(%a6) # save regno, too 1147 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1151 mov.l EXC_A2(%a6),%d0 # Get current a2 1152 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1154 mov.l %d0,EXC_A2(%a6) # Save decr value 1155 mov.l %d0,%a0 1157 mov.b &0x2,EXC_SAVREG(%a6) # save regno, too 1158 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1162 mov.l EXC_A3(%a6),%d0 # Get current a3 1163 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1165 mov.l %d0,EXC_A3(%a6) # Save decr value 1166 mov.l %d0,%a0 1168 mov.b &0x3,EXC_SAVREG(%a6) # save regno, too 1169 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1173 mov.l EXC_A4(%a6),%d0 # Get current a4 1174 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1176 mov.l %d0,EXC_A4(%a6) # Save decr value 1177 mov.l %d0,%a0 1179 mov.b &0x4,EXC_SAVREG(%a6) # save regno, too 1180 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1184 mov.l EXC_A5(%a6),%d0 # Get current a5 1185 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1187 mov.l %d0,EXC_A5(%a6) # Save decr value 1188 mov.l %d0,%a0 1190 mov.b &0x5,EXC_SAVREG(%a6) # save regno, too 1191 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1195 mov.l EXC_A6(%a6),%d0 # Get current a6 1196 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1198 mov.l %d0,EXC_A6(%a6) # Save decr value 1199 mov.l %d0,%a0 1201 mov.b &0x6,EXC_SAVREG(%a6) # save regno, too 1202 mov.b &restore_flg,SPCOND_FLG(%a6) # set flag 1206 mov.b &mda7_flg,SPCOND_FLG(%a6) # set "special case" flag 1208 mov.l EXC_A7(%a6),%d0 # Get current a7 1210 mov.l %d0,EXC_A7(%a6) # Save decr value 1211 mov.l %d0,%a0 1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1225 mov.w %d0,%a0 # sign extend displacement 1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1237 mov.w %d0,%a0 # sign extend displacement 1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1249 mov.w %d0,%a0 # sign extend displacement 1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1261 mov.w %d0,%a0 # sign extend displacement 1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1273 mov.w %d0,%a0 # sign extend displacement 1278 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1285 mov.w %d0,%a0 # sign extend displacement 1290 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1297 mov.w %d0,%a0 # sign extend displacement 1302 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1309 mov.w %d0,%a0 # sign extend displacement 1320 mov.l %d1,-(%sp) 1322 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1329 mov.l (%sp)+,%d1 1331 mov.l (EXC_AREGS,%a6,%d1.w*4),%a0 # put base in a0 1338 mov.l %d0,%d5 # put extword in d5 1339 mov.l %a0,%d3 # put base in d3 1344 mov.l %d2,-(%sp) # save old d2 1346 mov.l %d0,%d1 1350 mov.l (EXC_DREGS,%a6,%d1.w*4),%d1 # fetch index reg value 1356 mov.l %d0,%d2 1366 mov.l (%sp)+,%d2 # restore old d2 1377 mov.b &immed_flg,SPCOND_FLG(%a6) # set immediate flag 1379 mov.l EXC_EXTWPTR(%a6),%a0 # fetch extension word ptr 1386 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1393 mov.w %d0,%a0 # return <ea> in a0 1400 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1407 mov.l %d0,%a0 # return <ea> in a0 1414 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1421 mov.w %d0,%a0 # sign extend displacement 1437 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1444 mov.l EXC_EXTWPTR(%a6),%a0 # put base in a0 1454 mov.l %d0,%d5 # put extword in d5 1455 mov.l %a0,%d3 # put base in d3 1460 mov.l %d2,-(%sp) # create a temp register 1462 mov.l %d0,%d1 # make extword copy 1466 mov.l (EXC_DREGS,%a6,%d1.w*4),%d1 # fetch index reg value 1472 mov.l %d0,%d2 # make extword copy 1482 mov.l (%sp)+,%d2 # restore temp register 1501 mov.l (EXC_DREGS,%a6,%d2.w*4),%d2 1519 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1528 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1546 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1556 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1569 mov.l %d0,%d4 1573 mov.l %d3,%a0 1585 mov.l %d3,%a0 1596 mov.l %d3,%d0 1598 mov.l %d0,%a0 1612 mov.l %d3,%a0 # pass failing address 1613 mov.l &0x01010001,%d0 # pass fslw 1652 mov.w EXC_OPWORD(%a6),%d1 # fetch the opcode word 1654 mov.b %d1,%d0 1657 mov.l (EXC_AREGS,%a6,%d0.w*4),%a0 # fetch ay 1666 mov.w %d1,%d0 1670 mov.l (EXC_DREGS,%a6,%d0.w*4), %d0 # fetch dx 1678 mov.l %d0,%d2 # store data 1679 mov.l %a0,%a2 # store addr 1681 mov.l %d2,%d0 1689 mov.l %a2,%a0 1691 mov.l %d2,%d0 1699 mov.l %a2,%a0 1701 mov.l %d2,%d0 1709 mov.l %a2,%a0 1711 mov.l %d2,%d0 1723 mov.l %d0,%d2 # store data 1724 mov.l %a0,%a2 # store addr 1733 mov.l %a2,%a0 1734 mov.l %d2,%d0 1751 mov.l %a0,%a2 # store addr 1758 mov.l %d0,%d2 1761 mov.l %a2,%a0 1769 mov.b %d0,%d2 # append bytes 1772 mov.l %a2,%a0 1780 mov.b %d0,%d2 # append bytes 1783 mov.l %a2,%a0 1791 mov.b %d0,%d2 # append bytes 1793 mov.b EXC_OPWORD(%a6),%d1 1797 mov.l %d2,(EXC_DREGS,%a6,%d1.w*4) # store dx 1803 mov.l %a0,%a2 # store addr 1810 mov.l %d0,%d2 1813 mov.l %a2,%a0 1821 mov.b %d0,%d2 # append bytes 1823 mov.b EXC_OPWORD(%a6),%d1 1827 mov.w %d2,(EXC_DREGS+2,%a6,%d1.w*4) # store dx 1840 mov.l %a2,%a0 # pass failing address 1841 mov.l &0x00a10001,%d0 # pass fslw 1850 mov.l %a2,%a0 # pass failing address 1851 mov.l &0x01210001,%d0 # pass fslw 1897 mov.b EXC_EXTWORD(%a6), %d0 # fetch hi extension word 1901 mov.l (EXC_DREGS,%a6,%d0.w*4), %d2 # get regval 1910 mov.l %a0,%a2 # save copy of <ea> 1916 mov.l %d0,%d3 # save long lower bound 1918 mov.l %a2,%a0 # pass <ea> of long upper bound 1924 mov.l %d0,%d1 # long upper bound in d1 1925 mov.l %d3,%d0 # long lower bound in d0 1932 mov.l %a0,%a2 1938 mov.w %d0, %d1 # place hi in %d1 1956 mov.l %a0,%a2 1962 mov.b %d0, %d1 # place hi in %d1 1984 mov.w %cc, %d3 # fetch resulting ccodes 1989 mov.w %cc, %d4 # fetch resulting ccodes 1993 mov.w EXC_CC(%a6), %d4 # fetch old ccodes 1996 mov.w %d4, EXC_CC(%a6) # save new ccodes 2011 mov.b &ichk_flg,SPCOND_FLG(%a6) # set "special case" flag 2023 mov.l %a2,%a0 # pass failing address 2024 mov.l &0x01010001,%d0 # pass fslw 2033 mov.l %a2,%a0 # pass failing address 2034 mov.l &0x01410001,%d0 # pass fslw 2087 mov.b EXC_OPWORD+1(%a6), %d0 2092 mov.b EXC_OPWORD+1(%a6), %d0 # extract Dn from opcode 2094 mov.l (EXC_DREGS,%a6,%d0.w*4), %d7 # fetch divisor from register 2099 mov.b EXC_EXTWORD+1(%a6), %d0 # extract Dr from extword 2100 mov.b EXC_EXTWORD(%a6), %d1 # extract Dq from extword 2104 mov.w %d0, NDRSAVE(%a6) # save Dr for later 2105 mov.w %d1, NDQSAVE(%a6) # save Dq for later 2108 mov.l (EXC_DREGS,%a6,%d0.w*4), %d5 # get dividend hi 2109 mov.l (EXC_DREGS,%a6,%d1.w*4), %d6 # get dividend lo 2129 mov.w &0x0, %cc # clear 'X' cc bit 2173 mov.b NDIVISOR(%a6), %d0 2192 mov.w EXC_CC(%a6), %cc 2194 mov.w %cc, EXC_CC(%a6) 2196 mov.w NDRSAVE(%a6), %d0 # get Dr off stack 2197 mov.w NDQSAVE(%a6), %d1 # get Dq off stack 2201 mov.l %d5, (EXC_DREGS,%a6,%d0.w*4) # save remainder 2202 mov.l %d6, (EXC_DREGS,%a6,%d1.w*4) # save quotient 2251 mov.w %d6, %d5 # rb + u3 2255 mov.w %d5, %d1 # first quotient word 2257 mov.w %d6, %d5 # rb + u4 2262 mov.w %d5, %d1 # 2nd quotient 'digit' 2265 mov.l %d1, %d6 # and quotient 2292 mov.l %d7, %d3 # divisor 2293 mov.l %d5, %d2 # dividend mslw 2298 mov.w &0xffff, %d1 # use max trial quotient word 2301 mov.l %d5, %d1 2311 mov.l %d6, -(%sp) 2314 ddadj1: mov.l %d7, %d3 2315 mov.l %d1, %d2 2319 mov.l %d5, %d4 # U1U2 2324 mov.w %d4,%d0 2325 mov.w %d6,%d4 # insert lower word (U3) 2339 mov.l %d5, -(%sp) # save %d5 (%d6 already saved) 2340 mov.l %d1, %d6 2342 mov.l %d7, %d5 2344 mov.l %d5, %d2 # now %d2,%d3 are trial*divisor 2345 mov.l %d6, %d3 2346 mov.l (%sp)+, %d5 # restore dividend 2347 mov.l (%sp)+, %d6 2356 mov.l %d7, %d3 2361 mov.l %d7, %d3 2370 mov.w %d1, DDQUOTIENT(%a6) 2374 mov.w %d6, %d5 2380 mov.w %d1, DDQUOTIENT+2(%a6) 2382 mov.w %d5, %d6 2385 mov.l DDNORMAL(%a6), %d7 # get norm shift count 2393 mov.l %d6, %d5 # remainder 2394 mov.l DDQUOTIENT(%a6), %d6 # quotient 2403 mov.l %d6, %d2 2404 mov.l %d6, %d3 2405 mov.l %d5, %d4 2436 mov.l %a0,%a2 2442 mov.l %d0, %d7 2455 mov.l %d0,%d7 2472 mov.l %a2,%a0 # pass failing address 2473 mov.l &0x01010001,%d0 # pass fslw 2515 mov.b EXC_OPWORD+1(%a6), %d0 # extract src {mode,reg} 2523 mov.l (EXC_DREGS,%a6,%d0.w*4), %d3 # fetch multiplier 2528 mov.w EXC_EXTWORD(%a6), %d2 # fetch ext word 2530 mov.b %d2, %d1 # grab Dh 2534 mov.l (EXC_DREGS,%a6,%d2.w*4), %d4 # get multiplicand 2582 mov.l %d3, %d5 # mr in %d5 2583 mov.l %d3, %d6 # mr in %d6 2584 mov.l %d4, %d7 # md in %d7 2632 mov.l %d3, (EXC_DREGS,%a6,%d2.w*4) # save lo(result) 2633 mov.w &0x0, %cc 2634 mov.l %d4, (EXC_DREGS,%a6,%d1.w*4) # save hi(result) 2638 mov.w %cc, %d7 # fetch %ccr to see if 'N' set 2642 mov.b EXC_CC+1(%a6), %d6 # fetch previous %ccr 2646 mov.b %d6, EXC_CC+1(%a6) # save new %ccr 2670 mov.l %a0,%a2 2676 mov.l %d0, %d3 # store multiplier in %d3 2690 mov.l %d0,%d3 2707 mov.l %a2,%a0 # pass failing address 2708 mov.l &0x01010001,%d0 # pass fslw 2765 mov.l %d0,EXC_TEMP+0x4(%a6) # store for possible restart 2766 mov.l %d0,%d1 # extension word in d0 2770 mov.l (EXC_DREGS,%a6,%d0.w*4),%a1 # fetch ADDR2 2771 mov.l %a1,ADDR2(%a6) 2773 mov.l %d1,%d0 2777 mov.l (EXC_DREGS,%a6,%d1.w*4),%d5 # fetch Update2 Op 2780 mov.l (EXC_DREGS,%a6,%d0.w*4),%d3 # fetch Compare2 Op 2781 mov.w %d0,DC2(%a6) 2783 mov.w EXC_EXTWORD(%a6),%d0 2784 mov.l %d0,%d1 2788 mov.l (EXC_DREGS,%a6,%d0.w*4),%a0 # fetch ADDR1 2789 mov.l %a0,ADDR1(%a6) 2791 mov.l %d1,%d0 2795 mov.l (EXC_DREGS,%a6,%d1.w*4),%d4 # fetch Update1 Op 2798 mov.l (EXC_DREGS,%a6,%d0.w*4),%d2 # fetch Compare1 Op 2799 mov.w %d0,DC1(%a6) 2807 mov.l %a0,%a2 2808 mov.l %a1,%a3 2810 mov.l %d7,%d1 # pass size 2811 mov.l %d6,%d0 # pass mode 2813 mov.l %a2,%a0 2817 mov.l %d7,%d1 # pass size 2818 mov.l %d6,%d0 # pass mode 2819 mov.l %a3,%a0 # pass addr 2821 mov.l %a3,%a0 2825 mov.l %a2,%a0 2826 mov.l %a3,%a1 2833 mov.l %d0,-(%sp) # save FSLW 2834 mov.l %d7,%d1 # pass size 2835 mov.l %d6,%d0 # pass mode 2836 mov.l %a2,%a0 # pass ADDR1 2838 mov.l (%sp)+,%d0 # restore FSLW 2839 mov.l %a3,%a0 # pass failing addr 2849 mov.w EXC_CC(%a6),%cc # load old ccodes 2854 mov.w %cc,EXC_CC(%a6) # save new ccodes 2859 mov.w DC2(%a6),%d3 # fetch Dc2 2860 mov.w %d1,(2+EXC_DREGS,%a6,%d3.w*4) # store new Compare2 Op 2862 mov.w DC1(%a6),%d2 # fetch Dc1 2863 mov.w %d0,(2+EXC_DREGS,%a6,%d2.w*4) # store new Compare1 Op 2868 mov.l %d2,%d0 # pass mode 2870 mov.l ADDR1(%a6),%a0 # pass ADDR1 2873 mov.l %d2,%d0 # pass mode 2875 mov.l ADDR2(%a6),%a0 # pass ADDR2 2880 mov.w EXC_CC(%a6),%cc # load old ccodes 2885 mov.w %cc,EXC_CC(%a6) # save new ccodes 2890 mov.w DC2(%a6),%d3 # fetch Dc2 2891 mov.l %d1,(EXC_DREGS,%a6,%d3.w*4) # store new Compare2 Op 2893 mov.w DC1(%a6),%d2 # fetch Dc1 2894 mov.l %d0,(EXC_DREGS,%a6,%d2.w*4) # store new Compare1 Op 2899 mov.l %d2,%d0 # pass mode 2901 mov.l ADDR1(%a6),%a0 # pass ADDR1 2904 mov.l %d2,%d0 # pass mode 2906 mov.l ADDR2(%a6),%a0 # pass ADDR2 2913 mov.l EXC_TEMP+0x4(%a6),%d0 3011 mov.l %a0,ADDR(%a6) # save <ea> for possible restart 3018 mov.l %a0,ADDR(%a6) # save <ea> for possible restart 3022 mov.w EXC_EXTWORD(%a6),%d0 # fetch cas extension word 3023 mov.l %d0,%d1 # make a copy 3027 mov.l (EXC_DREGS,%a6,%d0.w*4),%d2 # get update operand 3030 mov.l (EXC_DREGS,%a6,%d1.w*4),%d4 # get compare operand 3031 mov.w %d1,DC(%a6) # save Dc 3036 mov.l %a0,%a2 # save temporarily 3037 mov.l %d7,%d1 # pass size 3038 mov.l %d6,%d0 # pass mode 3042 mov.l %a2,%a0 # pass addr in a0 3055 mov.w EXC_CC(%a6),%cc # restore cc 3057 mov.w %cc,EXC_CC(%a6) # save cc 3062 mov.w DC(%a6),%d3 3063 mov.w %d0,(EXC_DREGS+2,%a6,%d3.w*4) # Dc = destination 3066 mov.l ADDR(%a6),%a0 # pass addr 3076 mov.w EXC_CC(%a6),%cc # restore cc 3078 mov.w %cc,EXC_CC(%a6) # save cc 3083 mov.w DC(%a6),%d3 3084 mov.l %d0,(EXC_DREGS,%a6,%d3.w*4) # Dc = destination 3087 mov.l ADDR(%a6),%a0 # pass addr 3098 mov.l %d6,%sfc # restore previous sfc 3099 mov.l %d6,%dfc # restore previous dfc 3104 mov.l ADDR(%a6),%a0 # load <ea> 3114 mov.l %d6,%sfc # restore previous sfc 3115 mov.l %d6,%dfc # restore previous dfc 3119 mov.l %a0,%a2 # copy failing addr to a2 3121 mov.l %d0,-(%sp) 3123 mov.l (%sp)+,%d0 3128 mov.l &26,%d1 # want to move 51 longwords 3132 mov.l (%a0)+,(%a1)+ # move a longword 3135 mov.w &0x4008,EXC_IVOFF(%a6) # put new stk fmt, voff 3136 mov.l %a2,EXC_IVOFF+0x2(%a6) # put faulting addr on stack 3137 mov.l %d0,EXC_IVOFF+0x6(%a6) # put FSLW on stack 3155 mov.l &-0x1,%d0 # out of range; return d0 = -1 3270 mov.l %a0,%a2 # copy ADDR1 3271 mov.l %a1,%a3 # copy ADDR2 3272 mov.l %a0,%a4 # copy ADDR1 3273 mov.l %a1,%a5 # copy ADDR2 3277 mov.l %a2,%d1 # ADDR1 3280 mov.w %sr,%d7 # save current SR 3301 mov.l %d1,%a2 # ADDR1 3303 mov.l %d1,%a4 # ADDR1+3 3312 mov.l &0x80000000,%a2 # assert LOCK* buscr value 3313 mov.l &0xa0000000,%a3 # assert LOCKE* buscr value 3314 mov.l &0x00000000,%a4 # buscr unlock value 3319 mov.l %a0,%d0 # is ADDR1 misaligned? 3415 mov.w %d7,%sr # restore old SR 3427 mov.w %d7,%sr # restore old SR 3572 mov.l %a0,%a2 # copy ADDR1 3573 mov.l %a1,%a3 # copy ADDR2 3574 mov.l %a0,%a4 # copy ADDR1 3575 mov.l %a1,%a5 # copy ADDR2 3579 mov.l %a2,%d1 # ADDR1 3582 mov.w %sr,%d7 # save current SR 3603 mov.l %d1,%a2 # ADDR1 3605 mov.l %d1,%a4 # ADDR1+3 3614 mov.l &0x80000000,%a2 # assert LOCK* buscr value 3615 mov.l &0xa0000000,%a3 # assert LOCKE* buscr value 3616 mov.l &0x00000000,%a4 # buscr unlock value 3621 mov.l %a0,%d0 # is ADDR1 misaligned? 3715 mov.w %d7,%sr # restore old SR 3727 mov.w %d7,%sr # restore old SR 3883 mov.l %a0,%a1 # make copy for plpaw1 3884 mov.l %a0,%a2 # make copy for plpaw2 3887 mov.l %d2,%d3 # d3 = update[7:0] 3891 mov.w %sr,%d7 # save current SR 3909 mov.l &0x80000000,%a1 # assert LOCK* buscr value 3910 mov.l &0xa0000000,%a2 # assert LOCKE* buscr value 3911 mov.l &0x00000000,%a3 # buscr unlock value 4014 mov.w %d7,%sr # restore old SR 4026 mov.w %d7,%sr # restore old SR 4037 mov.l %a0,%a1 # make copy for plpaw1 4038 mov.l %a0,%a2 # make copy for plpaw2 4041 mov.l %a0,%d1 # byte or word misaligned? 4045 mov.l %d2,%d3 # d3 = update[15:0] 4049 mov.w %sr,%d7 # save current SR 4067 mov.l &0x80000000,%a1 # assert LOCK* buscr value 4068 mov.l &0xa0000000,%a2 # assert LOCKE* buscr value 4069 mov.l &0x00000000,%a3 # buscr unlock value 4170 mov.w %d7,%sr # restore old SR 4182 mov.w %d7,%sr # restore old SR 4189 mov.l %d2,%d5 # d5 = Update[7:0] 4191 mov.l %d2,%d3 # d3 = Update[23:8] 4195 mov.w %sr,%d7 # save current SR 4213 mov.l &0x80000000,%a1 # assert LOCK* buscr value 4214 mov.l &0xa0000000,%a2 # assert LOCKE* buscr value 4215 mov.l &0x00000000,%a3 # buscr unlock value
|
H A D | ilsp.S | 115 mov.w %cc,DIV64_CC(%a6) 130 mov.w %cc,DIV64_CC(%a6) 134 mov.l 0x8(%a6),%d7 # fetch divisor 138 mov.l 0xc(%a6), %d5 # get dividend hi 139 mov.l 0x10(%a6), %d6 # get dividend lo 159 mov.w &0x0, %cc # clear 'X' cc bit 203 mov.b NDIVISOR(%a6), %d0 224 mov.w DIV64_CC(%a6),%cc 243 mov.l 0xc(%a6), %d5 # get dividend hi 244 mov.l 0x10(%a6), %d6 # get dividend lo 248 mov.w DIV64_CC(%a6),%cc 253 mov.l 0xc(%a6),([0x14,%a6]) 254 mov.l 0x10(%a6),([0x14,%a6],0x4) 256 mov.w DIV64_CC(%a6),%cc 301 mov.w %d6, %d5 # rb + u3 305 mov.w %d5, %d1 # first quotient word 307 mov.w %d6, %d5 # rb + u4 312 mov.w %d5, %d1 # 2nd quotient 'digit' 315 mov.l %d1, %d6 # and quotient 342 mov.l %d7, %d3 # divisor 343 mov.l %d5, %d2 # dividend mslw 348 mov.w &0xffff, %d1 # use max trial quotient word 351 mov.l %d5, %d1 361 mov.l %d6, -(%sp) 364 lddadj1: mov.l %d7, %d3 365 mov.l %d1, %d2 369 mov.l %d5, %d4 # U1U2 374 mov.w %d4,%d0 375 mov.w %d6,%d4 # insert lower word (U3) 389 mov.l %d5, -(%sp) # save %d5 (%d6 already saved) 390 mov.l %d1, %d6 392 mov.l %d7, %d5 394 mov.l %d5, %d2 # now %d2,%d3 are trial*divisor 395 mov.l %d6, %d3 396 mov.l (%sp)+, %d5 # restore dividend 397 mov.l (%sp)+, %d6 406 mov.l %d7, %d3 411 mov.l %d7, %d3 420 mov.w %d1, DDQUOTIENT(%a6) 424 mov.w %d6, %d5 430 mov.w %d1, DDQUOTIENT+2(%a6) 432 mov.w %d5, %d6 435 mov.l DDNORMAL(%a6), %d7 # get norm shift count 443 mov.l %d6, %d5 # remainder 444 mov.l DDQUOTIENT(%a6), %d6 # quotient 453 mov.l %d6, %d2 454 mov.l %d6, %d3 455 mov.l %d5, %d4 517 mov.w %cc,MUL64_CC(%a6) # save incoming ccodes 519 mov.l 0x8(%a6),%d0 # store multiplier in d0 522 mov.l 0xc(%a6),%d1 # get multiplicand in d1 546 mov.l %d0,%d2 # mr in d2 547 mov.l %d0,%d3 # mr in d3 548 mov.l %d1,%d4 # md in d4 580 mov.w MUL64_CC(%a6),%d4 586 mov.w %d4,%cc 609 mov.w MUL64_CC(%a6),%d4 612 mov.w %d4,%cc # set 'Z' ccode bit 628 mov.w %cc,MUL64_CC(%a6) # save incoming ccodes 630 mov.l 0x8(%a6),%d0 # store multiplier in d0 633 mov.l 0xc(%a6),%d1 # get multiplicand in d1 672 mov.l %d0,%d2 # mr in d2 673 mov.l %d0,%d3 # mr in d3 674 mov.l %d1,%d4 # md in d4 717 mov.w MUL64_CC(%a6),%d4 723 mov.w %d4,%cc 746 mov.w MUL64_CC(%a6),%d4 749 mov.w %d4,%cc # set 'Z' ccode bit 797 mov.w %cc,CMP2_CC(%a6) 798 mov.l 0x8(%a6), %d2 # get regval 800 mov.b ([0xc,%a6],0x0),%d0 801 mov.b ([0xc,%a6],0x1),%d1 816 mov.w %cc,CMP2_CC(%a6) 817 mov.l 0x8(%a6), %d2 # get regval 819 mov.w ([0xc,%a6],0x0),%d0 820 mov.w ([0xc,%a6],0x2),%d1 835 mov.w %cc,CMP2_CC(%a6) 836 mov.l 0x8(%a6), %d2 # get regval 838 mov.l ([0xc,%a6],0x0),%d0 839 mov.l ([0xc,%a6],0x4),%d1 851 mov.w %cc,CMP2_CC(%a6) 852 mov.l 0x8(%a6), %d2 # get regval 854 mov.b ([0xc,%a6],0x0),%d0 855 mov.b ([0xc,%a6],0x1),%d1 874 mov.w %cc,CMP2_CC(%a6) 875 mov.l 0x8(%a6), %d2 # get regval 877 mov.w ([0xc,%a6],0x0),%d0 878 mov.w ([0xc,%a6],0x2),%d1 897 mov.w %cc,CMP2_CC(%a6) 898 mov.l 0x8(%a6), %d2 # get regval 900 mov.l ([0xc,%a6],0x0),%d0 901 mov.l ([0xc,%a6],0x4),%d1 912 mov.w %cc, %d3 # fetch resulting ccodes 917 mov.w %cc, %d4 # fetch resulting ccodes 921 mov.w CMP2_CC(%a6), %d4 # fetch old ccodes 924 mov.w %d4,%cc # save new ccodes
|
H A D | pfpsp.S | 97 mov.l %d0,-(%sp) 98 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0 100 mov.l 0x4(%sp),%d0 105 mov.l %d0,-(%sp) 106 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0 108 mov.l 0x4(%sp),%d0 113 mov.l %d0,-(%sp) 114 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0 116 mov.l 0x4(%sp),%d0 121 mov.l %d0,-(%sp) 122 mov.l (_060FPSP_TABLE-0x80+_off_inex,%pc),%d0 124 mov.l 0x4(%sp),%d0 129 mov.l %d0,-(%sp) 130 mov.l (_060FPSP_TABLE-0x80+_off_bsun,%pc),%d0 132 mov.l 0x4(%sp),%d0 137 mov.l %d0,-(%sp) 138 mov.l (_060FPSP_TABLE-0x80+_off_operr,%pc),%d0 140 mov.l 0x4(%sp),%d0 145 mov.l %d0,-(%sp) 146 mov.l (_060FPSP_TABLE-0x80+_off_snan,%pc),%d0 148 mov.l 0x4(%sp),%d0 153 mov.l %d0,-(%sp) 154 mov.l (_060FPSP_TABLE-0x80+_off_dz,%pc),%d0 156 mov.l 0x4(%sp),%d0 161 mov.l %d0,-(%sp) 162 mov.l (_060FPSP_TABLE-0x80+_off_fline,%pc),%d0 164 mov.l 0x4(%sp),%d0 169 mov.l %d0,-(%sp) 170 mov.l (_060FPSP_TABLE-0x80+_off_fpu_dis,%pc),%d0 172 mov.l 0x4(%sp),%d0 177 mov.l %d0,-(%sp) 178 mov.l (_060FPSP_TABLE-0x80+_off_trap,%pc),%d0 180 mov.l 0x4(%sp),%d0 185 mov.l %d0,-(%sp) 186 mov.l (_060FPSP_TABLE-0x80+_off_trace,%pc),%d0 188 mov.l 0x4(%sp),%d0 193 mov.l %d0,-(%sp) 194 mov.l (_060FPSP_TABLE-0x80+_off_access,%pc),%d0 196 mov.l 0x4(%sp),%d0 203 mov.l %d0,-(%sp) 204 mov.l (_060FPSP_TABLE-0x80+_off_imr,%pc),%d0 206 mov.l 0x4(%sp),%d0 211 mov.l %d0,-(%sp) 212 mov.l (_060FPSP_TABLE-0x80+_off_dmr,%pc),%d0 214 mov.l 0x4(%sp),%d0 219 mov.l %d0,-(%sp) 220 mov.l (_060FPSP_TABLE-0x80+_off_dmw,%pc),%d0 222 mov.l 0x4(%sp),%d0 227 mov.l %d0,-(%sp) 228 mov.l (_060FPSP_TABLE-0x80+_off_irw,%pc),%d0 230 mov.l 0x4(%sp),%d0 235 mov.l %d0,-(%sp) 236 mov.l (_060FPSP_TABLE-0x80+_off_irl,%pc),%d0 238 mov.l 0x4(%sp),%d0 243 mov.l %d0,-(%sp) 244 mov.l (_060FPSP_TABLE-0x80+_off_drb,%pc),%d0 246 mov.l 0x4(%sp),%d0 251 mov.l %d0,-(%sp) 252 mov.l (_060FPSP_TABLE-0x80+_off_drw,%pc),%d0 254 mov.l 0x4(%sp),%d0 259 mov.l %d0,-(%sp) 260 mov.l (_060FPSP_TABLE-0x80+_off_drl,%pc),%d0 262 mov.l 0x4(%sp),%d0 267 mov.l %d0,-(%sp) 268 mov.l (_060FPSP_TABLE-0x80+_off_dwb,%pc),%d0 270 mov.l 0x4(%sp),%d0 275 mov.l %d0,-(%sp) 276 mov.l (_060FPSP_TABLE-0x80+_off_dww,%pc),%d0 278 mov.l 0x4(%sp),%d0 283 mov.l %d0,-(%sp) 284 mov.l (_060FPSP_TABLE-0x80+_off_dwl,%pc),%d0 286 mov.l 0x4(%sp),%d0 649 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 650 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 653 mov.l %d0,EXC_OPWORD(%a6) 668 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 685 mov.b %d0,DTAG(%a6) # save dst optype tag 689 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 690 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 691 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 692 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) 693 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) 694 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) 697 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 699 mov.b 1+EXC_CMDREG(%a6),%d1 711 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 743 mov.w &0xe005,2+FP_SRC(%a6) # save exc status 761 mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 762 mov.w &0xe001,2+FP_SRC(%a6) # save exc status 778 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 779 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 780 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 783 mov.b &NORM,STAG(%a6) # set src optype tag 786 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 814 mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 889 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 890 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 893 mov.l %d0,EXC_OPWORD(%a6) 906 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 928 mov.b %d0,DTAG(%a6) # save dst optype tag 932 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 933 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 934 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 935 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) 936 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) 937 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) 940 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 942 mov.b 1+EXC_CMDREG(%a6),%d1 954 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 1005 mov.w &0xe003,2+FP_SRC(%a6) # save exc status 1035 mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 1036 mov.w &0xe001,2+FP_SRC(%a6) # save exc status 1052 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 1053 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 1054 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 1057 mov.b &NORM,STAG(%a6) # set src optype tag 1060 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 1088 mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 1216 mov.l %usp,%a0 # fetch user stack pointer 1217 mov.l %a0,EXC_A7(%a6) # save on stack 1224 mov.l %a0,EXC_A7(%a6) # save on stack 1231 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1235 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 1275 mov.b %d0,STAG(%a6) # save src optype tag 1294 mov.b %d0,DTAG(%a6) # save dst optype tag 1298 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1305 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr 1322 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set 1327 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1398 mov.l %d0,-(%sp) # save d0 1400 mov.l (%sp)+,%d0 # restore d0 1402 mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status 1419 mov.w &0x4,%d0 1422 mov.w &0x03,%d0 1439 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1469 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1516 mov.w FP_SRC_EX(%a6),%d0 # get exponent 1523 mov.b %d0,STAG(%a6) 1527 mov.b &DENORM,STAG(%a6) 1531 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1535 mov.l (%a6),EXC_A6(%a6) # in case a6 changes 1550 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1555 mov.l EXC_A6(%a6),(%a6) # in case a6 changed 1565 mov.l EXC_A7(%a6),%a0 # restore a7 1566 mov.l %a0,%usp 1597 mov.l (%a6),%a6 # restore frame pointer 1599 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 1600 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 1603 mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) 1604 mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) 1605 mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) 1649 mov.w &0x2024,0x6(%sp) 1659 mov.w (tbl_fu_out.b,%pc,%d0.w*2),%d0 1680 mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd8 1681 mov.w &0xe006,2+FP_SRC(%a6) 1695 mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 1696 mov.w &0xe004,2+FP_SRC(%a6) 1712 mov.w &0x30d4,EXC_VOFF(%a6) # vector offset = 0xd4 1713 mov.w &0xe005,2+FP_SRC(%a6) 1726 mov.l EXC_A6(%a6),(%a6) # restore a6 1731 mov.l EXC_A7(%a6),%a0 # restore a7 whether we need 1732 mov.l %a0,%usp # to or not... 1741 mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc 1742 mov.w &0xe003,2+FP_SRC(%a6) 1765 mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc 1766 mov.w &0xe003,2+FP_DST(%a6) 1770 mov.l (%a6),%a6 # restore frame pointer 1772 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 1773 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 1774 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 1777 mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) 1778 mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) 1779 mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) 1793 mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 1794 mov.w &0xe001,2+FP_SRC(%a6) 1820 mov.b %d0,STAG(%a6) # save src optype tag 1839 mov.b %d0,DTAG(%a6) # save dst optype tag 1843 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1850 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr 1867 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1872 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1885 mov.l EXC_A7(%a6),%a0 # update user a7 1886 mov.l %a0,%usp 1914 mov.l 0x4(%sp),0x10(%sp) 1915 mov.l 0x0(%sp),0xc(%sp) 1982 mov.l EXC_A7(%a6),%a0 # update user a7 1983 mov.l %a0,%usp 1986 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2006 mov.w &0x3,%d0 2010 mov.w &0x4,%d0 2017 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2028 mov.l 0x4(%sp),0x10(%sp) 2029 mov.l 0x0(%sp),0xc(%sp) 2055 mov.w &0x2024,0x6(%sp) 2085 mov.b %d0,STAG(%a6) # save src optype tag 2088 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 2092 mov.l (%a6),EXC_A6(%a6) # in case a6 changes 2107 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2111 mov.l EXC_A6(%a6),(%a6) # restore a6 2116 mov.l EXC_A7(%a6),%a0 # update user a7 2117 mov.l %a0,%usp 2142 mov.l (%a6),%a6 # restore frame pointer 2144 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2145 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2148 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) 2149 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) 2150 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) 2164 mov.l EXC_A6(%a6),(%a6) # restore a6 2177 mov.l EXC_A7(%a6),%a0 2178 mov.l %a0,%usp 2192 mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd0 2193 mov.w &0xe006,2+FP_SRC(%a6) # set fsave status 2197 mov.l (%a6),%a6 # restore frame pointer 2199 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2200 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2201 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 2204 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) 2205 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) 2206 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) 2217 mov.l EXC_A7(%a6),%a0 2218 mov.l %a0,%usp 2232 mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 2233 mov.w &0xe004,2+FP_SRC(%a6) # set fsave status 2237 mov.l (%a6),%a6 # restore frame pointer 2239 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2240 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2241 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 2244 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) 2245 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) 2246 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) 2257 mov.l EXC_A7(%a6),%a0 2258 mov.l %a0,%usp 2272 mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 2273 mov.w &0xe001,2+FP_SRC(%a6) # set fsave status 2277 mov.l (%a6),%a6 # restore frame pointer 2279 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2280 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2281 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 2284 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) 2285 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) 2286 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) 2310 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2317 mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man) 2320 mov.l %d1,FP_SRC_HI(%a6) # insert new hi(man) 2327 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2335 mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign 2338 mov.w &0x3c01,%d1 # pass denorm threshold 2340 mov.w &0x3c00,%d0 # new exponent 2346 mov.w %d0,FP_SRC_EX(%a6) # insert new exponent 2355 mov.l 0x0(%a0),FP_DST_EX(%a6) 2356 mov.l 0x4(%a0),FP_DST_HI(%a6) 2357 mov.l 0x8(%a0),FP_DST_LO(%a6) 2457 mov.l %d0,-(%sp) # save d0 2461 mov.l (%sp)+,%d0 # restore d0 2470 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) 2472 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 2475 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2508 mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to #<data> 2510 mov.l &0xc,%d0 # pass: 12 bytes 2520 mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to #<data> 2522 mov.l &0xc,%d0 # pass: 12 bytes 2535 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 2553 mov.b %d0,STAG(%a6) # could be ANYTHING!!! 2557 mov.b %d0,STAG(%a6) # set new optype tag 2572 mov.b %d0,DTAG(%a6) # could be ANYTHING!!! 2576 mov.b %d0,DTAG(%a6) # set new optype tag 2591 mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec 2593 mov.b 1+EXC_CMDREG(%a6),%d1 2602 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 2619 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2633 mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" 2634 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame 2678 mov.w (tbl_iea_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2686 mov.w &0xe005,2+FP_SRC(%a6) 2690 mov.w &0xe003,2+FP_SRC(%a6) 2693 mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" 2694 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame 2727 mov.l (%sp),-(%sp) # shift stack frame "down" 2728 mov.w 0x8(%sp),0x4(%sp) 2729 mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 2745 mov.l %usp,%a0 2746 mov.l %a0,EXC_A7(%a6) # store current a7 2748 mov.l EXC_A7(%a6),%a0 # load possibly new a7 2749 mov.l %a0,%usp # update usp 2755 mov.l %a0,EXC_A7(%a6) 2771 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2772 mov.l EXC_EXTWPTR(%a6),(EXC_PC,%a6,%d0) 2773 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2776 mov.l %a0,EXC_SR(%a6) 2783 mov.l (%sp)+,%sp 2787 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2788 mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0) 2789 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2790 mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0) 2793 mov.l %a0,EXC_SR(%a6) 2800 mov.l (%sp)+,%sp 2805 mov.b %d1,EXC_VOFF(%a6) # store strg 2806 mov.b %d0,0x1+EXC_VOFF(%a6) # store size 2812 mov.l (%a6),-(%sp) # make a copy of a6 2813 mov.l %d0,-(%sp) # save d0 2814 mov.l %d1,-(%sp) # save d1 2815 mov.l EXC_EXTWPTR(%a6),-(%sp) # make a copy of Next PC 2818 mov.b 0x1+EXC_VOFF(%a6),%d0 # fetch size 2824 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2825 mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0) 2826 mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0) 2827 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2833 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2834 mov.l (%sp)+,(EXC_PC,%a6,%d0) 2835 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2841 mov.b EXC_VOFF(%a6),%d1 # fetch strg 2882 mov.l 0x4(%sp),%d1 2883 mov.l 0x8(%sp),%d0 2884 mov.l 0xc(%sp),%a6 2885 mov.l (%sp)+,%sp 2904 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set Next PC 2933 mov.l (%a6),%a6 # restore frame pointer 2934 mov.w EXC_SR+LOCAL_SIZE(%sp),0x0+LOCAL_SIZE(%sp) 2935 mov.l EXC_PC+LOCAL_SIZE(%sp),0x8+LOCAL_SIZE(%sp) 2936 mov.l EXC_EXTWPTR+LOCAL_SIZE(%sp),0x2+LOCAL_SIZE(%sp) 2937 mov.w &0x2024,0x6+LOCAL_SIZE(%sp) # stk fmt = 0x2; voff = 0x024 2950 mov.l (%sp)+,%d0 # restore d0 2957 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) 2958 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 2961 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2968 mov.l &0x10,%d0 # 16 bytes of instruction 2975 mov.l &0xc,%d0 2987 mov.l EXC_EXTWPTR(%a6),%d0 2990 mov.w %d0,EXC_VOFF(%a6) # store stack shift value 3000 mov.l %d0,-(%sp) # save d0 3001 mov.w 0xc(%sp),0x4(%sp) # move SR 3002 mov.l 0xe(%sp),0x6(%sp) # move Current PC 3004 mov.w 0x12(%sp),%d0 3005 mov.l 0x6(%sp),0x10(%sp) # move Current PC 3007 mov.w &0x402c,0xa(%sp) # insert offset,frame format 3008 mov.l (%sp)+,%d0 # restore d0 3026 mov.l 0x8(%sp),(%sp) # store SR,hi(PC) 3027 mov.w 0xc(%sp),0x4(%sp) # store lo(PC) 3028 mov.w &0x4008,0x6(%sp) # store voff 3029 mov.l 0x2(%sp),0x8(%sp) # store ea 3030 mov.l &0x09428001,0xc(%sp) # store fslw 3049 mov.l (%a6),%a6 3051 mov.l 0x4+LOCAL_SIZE(%sp),-0x8+0x4+LOCAL_SIZE(%sp) 3052 mov.w 0x8+LOCAL_SIZE(%sp),-0x8+0x8+LOCAL_SIZE(%sp) 3053 mov.w &0x4008,-0x8+0xa+LOCAL_SIZE(%sp) 3054 mov.l %a0,-0x8+0xc+LOCAL_SIZE(%sp) 3055 mov.w %d0,-0x8+0x10+LOCAL_SIZE(%sp) 3056 mov.w &0x0001,-0x8+0x12+LOCAL_SIZE(%sp) 3117 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3119 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3122 mov.l %d0,EXC_OPWORD(%a6) 3166 mov.w FP_SRC_EX(%a6),%d1 # fetch exponent 3173 mov.l FP_SRC_HI(%a6),%d1 3177 mov.l FP_SRC_HI(%a6),L_SCR1(%a6) 3181 mov.l &0x7fffffff,%d1 3186 mov.l %d1,L_SCR1(%a6) 3190 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg 3191 mov.w (tbl_operr.b,%pc,%d0.w*2),%a0 3205 mov.b L_SCR1(%a6),%d0 # load positive default result 3208 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3221 mov.w L_SCR1(%a6),%d0 # load positive default result 3224 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3237 mov.l L_SCR1(%a6),%d0 # load positive default result 3240 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3313 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3315 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3318 mov.l %d0,EXC_OPWORD(%a6) 3360 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg 3361 mov.w (tbl_snan.b,%pc,%d0.w*2),%a0 3375 mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN 3379 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3392 mov.w FP_SRC_HI(%a6),%d0 # load upper word of SNAN 3396 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3409 mov.l FP_SRC_HI(%a6),%d0 # load upper longword of SNAN 3413 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3428 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3431 mov.l FP_SRC_HI(%a6),%d1 # load mantissa 3434 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3442 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3445 mov.l %d1,-(%sp) 3446 mov.l FP_SRC_HI(%a6),%d1 # load mantissa 3449 mov.l (%sp)+,%d1 3455 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3458 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa 3459 mov.l %d0,FP_SCR0_EX(%a6) # store to temp space 3460 mov.l &11,%d0 # load shift amt 3463 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa 3466 mov.l %d1,FP_SCR0_HI(%a6) # store to temp space 3467 mov.l FP_SRC_LO(%a6),%d1 # load lo mantissa 3471 mov.l EXC_EA(%a6),%a1 # pass: dst addr 3486 mov.w FP_SRC_EX(%a6),FP_SCR0_EX(%a6) 3488 mov.l FP_SRC_HI(%a6),%d0 3490 mov.l %d0,FP_SCR0_HI(%a6) 3491 mov.l FP_SRC_LO(%a6),FP_SCR0_LO(%a6) 3496 mov.l %usp,%a0 # fetch user stack pointer 3497 mov.l %a0,EXC_A7(%a6) # save on stack for calc_ea() 3498 mov.l (%a6),EXC_A6(%a6) 3501 mov.l %a0,%a1 3502 mov.l %a0,EXC_EA(%a6) # stack correct <ea> 3504 mov.l EXC_A7(%a6),%a0 3505 mov.l %a0,%usp # restore user stack pointer 3506 mov.l EXC_A6(%a6),(%a6) 3519 mov.l (%a6),EXC_A6(%a6) 3522 mov.l %a0,%a1 3523 mov.l %a0,EXC_EA(%a6) # stack correct <ea> 3525 mov.l EXC_A6(%a6),(%a6) 3537 mov.l EXC_A6(%a6),%a6 # restore frame pointer 3539 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 3540 mov.l LOCAL_SIZE+EXC_PC+0x2(%sp),LOCAL_SIZE+EXC_PC+0x2-0xc(%sp) 3541 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 3543 mov.l LOCAL_SIZE+FP_SCR0_EX(%sp),LOCAL_SIZE+EXC_SR(%sp) 3544 mov.l LOCAL_SIZE+FP_SCR0_HI(%sp),LOCAL_SIZE+EXC_PC+0x2(%sp) 3545 mov.l LOCAL_SIZE+FP_SCR0_LO(%sp),LOCAL_SIZE+EXC_EA(%sp) 3605 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3607 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3610 mov.l %d0,EXC_OPWORD(%a6) 3628 mov.w &0xe001,0x2+FP_SRC(%a6) 3650 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 3670 mov.b %d0,DTAG(%a6) # save dst optype tag 3674 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 3676 mov.b 1+EXC_CMDREG(%a6),%d1 3682 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 3702 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3703 mov.b 1+EXC_CMDREG(%a6),%d1 3724 mov.b &NORM,STAG(%a6) # src is a NORM 3727 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3779 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3781 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3784 mov.l %d0,EXC_OPWORD(%a6) 3877 mov.l %d0, %a0 # move # bytes to %a0 3879 mov.b 1+EXC_OPWORD(%a6), %d0 # fetch opcode word 3880 mov.l %d0, %d1 # make a copy 3896 mov.l EXC_EA(%a6),%a0 # return <ea> 3902 mov.b &immed_flg,SPCOND_FLG(%a6) 3909 mov.l %a0,%d0 # pass amt to inc by 3912 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 3920 mov.l %a0,%d0 # pass amt to dec by 3923 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 3930 mov.l %a0,EXC_EA(%a6) # put correct <ea> on stack 3962 mov.b 1+EXC_OPWORD(%a6),%d0 # fetch opcode word 3963 mov.l %d0,%d1 # make a copy 3974 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 3981 mov.w (tbl_ceaf_pi.b,%pc,%d1.w*2),%d1 3982 mov.l EXC_EA(%a6),%a0 4018 mov.b &mia7_flg,SPCOND_FLG(%a6) 4026 mov.w (tbl_ceaf_pd.b,%pc,%d1.w*2),%d1 4027 mov.l EXC_EA(%a6),%a0 4044 mov.l %a0,EXC_DREGS+0x8(%a6) 4047 mov.l %a0,EXC_DREGS+0xc(%a6) 4050 mov.l %a0,%a2 4053 mov.l %a0,%a3 4056 mov.l %a0,%a4 4059 mov.l %a0,%a5 4062 mov.l %a0,EXC_A6(%a6) 4065 mov.l %a0,EXC_A7(%a6) 4066 mov.b &mda7_flg,SPCOND_FLG(%a6) 4268 mov.b 1+EXC_EXTWORD(%a6),%d1 # fetch extword 4277 mov.l %d0,-(%sp) # save strg 4278 mov.b (tbl_fmovm_size.w,%pc,%d0),%d0 4279 mov.l %d0,-(%sp) # save size 4281 mov.l (%sp)+,%d0 # restore size 4282 mov.l (%sp)+,%d1 # restore strg 4304 mov.b (tbl_fmovm_convert.w,%pc,%d1.w*1),%d1 4320 mov.l %a0,%a1 # move <ea> to a1 4328 mov.l 0x0+EXC_FP0(%a6),(%a0)+ # yes 4329 mov.l 0x4+EXC_FP0(%a6),(%a0)+ 4330 mov.l 0x8+EXC_FP0(%a6),(%a0)+ 4336 mov.l 0x0+EXC_FP1(%a6),(%a0)+ # yes 4337 mov.l 0x4+EXC_FP1(%a6),(%a0)+ 4338 mov.l 0x8+EXC_FP1(%a6),(%a0)+ 4383 mov.l %a1,L_SCR1(%a6) 4386 mov.l %d0,-(%sp) # save size 4389 mov.l (%sp)+,%d0 4401 mov.l %a0,L_SCR1(%a6) 4406 mov.l %d1,-(%sp) # save bit string for later 4407 mov.l %d0,-(%sp) # save # of bytes 4411 mov.l (%sp)+,%d0 # retrieve # of bytes 4416 mov.l (%sp)+,%d1 # load bit string 4423 mov.l (%a0)+,0x0+EXC_FP0(%a6) # yes 4424 mov.l (%a0)+,0x4+EXC_FP0(%a6) 4425 mov.l (%a0)+,0x8+EXC_FP0(%a6) 4431 mov.l (%a0)+,0x0+EXC_FP1(%a6) # yes 4432 mov.l (%a0)+,0x4+EXC_FP1(%a6) 4433 mov.l (%a0)+,0x8+EXC_FP1(%a6) 4573 mov.l %d0,%a0 # move # bytes to a0 4577 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word 4578 mov.w %d0,%d1 # make a copy 4584 mov.w (tbl_fea_mode.b,%pc,%d0.w*2),%d0 # fetch jmp distance 4665 mov.l EXC_DREGS+0x8(%a6),%a0 # Get current a0 4669 mov.l EXC_DREGS+0xc(%a6),%a0 # Get current a1 4673 mov.l %a2,%a0 # Get current a2 4677 mov.l %a3,%a0 # Get current a3 4681 mov.l %a4,%a0 # Get current a4 4685 mov.l %a5,%a0 # Get current a5 4689 mov.l (%a6),%a0 # Get current a6 4693 mov.l EXC_A7(%a6),%a0 # Get current a7 4700 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 4701 mov.l %d0,%d1 4703 mov.l %d1,EXC_DREGS+0x8(%a6) # Save incr value 4704 mov.l %d0,%a0 4708 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 4709 mov.l %d0,%d1 4711 mov.l %d1,EXC_DREGS+0xc(%a6) # Save incr value 4712 mov.l %d0,%a0 4716 mov.l %a2,%d0 # Get current a2 4717 mov.l %d0,%d1 4719 mov.l %d1,%a2 # Save incr value 4720 mov.l %d0,%a0 4724 mov.l %a3,%d0 # Get current a3 4725 mov.l %d0,%d1 4727 mov.l %d1,%a3 # Save incr value 4728 mov.l %d0,%a0 4732 mov.l %a4,%d0 # Get current a4 4733 mov.l %d0,%d1 4735 mov.l %d1,%a4 # Save incr value 4736 mov.l %d0,%a0 4740 mov.l %a5,%d0 # Get current a5 4741 mov.l %d0,%d1 4743 mov.l %d1,%a5 # Save incr value 4744 mov.l %d0,%a0 4748 mov.l (%a6),%d0 # Get current a6 4749 mov.l %d0,%d1 4751 mov.l %d1,(%a6) # Save incr value 4752 mov.l %d0,%a0 4756 mov.b &mia7_flg,SPCOND_FLG(%a6) # set "special case" flag 4758 mov.l EXC_A7(%a6),%d0 # Get current a7 4759 mov.l %d0,%d1 4761 mov.l %d1,EXC_A7(%a6) # Save incr value 4762 mov.l %d0,%a0 4769 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 4771 mov.l %d0,EXC_DREGS+0x8(%a6) # Save decr value 4772 mov.l %d0,%a0 4776 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 4778 mov.l %d0,EXC_DREGS+0xc(%a6) # Save decr value 4779 mov.l %d0,%a0 4783 mov.l %a2,%d0 # Get current a2 4785 mov.l %d0,%a2 # Save decr value 4786 mov.l %d0,%a0 4790 mov.l %a3,%d0 # Get current a3 4792 mov.l %d0,%a3 # Save decr value 4793 mov.l %d0,%a0 4797 mov.l %a4,%d0 # Get current a4 4799 mov.l %d0,%a4 # Save decr value 4800 mov.l %d0,%a0 4804 mov.l %a5,%d0 # Get current a5 4806 mov.l %d0,%a5 # Save decr value 4807 mov.l %d0,%a0 4811 mov.l (%a6),%d0 # Get current a6 4813 mov.l %d0,(%a6) # Save decr value 4814 mov.l %d0,%a0 4818 mov.b &mda7_flg,SPCOND_FLG(%a6) # set "special case" flag 4820 mov.l EXC_A7(%a6),%d0 # Get current a7 4822 mov.l %d0,EXC_A7(%a6) # Save decr value 4823 mov.l %d0,%a0 4830 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4837 mov.w %d0,%a0 # sign extend displacement 4843 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4850 mov.w %d0,%a0 # sign extend displacement 4856 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4863 mov.w %d0,%a0 # sign extend displacement 4869 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4876 mov.w %d0,%a0 # sign extend displacement 4882 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4889 mov.w %d0,%a0 # sign extend displacement 4895 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4902 mov.w %d0,%a0 # sign extend displacement 4908 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4915 mov.w %d0,%a0 # sign extend displacement 4921 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4928 mov.w %d0,%a0 # sign extend displacement 4942 mov.l %d0,-(%sp) 4944 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4951 mov.l (%sp)+,%a0 4956 mov.l %d0,L_SCR1(%a6) # hold opword 4958 mov.l %d0,%d1 4965 mov.l %d2,-(%sp) # save d2 4966 mov.l L_SCR1(%a6),%d2 # fetch opword 4972 mov.l %d2,%d1 4982 mov.l (%sp)+,%d2 # restore old d2 4989 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4996 mov.w %d0,%a0 # return <ea> in a0 5003 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5010 mov.l %d0,%a0 # return <ea> in a0 5017 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5024 mov.w %d0,%a0 # sign extend displacement 5039 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5046 mov.l EXC_EXTWPTR(%a6),%a0 # put base in a0 5052 mov.l %d0,L_SCR1(%a6) # store opword 5054 mov.l %d0,%d1 # make extword copy 5061 mov.l %d2,-(%sp) # save d2 5062 mov.l L_SCR1(%a6),%d2 # fetch opword 5068 mov.l %d2,%d1 5078 mov.l (%sp)+,%d2 # restore temp register 5091 mov.l %d0,%d5 # put extword in d5 5092 mov.l %a0,%d3 # put base in d3 5099 mov.l %d0,L_SCR1(%a6) # save d0 (opword) 5104 mov.l %d0,%d2 # put index in d2 5105 mov.l L_SCR1(%a6),%d5 5106 mov.l %a0,%d3 5132 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5142 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5163 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5173 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5187 mov.l %d0,%d4 5192 mov.l %d3,%a0 5204 mov.l %d3,%a0 5215 mov.l %d3,%d0 5217 mov.l %d0,%a0 5224 mov.l %d3,%a0 5227 mov.w &0x0101,%d0 5236 mov.w &0x00e1,%d0 5241 mov.w &0x0161,%d0 5244 mov.l L_SCR1(%a6),%a0 5286 mov.b EXC_EXTWORD(%a6),%d0 # fetch reg select bits 5296 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5303 mov.l %d0,USER_FPSR(%a6) # store new FPSR to stack 5304 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5311 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 5316 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5323 mov.l %d0,USER_FPCR(%a6) # store new FPCR to stack 5324 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5331 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 5336 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5343 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 5344 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5351 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 5356 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5363 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 5364 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5371 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 5372 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 5379 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to mem 5414 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 5415 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 5416 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 5417 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 5418 mov.w SRC_EX(%a0),%d0 5419 mov.w DST_EX(%a1),%d1 5420 mov.w %d0,FP_SCR0_EX(%a6) 5421 mov.w %d1,FP_SCR1_EX(%a6) 5425 mov.w %d0,L_SCR1(%a6) # store src exponent 5426 mov.w %d1,2+L_SCR1(%a6) # store dst exponent 5434 mov.l %d0,-(%sp) # save scale factor 5442 mov.w %d0,L_SCR1(%a6) # inset new exp 5445 mov.w 2+L_SCR1(%a6),%d0 5451 mov.w L_SCR1(%a6),%d0 5453 mov.w FP_SCR0_EX(%a6),%d1 5456 mov.w %d0,FP_SCR0_EX(%a6) # insert new dst exponent 5458 mov.l (%sp)+,%d0 # return SCALE factor 5465 mov.l (%sp)+,%d0 # return SCALE factor 5471 mov.l %d0,-(%sp) # save scale factor 5478 mov.w %d0,2+L_SCR1(%a6) # inset new exp 5481 mov.w L_SCR1(%a6),%d0 5487 mov.w 2+L_SCR1(%a6),%d0 5489 mov.w FP_SCR1_EX(%a6),%d1 5492 mov.w %d0,FP_SCR1_EX(%a6) # insert new dst exponent 5494 mov.l (%sp)+,%d0 # return SCALE factor 5501 mov.l (%sp)+,%d0 # return SCALE factor 5531 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp} 5532 mov.w %d1,%d0 # make a copy 5539 mov.w %d0,FP_SCR0_EX(%a6) # insert biased exponent 5545 mov.l &0x3fff,%d0 5554 mov.l %d0,%d1 # prepare for op_norm call 5588 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp} 5598 mov.l &0x3fff,%d0 5606 mov.l &0x3ffe,%d0 5658 mov.w FP_SCR1_EX(%a6),%d1 # extract operand's {sgn,exp} 5659 mov.w %d1,%d0 # make a copy 5666 mov.w %d0,FP_SCR1_EX(%a6) # insert biased exponent 5672 mov.l &0x3fff,%d0 5680 mov.l %d0,%d1 # prepare for op_norm call 5841 mov.w (tbl_thresh.b,%pc,%d0.w*2), %d1 # load prec threshold 5842 mov.w %d1, %d0 # copy d1 into d0 5861 mov.l &0x20000000, %d0 # set sticky bit in return value 5862 mov.w %d1, FTEMP_EX(%a0) # load exp with threshold 5890 mov.l FTEMP_LO(%a0), FTEMP_LO2(%a6) # make FTEMP_LO copy 5891 mov.l %d0, GRS(%a6) # place g,r,s after it 5897 mov.l %d1, %d0 # copy the denorm threshold 5910 mov.l GRS(%a6), %d0 # restore original g,r,s 5937 mov.l %d2, -(%sp) # create temp storage 5939 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 5940 mov.l &32, %d0 5945 mov.b GRS(%a6), %d2 5953 mov.l %d2, FTEMP_HI(%a0) # store new FTEMP_HI 5954 mov.l %d1, FTEMP_LO(%a0) # store new FTEMP_LO 5962 mov.l (%sp)+, %d2 # restore temp register 5989 mov.l %d2, -(%sp) # create temp storage 5991 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 5993 mov.l &0x20, %d0 5999 mov.b GRS(%a6), %d2 6010 mov.l %d1, %d0 # move new G,R,S to %d0 6014 mov.l %d1, %d0 # move new G,R,S to %d0 6019 mov.l %d2, FTEMP_LO(%a0) # store FTEMP_LO 6022 mov.l (%sp)+,%d2 # restore temp register 6032 mov.w %d0, FTEMP_EX(%a0) # insert denorm threshold 6046 mov.l &0x20000000, %d0 # set sticky bit 6070 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 6071 mov.l %d0, %d1 # make a copy 6098 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 6184 mov.w (tbl_mode.b,%pc,%d1.w*2), %a1 # load jump offset 6202 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 6219 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 6375 mov.l &30, %d2 # of the sgl prec. limits 6377 mov.l FTEMP_HI(%a0), %d2 # get word 2 for s-bit test 6400 mov.l &30, %d2 # of the dbl prec. limits 6402 mov.l FTEMP_LO(%a0), %d2 # get lower mantissa for s-bit test 6412 mov.l %d3, %d0 # return grs to d0 6440 mov.l %d2, -(%sp) # create some temp regs 6441 mov.l %d3, -(%sp) 6443 mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) 6444 mov.l FTEMP_LO(%a0), %d1 # load lo(mantissa) 6456 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 6457 mov.l %d1, FTEMP_LO(%a0) # store new lo(man) 6459 mov.l %d2, %d0 # return shift amount 6461 mov.l (%sp)+, %d3 # restore temp regs 6462 mov.l (%sp)+, %d2 6471 mov.l %d1, FTEMP_HI(%a0) # store hi(man) 6474 mov.l %d2, %d0 # return shift amount 6476 mov.l (%sp)+, %d3 # restore temp regs 6477 mov.l (%sp)+, %d2 6520 mov.w FTEMP_EX(%a0), %d1 # extract exponent 6530 mov.w FTEMP_EX(%a0), %d0 # load old exponent 6533 mov.w %d1, FTEMP_EX(%a0) # insert new exponent 6537 mov.b &NORM, %d0 # return new optype tag 6548 mov.l %d0, FTEMP_HI(%a0) # save new hi(man) 6550 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 6552 mov.l %d0, FTEMP_LO(%a0) # save new lo(man) 6556 mov.b &DENORM, %d0 # return new optype tag 6565 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 6568 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 6573 mov.b &DENORM, %d0 # return new optype tag 6582 mov.b &ZERO, %d0 # fix optype tag 6609 mov.w FTEMP_EX(%a0), %d0 # extract exponent 6617 mov.b &NORM, %d0 6628 mov.b &ZERO, %d0 6631 mov.b &DENORM, %d0 6642 mov.b &ZERO, %d0 6645 mov.b &UNNORM, %d0 6650 mov.l FTEMP_HI(%a0), %d0 6654 mov.b &INF, %d0 6659 mov.b &QNAN, %d0 6662 mov.b &SNAN, %d0 6687 mov.l FTEMP(%a0), %d0 6688 mov.l %d0, %d1 6697 mov.b &NORM, %d0 6705 mov.b &ZERO, %d0 6708 mov.b &DENORM, %d0 6716 mov.b &INF, %d0 6722 mov.b &SNAN, %d0 6725 mov.b &QNAN, %d0 6750 mov.l FTEMP(%a0), %d0 6751 mov.l %d0, %d1 6760 mov.b &NORM, %d0 6766 mov.b &ZERO, %d0 6769 mov.b &DENORM, %d0 6775 mov.b &INF, %d0 6781 mov.b &SNAN, %d0 6784 mov.b &QNAN, %d0 6823 mov.l %d1, -(%sp) # save rnd prec,mode on stack 6828 mov.w FTEMP_EX(%a0), %d1 # extract exponent 6831 mov.w %d1, FTEMP_EX(%a0) # insert 16 bit exponent 6833 mov.l %a0, -(%sp) # save operand ptr during calls 6835 mov.l 0x4(%sp),%d0 # pass rnd prec. 6840 mov.l (%sp),%a0 6841 mov.w 0x6(%sp),%d1 # load prec:mode into %d1 6845 mov.w 0x6(%sp),%d1 6850 mov.l (%sp)+, %a0 6887 mov.l %d1,-(%sp) # save rnd prec,mode on stack 6892 mov.w FTEMP_EX(%a0),%d1 # extract exponent 6895 mov.w %d1,FTEMP_EX(%a0) # insert 16 bit exponent 6897 mov.l %a0,-(%sp) # save operand ptr during calls 6902 mov.l (%sp),%a0 6903 mov.w &s_mode,%d1 # force rnd prec = sgl 6905 mov.w 0x6(%sp),%d1 # load rnd mode 6910 mov.l (%sp)+,%a0 6981 mov.w %d1,%d0 # make a copy 6991 mov.w %d1, %d0 # make a copy 6999 mov.b (tbl_ovfl_cc.b,%pc,%d0.w*1), %d0 # fetch result ccodes 7103 mov.w (tbl_fout.b,%pc,%d1.w*2),%a1 # use as index 7138 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 7142 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 7151 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 7157 mov.l SRC_EX(%a0),%d1 7184 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 7188 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 7197 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 7203 mov.l SRC_EX(%a0),%d1 7231 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 7235 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 7244 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 7250 mov.l SRC_EX(%a0),%d1 7268 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 7270 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 7271 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 7277 mov.l %a0,%a1 # pass: dst addr 7279 mov.l &0xc,%d0 # pass: opsize is 12 bytes 7300 mov.b FPCR_ENABLE(%a6),%d0 7328 mov.l EXC_A6(%a6),(%a6) # fix stacked a6 7337 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 7345 mov.w SRC_EX(%a0),%d0 # extract exponent 7372 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 7376 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 7385 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 7398 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 7399 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 7400 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 7401 mov.l %a0,-(%sp) 7413 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 7419 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 7423 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 7432 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 7437 mov.b FPCR_ENABLE(%a6),%d1 7457 mov.l %a0,-(%sp) 7464 mov.l L_SCR3(%a6),%d0 # pass: sgl prec,rnd mode 7469 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 7473 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 7482 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 7487 mov.b FPCR_ENABLE(%a6),%d1 7502 mov.w SRC_EX(%a0),%d1 # fetch current sign 7505 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp 7506 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy hi(man) 7507 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy lo(man) 7522 mov.l (%sp)+,%a0 7524 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 7525 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 7526 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 7540 mov.l (%sp)+,%a0 # restore a0 7542 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 7543 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 7544 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 7551 mov.b 3+L_SCR3(%a6),%d1 7555 mov.b 3+L_SCR3(%a6),%d1 7575 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 7583 mov.w SRC_EX(%a0),%d0 # extract exponent 7609 mov.l EXC_EA(%a6),%a1 # pass: dst addr 7627 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 7628 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 7629 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 7630 mov.l %a0,-(%sp) 7642 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 7647 mov.l %d0,L_SCR1(%a6) 7648 mov.l %d1,L_SCR2(%a6) 7650 mov.l EXC_EA(%a6),%a1 # pass: dst addr 7658 mov.b FPCR_ENABLE(%a6),%d1 7668 mov.w 2+SRC_LO(%a0),%d0 7678 mov.l %a0,-(%sp) 7685 mov.l L_SCR3(%a6),%d0 # pass: dbl prec,rnd mode 7690 mov.l EXC_EA(%a6),%a1 # pass: dst addr 7698 mov.b FPCR_ENABLE(%a6),%d1 7713 mov.w SRC_EX(%a0),%d1 # fetch current sign 7716 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp 7717 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy hi(man) 7718 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy lo(man) 7770 mov.w FTEMP_EX(%a0),%d0 # get exponent 7783 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa 7786 mov.l %d0,L_SCR1(%a6) # put the new exp back on the stack 7787 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa 7788 mov.l &21,%d0 # load shift count 7790 mov.l %d1,L_SCR2(%a6) # build lower lword in memory 7791 mov.l FTEMP_LO(%a0),%d1 # get ls mantissa 7793 mov.l L_SCR2(%a6),%d1 7795 mov.l L_SCR1(%a6),%d0 7835 mov.w FTEMP_EX(%a0),%d0 # get exponent 7848 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa 7857 mov.l %a0,-(%sp) 7859 mov.b STAG(%a6),%d0 # fetch input type 7867 mov.b 1+EXC_CMDREG(%a6),%d1 # fetch dynamic reg 7875 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch static field 7879 mov.l %d0,-(%sp) 7890 mov.l (%sp)+,%d0 7915 mov.l (%sp)+,%a1 # pass: dst addr 7916 mov.l &0xc,%d0 # pass: opsize is 12 bytes 8010 mov.l %d0,L_SCR3(%a6) # store rnd info 8013 mov.b DTAG(%a6),%d1 8019 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 8020 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 8021 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 8023 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 8024 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 8025 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 8028 mov.l %d0,-(%sp) # save scale factor 1 8034 mov.w 2+L_SCR3(%a6),%d1 # fetch precision 8036 mov.l (%sp)+,%d0 # load S.F. 8068 mov.l %d2,-(%sp) # save d2 8069 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 8070 mov.l %d1,%d2 # make a copy 8075 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 8076 mov.l (%sp)+,%d2 # restore d2 8110 mov.b FPCR_ENABLE(%a6),%d1 8118 mov.l L_SCR3(%a6),%d0 # pass rnd prec,mode 8131 mov.l L_SCR3(%a6),%d1 8138 mov.l %d2,-(%sp) # save d2 8139 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 8140 mov.w %d1,%d2 # make a copy 8147 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 8148 mov.l (%sp)+,%d2 # restore d2 8155 mov.l L_SCR3(%a6),%d1 8222 mov.b FPCR_ENABLE(%a6),%d1 8230 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 8242 mov.l L_SCR3(%a6),%d1 8258 mov.l %d2,-(%sp) # save d2 8259 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 8260 mov.l %d1,%d2 # make a copy 8267 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 8268 mov.l (%sp)+,%d2 # restore d2 8273 mov.l L_SCR3(%a6),%d1 8309 mov.l L_SCR3(%a6),%d1 8330 mov.w (tbl_fmul_op.b,%pc,%d1.w*2),%d1 8401 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 8402 mov.b DST_EX(%a1),%d1 8407 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/N 8411 mov.b &z_bmask,FPSR_CC(%a6) # set Z 8425 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 8426 mov.b DST_EX(%a1),%d1 8432 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/N 8436 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 8442 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 8443 mov.b DST_EX(%a1),%d1 8495 mov.l %d0,L_SCR3(%a6) # store rnd info 8497 mov.b STAG(%a6),%d1 # fetch src optype tag 8543 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 8544 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 8545 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 8550 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp 8554 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 8569 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 8570 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 8571 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 8595 mov.l %d2,-(%sp) # save d2 8597 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 8598 mov.w %d1,%d2 # make a copy 8603 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 8604 mov.l (%sp)+,%d2 # restore d2 8612 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 8613 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 8614 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 8636 mov.b FPCR_ENABLE(%a6),%d1 8642 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 8653 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 8654 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 8655 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 8657 mov.l %d2,-(%sp) # save d2 8658 mov.w %d1,%d2 # make a copy 8665 mov.w %d2,FP_SCR1_EX(%a6) # insert new exponent 8667 mov.l (%sp)+,%d2 # restore d2 8687 mov.b FPCR_ENABLE(%a6),%d1 8698 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 8710 mov.l %d2,-(%sp) # save d2 8711 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 8712 mov.l %d1,%d2 # make a copy 8719 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 8720 mov.l (%sp)+,%d2 # restore d2 8766 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 8828 mov.l %d0,L_SCR3(%a6) # store rnd info 8831 mov.b DTAG(%a6),%d1 8841 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 8842 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 8843 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 8845 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 8846 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 8847 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 8850 mov.l %d0,-(%sp) # save scale factor 1 8857 mov.w 2+L_SCR3(%a6),%d1 # fetch precision 8859 mov.l (%sp)+,%d0 # load S.F. 8882 mov.l %d2,-(%sp) # store d2 8883 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 8884 mov.l %d1,%d2 # make a copy 8889 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 8890 mov.l (%sp)+,%d2 # restore d2 8900 mov.l (%sp)+,%d0 # restore scale factor 8904 mov.l %d0,-(%sp) # save scale factor 8919 mov.w (%sp),%d0 # fetch new exponent 8925 mov.l (%sp)+,%d0 8930 mov.b FPCR_ENABLE(%a6),%d1 8937 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 8944 mov.l L_SCR3(%a6),%d1 8951 mov.l %d2,-(%sp) # save d2 8952 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 8953 mov.w %d1,%d2 # make a copy 8960 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 8961 mov.l (%sp)+,%d2 # restore d2 8968 mov.l L_SCR3(%a6),%d1 8992 mov.b FPCR_ENABLE(%a6),%d1 9000 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 9012 mov.l L_SCR3(%a6),%d1 9026 mov.l %d2,-(%sp) # save d2 9027 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 9028 mov.l %d1,%d2 # make a copy 9035 mov.w %d1,FP_SCR0_EX(%a6) # insert new exp 9036 mov.l (%sp)+,%d2 # restore d2 9041 mov.l L_SCR3(%a6),%d1 9077 mov.l L_SCR3(%a6),%d1 9098 mov.w (tbl_fdiv_op.b,%pc,%d1.w*2),%d1 9166 mov.b SRC_EX(%a0),%d0 # result sign is exclusive 9167 mov.b DST_EX(%a1),%d1 # or of input signs. 9171 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/N 9175 mov.b &z_bmask,FPSR_CC(%a6) # set Z 9186 mov.b SRC_EX(%a0),%d0 # load both signs 9187 mov.b DST_EX(%a1),%d1 9191 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/N 9195 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 9206 mov.b DST_EX(%a1),%d0 # load both signs 9207 mov.b SRC_EX(%a0),%d1 9214 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/NEG 9220 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 9269 mov.l %d0,L_SCR3(%a6) # store rnd info 9270 mov.b STAG(%a6),%d1 9285 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 9286 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 9287 mov.w SRC_EX(%a0),%d0 9290 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 9292 mov.w %d0,FP_SCR0_EX(%a6) 9306 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 9307 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 9308 mov.w SRC_EX(%a0),%d0 9311 mov.b &neg_bmask,FPSR_CC(%a6) # yes, set 'N' ccode bit 9313 mov.w %d0,FP_SCR0_EX(%a6) 9330 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp 9334 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 9349 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 9350 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 9351 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 9375 mov.l %d2,-(%sp) # save d2 9377 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp 9378 mov.w %d1,%d2 # make a copy 9383 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 9384 mov.l (%sp)+,%d2 # restore d2 9392 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 9393 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 9394 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 9416 mov.b FPCR_ENABLE(%a6),%d1 9422 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 9433 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 9434 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 9435 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 9437 mov.l %d2,-(%sp) # save d2 9438 mov.l %d1,%d2 # make a copy 9445 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp 9447 mov.l (%sp)+,%d2 # restore d2 9467 mov.b FPCR_ENABLE(%a6),%d1 9478 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 9490 mov.l %d2,-(%sp) # save d2 9491 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 9492 mov.l %d1,%d2 # make a copy 9499 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 9501 mov.l (%sp)+,%d2 # restore d2 9546 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 9570 mov.b STAG(%a6),%d1 9581 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 9605 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 9615 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 9618 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'I','N' ccode bits 9628 mov.b &z_bmask,FPSR_CC(%a6) # set 'N' ccode bit 9631 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 9662 mov.b STAG(%a6),%d1 9706 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) # copy sign, zero exp 9707 mov.b &0x80,FP_SCR0_HI(%a6) # force DENORM ==> small NORM 9719 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 9723 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 9734 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 9737 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits 9768 mov.b STAG(%a6),%d1 9808 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) # copy sign, zero exp 9809 mov.b &0x80,FP_SCR0_HI(%a6) # force DENORM ==> small NORM 9821 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 9825 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 9836 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 9839 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits 9892 mov.l %d0,L_SCR3(%a6) # store rnd info 9893 mov.b STAG(%a6),%d1 9908 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 9909 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 9910 mov.w SRC_EX(%a0),%d1 9912 mov.w %d1,FP_SCR0_EX(%a6) # insert exponent 9926 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 9927 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 9928 mov.w SRC_EX(%a0),%d0 9930 mov.w %d0,FP_SCR0_EX(%a6) # insert exponent 9948 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp 9952 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 9967 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 9968 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 9969 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 9993 mov.l %d2,-(%sp) # save d2 9995 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp 9996 mov.l %d1,%d2 # make a copy 10001 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 10002 mov.l (%sp)+,%d2 # restore d2 10010 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 10011 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 10012 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 10031 mov.b FPCR_ENABLE(%a6),%d1 10037 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 10048 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 10049 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 10050 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 10052 mov.l %d2,-(%sp) # save d2 10053 mov.l %d1,%d2 # make a copy 10060 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp 10062 mov.l (%sp)+,%d2 # restore d2 10082 mov.b FPCR_ENABLE(%a6),%d1 10093 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 10105 mov.l %d2,-(%sp) # save d2 10106 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 10107 mov.l %d1,%d2 # make a copy 10114 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 10116 mov.l (%sp)+,%d2 # restore d2 10158 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 10161 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 10190 mov.b DTAG(%a6),%d1 10205 mov.b %d0,FPSR_CC(%a6) # set ccode bits(no exc bits are set) 10213 mov.w (tbl_fcmp_op.b,%pc,%d1.w*2),%d1 10296 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 10297 mov.l SRC_HI(%a0),%d0 10299 mov.l %d0,FP_SCR0_HI(%a6) 10300 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 10305 mov.l DST_EX(%a1),FP_SCR0_EX(%a6) 10306 mov.l DST_HI(%a1),%d0 10308 mov.l %d0,FP_SCR0_HI(%a6) 10309 mov.l DST_LO(%a1),FP_SCR0_LO(%a6) 10314 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 10315 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 10316 mov.l DST_HI(%a1),%d0 10318 mov.l %d0,FP_SCR1_HI(%a6) 10319 mov.l SRC_HI(%a0),%d0 10321 mov.l %d0,FP_SCR0_HI(%a6) 10322 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 10323 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 10329 mov.b SRC_EX(%a0),%d0 # determine if like signs 10330 mov.b DST_EX(%a1),%d1 10339 mov.b &neg_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 10343 mov.b SRC_EX(%a0),%d0 # determine if like signs 10344 mov.b DST_EX(%a1),%d1 10353 mov.b &neg_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 10391 mov.l %d0,L_SCR3(%a6) # store rnd info 10394 mov.b DTAG(%a6),%d1 10401 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 10402 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 10403 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 10405 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 10406 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 10407 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 10410 mov.l %d0,-(%sp) # save scale factor 1 10439 mov.l %d2,-(%sp) # save d2 10440 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 10441 mov.l %d1,%d2 # make a copy 10446 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 10447 mov.l (%sp)+,%d2 # restore d2 10469 mov.b FPCR_ENABLE(%a6),%d1 10476 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 10486 mov.l %d2,-(%sp) # save d2 10487 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 10488 mov.l %d1,%d2 # make a copy 10495 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 10496 mov.l (%sp)+,%d2 # restore d2 10535 mov.b FPCR_ENABLE(%a6),%d1 10543 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 10563 mov.l %d2,-(%sp) # save d2 10564 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 10565 mov.l %d1,%d2 # make a copy 10572 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 10573 mov.l (%sp)+,%d2 # restore d2 10604 mov.l L_SCR3(%a6),%d1 10625 mov.w (tbl_fsglmul_op.b,%pc,%d1.w*2),%d1 10732 mov.l %d0,L_SCR3(%a6) # store rnd info 10735 mov.b DTAG(%a6),%d1 10745 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 10746 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 10747 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 10749 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 10750 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 10751 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 10754 mov.l %d0,-(%sp) # save scale factor 1 10761 mov.w 2+L_SCR3(%a6),%d1 # fetch precision,mode 10763 mov.l (%sp)+,%d0 10786 mov.l %d2,-(%sp) # save d2 10787 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 10788 mov.l %d1,%d2 # make a copy 10793 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 10794 mov.l (%sp)+,%d2 # restore d2 10812 mov.w (%sp),%d1 # fetch new exponent 10822 mov.b FPCR_ENABLE(%a6),%d1 10829 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 10839 mov.l %d2,-(%sp) # save d2 10840 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 10841 mov.l %d1,%d2 # make a copy 10848 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 10849 mov.l (%sp)+,%d2 # restore d2 10868 mov.b FPCR_ENABLE(%a6),%d1 10876 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 10896 mov.l %d2,-(%sp) # save d2 10897 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 10898 mov.l %d1,%d2 # make a copy 10905 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 10906 mov.l (%sp)+,%d2 # restore d2 10960 mov.w (tbl_fsgldiv_op.b,%pc,%d1.w*2),%d1 11079 mov.l %d0,L_SCR3(%a6) # store rnd info 11082 mov.b DTAG(%a6),%d1 11109 mov.l %d2,-(%sp) # save d2 11113 mov.w 2+L_SCR3(%a6),%d1 11116 mov.w (%sp),%d2 # fetch new sign, exp 11128 mov.w (%sp),%d1 11131 mov.w %d1,(%sp) # insert new exponent 11135 mov.l (%sp)+,%d2 # restore d2 11155 mov.b FPCR_ENABLE(%a6),%d1 11163 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 11167 mov.l (%sp)+,%d2 # restore d2 11171 mov.b L_SCR3(%a6),%d1 11176 mov.w (%sp),%d1 11181 mov.w %d1,(%sp) # insert new exponent 11189 mov.l L_SCR3(%a6),%d1 11218 mov.b FPCR_ENABLE(%a6),%d1 11226 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 11230 mov.l (%sp)+,%d2 # restore d2 11236 mov.l L_SCR3(%a6),%d1 11250 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 11251 mov.l %d1,%d2 # make a copy 11258 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 11263 mov.l L_SCR3(%a6),%d1 11275 mov.l L_SCR3(%a6),%d1 11279 mov.l 0x4(%sp),%d1 # extract hi(man) 11301 mov.l L_SCR3(%a6),%d1 11324 mov.w (tbl_fadd_op.b,%pc,%d1.w*2),%d1 11392 mov.b SRC_EX(%a0),%d0 # are the signs opposite 11393 mov.b DST_EX(%a1),%d1 11402 mov.b &z_bmask,FPSR_CC(%a6) # set Z 11411 mov.b 3+L_SCR3(%a6),%d1 11416 mov.b &z_bmask,FPSR_CC(%a6) # set Z 11421 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set NEG/Z 11429 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 11430 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 11431 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 11439 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 11440 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 11441 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 11453 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11454 mov.b DST_EX(%a1),%d1 11468 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 11478 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 11482 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 11532 mov.l %d0,L_SCR3(%a6) # store rnd info 11535 mov.b DTAG(%a6),%d1 11562 mov.l %d2,-(%sp) # save d2 11566 mov.w 2+L_SCR3(%a6),%d1 11569 mov.w (%sp),%d2 # fetch new exponent 11581 mov.w (%sp),%d1 11584 mov.w %d1,(%sp) # insert new exponent 11588 mov.l (%sp)+,%d2 # restore d2 11608 mov.b FPCR_ENABLE(%a6),%d1 11616 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 11620 mov.l (%sp)+,%d2 # restore d2 11624 mov.b L_SCR3(%a6),%d1 11629 mov.w (%sp),%d1 # fetch {sgn,exp} 11634 mov.w %d1,(%sp) # insert new exponent 11642 mov.l L_SCR3(%a6),%d1 11671 mov.b FPCR_ENABLE(%a6),%d1 11679 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 11683 mov.l (%sp)+,%d2 # restore d2 11689 mov.l L_SCR3(%a6),%d1 11703 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 11704 mov.l %d1,%d2 # make a copy 11711 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 11716 mov.l L_SCR3(%a6),%d1 11728 mov.l L_SCR3(%a6),%d1 11732 mov.l 0x4(%sp),%d1 11754 mov.l L_SCR3(%a6),%d1 11777 mov.w (tbl_fsub_op.b,%pc,%d1.w*2),%d1 11845 mov.b SRC_EX(%a0),%d0 11846 mov.b DST_EX(%a1),%d1 11854 mov.b &z_bmask,FPSR_CC(%a6) # set Z 11863 mov.b 3+L_SCR3(%a6),%d1 11868 mov.b &z_bmask,FPSR_CC(%a6) # set Z 11873 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/NEG 11881 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 11882 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 11883 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 11891 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 11892 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 11893 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 11905 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11906 mov.b DST_EX(%a1),%d1 11917 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 11924 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 11928 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 11977 mov.l %d0,L_SCR3(%a6) # store rnd info 11979 mov.b STAG(%a6),%d1 12009 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12010 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12011 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12028 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12029 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12030 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12056 mov.l %d2,-(%sp) # save d2 12058 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp 12059 mov.l %d1,%d2 # make a copy 12064 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 12065 mov.l (%sp)+,%d2 # restore d2 12073 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12074 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12075 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12111 mov.b FPCR_ENABLE(%a6),%d1 12119 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 12130 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 12131 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 12132 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 12134 mov.l %d2,-(%sp) # save d2 12135 mov.l %d1,%d2 # make a copy 12142 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp 12144 mov.l (%sp)+,%d2 # restore d2 12164 mov.b FPCR_ENABLE(%a6),%d1 12175 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 12187 mov.l %d2,-(%sp) # save d2 12188 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 12189 mov.l %d1,%d2 # make a copy 12196 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 12198 mov.l (%sp)+,%d2 # restore d2 12252 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 12256 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 12264 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 12291 mov.w (tbl_fdreg.b,%pc,%d1.w*2),%d0 12313 mov.l EXC_DREGS+0x0(%a6),%d0 12316 mov.l EXC_DREGS+0x4(%a6),%d0 12319 mov.l %d2,%d0 12322 mov.l %d3,%d0 12325 mov.l %d4,%d0 12328 mov.l %d5,%d0 12331 mov.l %d6,%d0 12334 mov.l %d7,%d0 12337 mov.l EXC_DREGS+0x8(%a6),%d0 12340 mov.l EXC_DREGS+0xc(%a6),%d0 12343 mov.l %a2,%d0 12346 mov.l %a3,%d0 12349 mov.l %a4,%d0 12352 mov.l %a5,%d0 12355 mov.l (%a6),%d0 12358 mov.l EXC_A7(%a6),%d0 12384 mov.w (tbl_sdregl.b,%pc,%d1.w*2),%d1 12398 mov.l %d0,EXC_DREGS+0x0(%a6) 12401 mov.l %d0,EXC_DREGS+0x4(%a6) 12404 mov.l %d0,%d2 12407 mov.l %d0,%d3 12410 mov.l %d0,%d4 12413 mov.l %d0,%d5 12416 mov.l %d0,%d6 12419 mov.l %d0,%d7 12445 mov.w (tbl_sdregw.b,%pc,%d1.w*2),%d1 12459 mov.w %d0,2+EXC_DREGS+0x0(%a6) 12462 mov.w %d0,2+EXC_DREGS+0x4(%a6) 12465 mov.w %d0,%d2 12468 mov.w %d0,%d3 12471 mov.w %d0,%d4 12474 mov.w %d0,%d5 12477 mov.w %d0,%d6 12480 mov.w %d0,%d7 12506 mov.w (tbl_sdregb.b,%pc,%d1.w*2),%d1 12520 mov.b %d0,3+EXC_DREGS+0x0(%a6) 12523 mov.b %d0,3+EXC_DREGS+0x4(%a6) 12526 mov.b %d0,%d2 12529 mov.b %d0,%d3 12532 mov.b %d0,%d4 12535 mov.b %d0,%d5 12538 mov.b %d0,%d6 12541 mov.b %d0,%d7 12572 mov.w (tbl_iareg.b,%pc,%d1.w*2),%d1 12599 iareg7: mov.b &mia7_flg,SPCOND_FLG(%a6) 12636 mov.w (tbl_dareg.b,%pc,%d1.w*2),%d1 12663 dareg7: mov.b &mda7_flg,SPCOND_FLG(%a6) 12695 mov.w (tbl_load_fpn1.b,%pc,%d0.w*2), %d0 12709 mov.l 0+EXC_FP0(%a6), 0+FP_SRC(%a6) 12710 mov.l 4+EXC_FP0(%a6), 4+FP_SRC(%a6) 12711 mov.l 8+EXC_FP0(%a6), 8+FP_SRC(%a6) 12715 mov.l 0+EXC_FP1(%a6), 0+FP_SRC(%a6) 12716 mov.l 4+EXC_FP1(%a6), 4+FP_SRC(%a6) 12717 mov.l 8+EXC_FP1(%a6), 8+FP_SRC(%a6) 12768 mov.w (tbl_load_fpn2.b,%pc,%d0.w*2), %d0 12782 mov.l 0+EXC_FP0(%a6), 0+FP_DST(%a6) 12783 mov.l 4+EXC_FP0(%a6), 4+FP_DST(%a6) 12784 mov.l 8+EXC_FP0(%a6), 8+FP_DST(%a6) 12788 mov.l 0+EXC_FP1(%a6), 0+FP_DST(%a6) 12789 mov.l 4+EXC_FP1(%a6), 4+FP_DST(%a6) 12790 mov.l 8+EXC_FP1(%a6), 8+FP_DST(%a6) 12843 mov.w (tbl_store_fpreg.b,%pc,%d0.w*2), %d0 12920 mov.l &0xc,%d0 # packed is 12 bytes 12924 mov.l &0xc,%d0 # pass: 12 bytes 12939 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 13032 mov.l 0x0(%a0),FP_SCR0_EX(%a6) # make a copy of input 13033 mov.l 0x4(%a0),FP_SCR0_HI(%a6) # so we don't alter it 13034 mov.l 0x8(%a0),FP_SCR0_LO(%a6) 13062 mov.l &EDIGITS,%d2 # # of nibbles (digits) in fraction part 13063 mov.l &ESTRT,%d3 # counter to pick up digits 13064 mov.l (%a0),%d4 # get first word of bcd 13082 mov.l %d1,-(%sp) # save exp on stack 13105 mov.l &1,%d1 # word counter, init to 1 13120 mov.l (%a0,%d1.L*4),%d4 # load mantissa lonqword into d4 13121 mov.l &FSTRT,%d3 # counter to pick up digits 13122 mov.l &FNIBS,%d2 # reset number of digits per a0 ptr 13198 mov.l (%sp),%d1 # load expA for range test 13204 mov.l (%a0),%d4 # load lword 1 to d4 13208 mov.l &1,%d5 # init lword counter 13209 mov.l (%a0,%d5.L*4),%d4 # get lword 2 to d4 13213 mov.l (%a0,%d5.L*4),%d4 # get lword 3 to d4 13216 mov.l &7,%d2 # init digit counter 13224 mov.l %d1,%d0 # copy counter to d2 13225 mov.l (%sp),%d1 # get adjusted exp from memory 13229 mov.l (%a0),%d4 # load lword 1 to d4 13240 mov.l &3,%d2 # init d2 to count bits in counter 13256 mov.l &2,%d5 # set up d5 to point to lword 3 13257 mov.l (%a0,%d5.L*4),%d4 # get lword 3 13261 mov.l (%a0,%d5.L*4),%d4 # get lword 2 13263 mov.l &28,%d3 # point to last digit 13264 mov.l &7,%d2 # init digit counter 13272 mov.l %d1,%d0 # copy counter to d0 13273 mov.l (%sp),%d1 # get adjusted exp from memory 13277 mov.l (%a0),%d4 # load lword 1 to d4 13288 mov.l &3,%d2 # init d2 to count bits in counter 13343 mov.l USER_FPCR(%a6),%d3 # get user's FPCR 13345 mov.l (%a0),%d4 # reload 1st bcd word to d4 13350 mov.b (%a1,%d2),%d0 # load new rounding bits from table 13366 mov.l %d1,%d0 # copy exp to d0;use d0 13583 mov.l (%a0),L_SCR2(%a6) # save exponent for sign check 13584 mov.l %d0,%d7 # move k-factor to d7 13594 mov.w (%a0),%d0 13596 mov.l 4(%a0),%d1 13597 mov.l 8(%a0),%d2 13612 mov.w %d0,(%a0) 13613 mov.l %d1,4(%a0) 13614 mov.l %d2,8(%a0) 13619 mov.l (%a0),FP_SCR1(%a6) # move input to work space 13620 mov.l 4(%a0),FP_SCR1+4(%a6) # move input to work space 13621 mov.l 8(%a0),FP_SCR1+8(%a6) # move input to work space 13652 mov.l &-4933,%d6 # force ILOG = -4933 13655 mov.w FP_SCR1(%a6),%d0 # move exp to d0 13656 mov.w &0x3fff,FP_SCR1(%a6) # replace exponent with 0x3fff 13715 mov.l %d7,%d4 # if k > 0, LEN = k 13718 mov.l %d6,%d4 # first load ILOG to d4 13726 mov.l &17,%d4 # set max LEN = 17 13732 mov.l &1,%d4 # min LEN is 1 13789 mov.l %d7,%d6 # if ((k<0) & (ILOG < k)) ILOG = k 13791 mov.l %d6,%d0 # calc ILOG + 1 - LEN in d0 13803 mov.l &24,%d2 # put 24 in d2 for A9 13817 mov.b (%a2,%d1),%d3 # load d3 with new rmode 13907 mov.w (%sp),%d3 # grab exponent 13922 mov.l 0x8(%a0),-(%sp) # put input op mantissa on stk 13923 mov.l 0x4(%a0),-(%sp) 13924 mov.l &0x3fff0000,-(%sp) # force exp to zero 13930 mov.l 36+8(%a1),-(%sp) # get 10^8 mantissa 13931 mov.l 36+4(%a1),-(%sp) 13932 mov.l &0x3fff0000,-(%sp) # force exp to zero 13933 mov.l 48+8(%a1),-(%sp) # get 10^16 mantissa 13934 mov.l 48+4(%a1),-(%sp) 13935 mov.l &0x3fff0000,-(%sp)# force exp to zero 13988 mov.l USER_FPCR(%a6),L_SCR1(%a6) # save it for later 14019 mov.l L_SCR1(%a6),-(%sp) 14020 mov.l L_SCR2(%a6),-(%sp) 14028 mov.l USER_FPSR(%a6),-(%sp) 14033 ## mov.l USER_FPCR(%a6),%d0 # ext prec/keep rnd mode 14043 mov.b (%sp),USER_FPSR(%a6) 14046 mov.l (%sp)+,L_SCR2(%a6) 14047 mov.l (%sp)+,L_SCR1(%a6) 14050 mov.l L_SCR2(%a6),FP_SCR1(%a6) # restore original exponent 14051 mov.l L_SCR1(%a6),USER_FPCR(%a6) # restore user's FPCR 14092 mov.l %d4,%d0 # put LEN in d0 14119 mov.w &1,%d5 # set ICTR 14133 mov.w &1,%d5 # set ICTR 14144 mov.l %d4,%d0 # put LEN in d0 14198 mov.l 4(%a0),%d2 # move 2nd word of FP_RES to d2 14199 mov.l 8(%a0),%d3 # move 3rd word of FP_RES to d3 14202 mov.l (%a0),%d0 # move exponent to d0 14224 mov.l %d4,%d0 # put LEN in d0 for binstr call 14293 mov.l 4(%a2),%d2 # move word 2 to d2 14294 mov.l 8(%a2),%d3 # move word 3 to d3 14295 mov.w (%a2),%d0 # move exp to d0 14308 mov.l &4,%d0 # put 4 in d0 for binstr call 14311 mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0 14312 mov.l &12,%d1 # use d1 for shift count 14350 mov.l &2,%d0 # move 2 in to d0 for SM 14480 mov.l &1,%d7 # init d7 for second digit 14486 mov.l %d2,%d4 # copy the fraction before muls 14487 mov.l %d3,%d5 # to d4:d5 14521 mov.b %d7,(%a0)+ # store d7b byte in memory 14528 mov.w %d1,%d7 # put new digit in d7b 14534 mov.b %d7,(%a0)+ # store it in memory string 14579 mov.w &0x0121,EXC_VOFF(%a6) # set FSLW 14586 mov.w &0x0141,EXC_VOFF(%a6) # set FSLW 14593 mov.w &0x0101,EXC_VOFF(%a6) # set FSLW 14600 mov.w &0x0161,EXC_VOFF(%a6) # set FSLW 14607 mov.w &0x0161,EXC_VOFF(%a6) # set FSLW 14616 mov.w &0x00a1,EXC_VOFF(%a6) # set FSLW 14623 mov.w &0x00c1,EXC_VOFF(%a6) # set FSLW 14630 mov.w &0x0081,EXC_VOFF(%a6) # set FSLW 14637 mov.w &0x00e1,EXC_VOFF(%a6) # set FSLW 14641 mov.l &0xc,%d0 # twelve bytes 14644 mov.w &0x00e1,EXC_VOFF(%a6) # set FSLW 14649 mov.l USER_FPIAR(%a6),EXC_PC(%a6) # store current PC 14657 mov.l (%sp),-(%sp) # store SR, hi(PC) 14658 mov.l 0x8(%sp),0x4(%sp) # store lo(PC) 14659 mov.l 0xc(%sp),0x8(%sp) # store EA 14660 mov.l &0x00000001,0xc(%sp) # store FSLW 14661 mov.w 0x6(%sp),0xc(%sp) # fix FSLW (size) 14662 mov.w &0x4008,0x6(%sp) # store voff 14679 mov.b EXC_OPWORD+0x1(%a6),%d1 14688 mov.b EXC_OPWORD+0x1(%a6),%d1 14691 mov.w (tbl_rest_inc.b,%pc,%d1.w*2),%d1
|
H A D | fpsp.S | 98 mov.l %d0,-(%sp) 99 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0 101 mov.l 0x4(%sp),%d0 106 mov.l %d0,-(%sp) 107 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0 109 mov.l 0x4(%sp),%d0 114 mov.l %d0,-(%sp) 115 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0 117 mov.l 0x4(%sp),%d0 122 mov.l %d0,-(%sp) 123 mov.l (_060FPSP_TABLE-0x80+_off_inex,%pc),%d0 125 mov.l 0x4(%sp),%d0 130 mov.l %d0,-(%sp) 131 mov.l (_060FPSP_TABLE-0x80+_off_bsun,%pc),%d0 133 mov.l 0x4(%sp),%d0 138 mov.l %d0,-(%sp) 139 mov.l (_060FPSP_TABLE-0x80+_off_operr,%pc),%d0 141 mov.l 0x4(%sp),%d0 146 mov.l %d0,-(%sp) 147 mov.l (_060FPSP_TABLE-0x80+_off_snan,%pc),%d0 149 mov.l 0x4(%sp),%d0 154 mov.l %d0,-(%sp) 155 mov.l (_060FPSP_TABLE-0x80+_off_dz,%pc),%d0 157 mov.l 0x4(%sp),%d0 162 mov.l %d0,-(%sp) 163 mov.l (_060FPSP_TABLE-0x80+_off_fline,%pc),%d0 165 mov.l 0x4(%sp),%d0 170 mov.l %d0,-(%sp) 171 mov.l (_060FPSP_TABLE-0x80+_off_fpu_dis,%pc),%d0 173 mov.l 0x4(%sp),%d0 178 mov.l %d0,-(%sp) 179 mov.l (_060FPSP_TABLE-0x80+_off_trap,%pc),%d0 181 mov.l 0x4(%sp),%d0 186 mov.l %d0,-(%sp) 187 mov.l (_060FPSP_TABLE-0x80+_off_trace,%pc),%d0 189 mov.l 0x4(%sp),%d0 194 mov.l %d0,-(%sp) 195 mov.l (_060FPSP_TABLE-0x80+_off_access,%pc),%d0 197 mov.l 0x4(%sp),%d0 204 mov.l %d0,-(%sp) 205 mov.l (_060FPSP_TABLE-0x80+_off_imr,%pc),%d0 207 mov.l 0x4(%sp),%d0 212 mov.l %d0,-(%sp) 213 mov.l (_060FPSP_TABLE-0x80+_off_dmr,%pc),%d0 215 mov.l 0x4(%sp),%d0 220 mov.l %d0,-(%sp) 221 mov.l (_060FPSP_TABLE-0x80+_off_dmw,%pc),%d0 223 mov.l 0x4(%sp),%d0 228 mov.l %d0,-(%sp) 229 mov.l (_060FPSP_TABLE-0x80+_off_irw,%pc),%d0 231 mov.l 0x4(%sp),%d0 236 mov.l %d0,-(%sp) 237 mov.l (_060FPSP_TABLE-0x80+_off_irl,%pc),%d0 239 mov.l 0x4(%sp),%d0 244 mov.l %d0,-(%sp) 245 mov.l (_060FPSP_TABLE-0x80+_off_drb,%pc),%d0 247 mov.l 0x4(%sp),%d0 252 mov.l %d0,-(%sp) 253 mov.l (_060FPSP_TABLE-0x80+_off_drw,%pc),%d0 255 mov.l 0x4(%sp),%d0 260 mov.l %d0,-(%sp) 261 mov.l (_060FPSP_TABLE-0x80+_off_drl,%pc),%d0 263 mov.l 0x4(%sp),%d0 268 mov.l %d0,-(%sp) 269 mov.l (_060FPSP_TABLE-0x80+_off_dwb,%pc),%d0 271 mov.l 0x4(%sp),%d0 276 mov.l %d0,-(%sp) 277 mov.l (_060FPSP_TABLE-0x80+_off_dww,%pc),%d0 279 mov.l 0x4(%sp),%d0 284 mov.l %d0,-(%sp) 285 mov.l (_060FPSP_TABLE-0x80+_off_dwl,%pc),%d0 287 mov.l 0x4(%sp),%d0 650 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 651 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 654 mov.l %d0,EXC_OPWORD(%a6) 669 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 686 mov.b %d0,DTAG(%a6) # save dst optype tag 690 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 691 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 692 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 693 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) 694 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) 695 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) 698 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 700 mov.b 1+EXC_CMDREG(%a6),%d1 712 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 744 mov.w &0xe005,2+FP_SRC(%a6) # save exc status 762 mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 763 mov.w &0xe001,2+FP_SRC(%a6) # save exc status 779 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 780 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 781 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 784 mov.b &NORM,STAG(%a6) # set src optype tag 787 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 815 mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 890 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 891 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 894 mov.l %d0,EXC_OPWORD(%a6) 907 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 929 mov.b %d0,DTAG(%a6) # save dst optype tag 933 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 934 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 935 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 936 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) 937 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) 938 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) 941 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 943 mov.b 1+EXC_CMDREG(%a6),%d1 955 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 1006 mov.w &0xe003,2+FP_SRC(%a6) # save exc status 1036 mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 1037 mov.w &0xe001,2+FP_SRC(%a6) # save exc status 1053 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) 1054 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) 1055 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) 1058 mov.b &NORM,STAG(%a6) # set src optype tag 1061 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 1089 mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 1217 mov.l %usp,%a0 # fetch user stack pointer 1218 mov.l %a0,EXC_A7(%a6) # save on stack 1225 mov.l %a0,EXC_A7(%a6) # save on stack 1232 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 1233 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 1236 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 1276 mov.b %d0,STAG(%a6) # save src optype tag 1295 mov.b %d0,DTAG(%a6) # save dst optype tag 1299 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1306 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr 1323 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set 1328 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1399 mov.l %d0,-(%sp) # save d0 1401 mov.l (%sp)+,%d0 # restore d0 1403 mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status 1420 mov.w &0x4,%d0 1423 mov.w &0x03,%d0 1440 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1470 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1517 mov.w FP_SRC_EX(%a6),%d0 # get exponent 1524 mov.b %d0,STAG(%a6) 1528 mov.b &DENORM,STAG(%a6) 1532 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1536 mov.l (%a6),EXC_A6(%a6) # in case a6 changes 1551 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1556 mov.l EXC_A6(%a6),(%a6) # in case a6 changed 1566 mov.l EXC_A7(%a6),%a0 # restore a7 1567 mov.l %a0,%usp 1598 mov.l (%a6),%a6 # restore frame pointer 1600 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 1601 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 1604 mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) 1605 mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) 1606 mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) 1650 mov.w &0x2024,0x6(%sp) 1660 mov.w (tbl_fu_out.b,%pc,%d0.w*2),%d0 1681 mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd8 1682 mov.w &0xe006,2+FP_SRC(%a6) 1696 mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 1697 mov.w &0xe004,2+FP_SRC(%a6) 1713 mov.w &0x30d4,EXC_VOFF(%a6) # vector offset = 0xd4 1714 mov.w &0xe005,2+FP_SRC(%a6) 1727 mov.l EXC_A6(%a6),(%a6) # restore a6 1732 mov.l EXC_A7(%a6),%a0 # restore a7 whether we need 1733 mov.l %a0,%usp # to or not... 1742 mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc 1743 mov.w &0xe003,2+FP_SRC(%a6) 1766 mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc 1767 mov.w &0xe003,2+FP_DST(%a6) 1771 mov.l (%a6),%a6 # restore frame pointer 1773 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 1774 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 1775 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 1778 mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) 1779 mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) 1780 mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) 1794 mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 1795 mov.w &0xe001,2+FP_SRC(%a6) 1821 mov.b %d0,STAG(%a6) # save src optype tag 1840 mov.b %d0,DTAG(%a6) # save dst optype tag 1844 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1851 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr 1868 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1873 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1886 mov.l EXC_A7(%a6),%a0 # update user a7 1887 mov.l %a0,%usp 1915 mov.l 0x4(%sp),0x10(%sp) 1916 mov.l 0x0(%sp),0xc(%sp) 1983 mov.l EXC_A7(%a6),%a0 # update user a7 1984 mov.l %a0,%usp 1987 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2007 mov.w &0x3,%d0 2011 mov.w &0x4,%d0 2018 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2029 mov.l 0x4(%sp),0x10(%sp) 2030 mov.l 0x0(%sp),0xc(%sp) 2056 mov.w &0x2024,0x6(%sp) 2086 mov.b %d0,STAG(%a6) # save src optype tag 2089 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 2093 mov.l (%a6),EXC_A6(%a6) # in case a6 changes 2108 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2112 mov.l EXC_A6(%a6),(%a6) # restore a6 2117 mov.l EXC_A7(%a6),%a0 # update user a7 2118 mov.l %a0,%usp 2143 mov.l (%a6),%a6 # restore frame pointer 2145 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2146 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2149 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) 2150 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) 2151 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) 2165 mov.l EXC_A6(%a6),(%a6) # restore a6 2178 mov.l EXC_A7(%a6),%a0 2179 mov.l %a0,%usp 2193 mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd0 2194 mov.w &0xe006,2+FP_SRC(%a6) # set fsave status 2198 mov.l (%a6),%a6 # restore frame pointer 2200 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2201 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2202 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 2205 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) 2206 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) 2207 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) 2218 mov.l EXC_A7(%a6),%a0 2219 mov.l %a0,%usp 2233 mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 2234 mov.w &0xe004,2+FP_SRC(%a6) # set fsave status 2238 mov.l (%a6),%a6 # restore frame pointer 2240 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2241 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2242 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 2245 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) 2246 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) 2247 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) 2258 mov.l EXC_A7(%a6),%a0 2259 mov.l %a0,%usp 2273 mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 2274 mov.w &0xe001,2+FP_SRC(%a6) # set fsave status 2278 mov.l (%a6),%a6 # restore frame pointer 2280 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 2281 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) 2282 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 2285 mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) 2286 mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) 2287 mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) 2311 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2318 mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man) 2321 mov.l %d1,FP_SRC_HI(%a6) # insert new hi(man) 2328 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2336 mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign 2339 mov.w &0x3c01,%d1 # pass denorm threshold 2341 mov.w &0x3c00,%d0 # new exponent 2347 mov.w %d0,FP_SRC_EX(%a6) # insert new exponent 2356 mov.l 0x0(%a0),FP_DST_EX(%a6) 2357 mov.l 0x4(%a0),FP_DST_HI(%a6) 2358 mov.l 0x8(%a0),FP_DST_LO(%a6) 2458 mov.l %d0,-(%sp) # save d0 2462 mov.l (%sp)+,%d0 # restore d0 2471 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) 2473 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 2476 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2509 mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to #<data> 2511 mov.l &0xc,%d0 # pass: 12 bytes 2521 mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to #<data> 2523 mov.l &0xc,%d0 # pass: 12 bytes 2536 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 2554 mov.b %d0,STAG(%a6) # could be ANYTHING!!! 2558 mov.b %d0,STAG(%a6) # set new optype tag 2573 mov.b %d0,DTAG(%a6) # could be ANYTHING!!! 2577 mov.b %d0,DTAG(%a6) # set new optype tag 2592 mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec 2594 mov.b 1+EXC_CMDREG(%a6),%d1 2603 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 2620 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2634 mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" 2635 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame 2679 mov.w (tbl_iea_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2687 mov.w &0xe005,2+FP_SRC(%a6) 2691 mov.w &0xe003,2+FP_SRC(%a6) 2694 mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" 2695 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame 2728 mov.l (%sp),-(%sp) # shift stack frame "down" 2729 mov.w 0x8(%sp),0x4(%sp) 2730 mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 2746 mov.l %usp,%a0 2747 mov.l %a0,EXC_A7(%a6) # store current a7 2749 mov.l EXC_A7(%a6),%a0 # load possibly new a7 2750 mov.l %a0,%usp # update usp 2756 mov.l %a0,EXC_A7(%a6) 2772 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2773 mov.l EXC_EXTWPTR(%a6),(EXC_PC,%a6,%d0) 2774 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2777 mov.l %a0,EXC_SR(%a6) 2784 mov.l (%sp)+,%sp 2788 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2789 mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0) 2790 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2791 mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0) 2794 mov.l %a0,EXC_SR(%a6) 2801 mov.l (%sp)+,%sp 2806 mov.b %d1,EXC_VOFF(%a6) # store strg 2807 mov.b %d0,0x1+EXC_VOFF(%a6) # store size 2813 mov.l (%a6),-(%sp) # make a copy of a6 2814 mov.l %d0,-(%sp) # save d0 2815 mov.l %d1,-(%sp) # save d1 2816 mov.l EXC_EXTWPTR(%a6),-(%sp) # make a copy of Next PC 2819 mov.b 0x1+EXC_VOFF(%a6),%d0 # fetch size 2825 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2826 mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0) 2827 mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0) 2828 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2834 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2835 mov.l (%sp)+,(EXC_PC,%a6,%d0) 2836 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2842 mov.b EXC_VOFF(%a6),%d1 # fetch strg 2883 mov.l 0x4(%sp),%d1 2884 mov.l 0x8(%sp),%d0 2885 mov.l 0xc(%sp),%a6 2886 mov.l (%sp)+,%sp 2905 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set Next PC 2934 mov.l (%a6),%a6 # restore frame pointer 2935 mov.w EXC_SR+LOCAL_SIZE(%sp),0x0+LOCAL_SIZE(%sp) 2936 mov.l EXC_PC+LOCAL_SIZE(%sp),0x8+LOCAL_SIZE(%sp) 2937 mov.l EXC_EXTWPTR+LOCAL_SIZE(%sp),0x2+LOCAL_SIZE(%sp) 2938 mov.w &0x2024,0x6+LOCAL_SIZE(%sp) # stk fmt = 0x2; voff = 0x024 2951 mov.l (%sp)+,%d0 # restore d0 2958 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) 2959 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 2962 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2969 mov.l &0x10,%d0 # 16 bytes of instruction 2976 mov.l &0xc,%d0 2988 mov.l EXC_EXTWPTR(%a6),%d0 2991 mov.w %d0,EXC_VOFF(%a6) # store stack shift value 3001 mov.l %d0,-(%sp) # save d0 3002 mov.w 0xc(%sp),0x4(%sp) # move SR 3003 mov.l 0xe(%sp),0x6(%sp) # move Current PC 3005 mov.w 0x12(%sp),%d0 3006 mov.l 0x6(%sp),0x10(%sp) # move Current PC 3008 mov.w &0x402c,0xa(%sp) # insert offset,frame format 3009 mov.l (%sp)+,%d0 # restore d0 3027 mov.l 0x8(%sp),(%sp) # store SR,hi(PC) 3028 mov.w 0xc(%sp),0x4(%sp) # store lo(PC) 3029 mov.w &0x4008,0x6(%sp) # store voff 3030 mov.l 0x2(%sp),0x8(%sp) # store ea 3031 mov.l &0x09428001,0xc(%sp) # store fslw 3050 mov.l (%a6),%a6 3052 mov.l 0x4+LOCAL_SIZE(%sp),-0x8+0x4+LOCAL_SIZE(%sp) 3053 mov.w 0x8+LOCAL_SIZE(%sp),-0x8+0x8+LOCAL_SIZE(%sp) 3054 mov.w &0x4008,-0x8+0xa+LOCAL_SIZE(%sp) 3055 mov.l %a0,-0x8+0xc+LOCAL_SIZE(%sp) 3056 mov.w %d0,-0x8+0x10+LOCAL_SIZE(%sp) 3057 mov.w &0x0001,-0x8+0x12+LOCAL_SIZE(%sp) 3118 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3120 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3123 mov.l %d0,EXC_OPWORD(%a6) 3167 mov.w FP_SRC_EX(%a6),%d1 # fetch exponent 3174 mov.l FP_SRC_HI(%a6),%d1 3178 mov.l FP_SRC_HI(%a6),L_SCR1(%a6) 3182 mov.l &0x7fffffff,%d1 3187 mov.l %d1,L_SCR1(%a6) 3191 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg 3192 mov.w (tbl_operr.b,%pc,%d0.w*2),%a0 3206 mov.b L_SCR1(%a6),%d0 # load positive default result 3209 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3222 mov.w L_SCR1(%a6),%d0 # load positive default result 3225 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3238 mov.l L_SCR1(%a6),%d0 # load positive default result 3241 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3314 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3316 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3319 mov.l %d0,EXC_OPWORD(%a6) 3361 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg 3362 mov.w (tbl_snan.b,%pc,%d0.w*2),%a0 3376 mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN 3380 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3393 mov.w FP_SRC_HI(%a6),%d0 # load upper word of SNAN 3397 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3410 mov.l FP_SRC_HI(%a6),%d0 # load upper longword of SNAN 3414 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3429 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3432 mov.l FP_SRC_HI(%a6),%d1 # load mantissa 3435 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result 3443 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3446 mov.l %d1,-(%sp) 3447 mov.l FP_SRC_HI(%a6),%d1 # load mantissa 3450 mov.l (%sp)+,%d1 3456 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3459 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa 3460 mov.l %d0,FP_SCR0_EX(%a6) # store to temp space 3461 mov.l &11,%d0 # load shift amt 3464 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa 3467 mov.l %d1,FP_SCR0_HI(%a6) # store to temp space 3468 mov.l FP_SRC_LO(%a6),%d1 # load lo mantissa 3472 mov.l EXC_EA(%a6),%a1 # pass: dst addr 3487 mov.w FP_SRC_EX(%a6),FP_SCR0_EX(%a6) 3489 mov.l FP_SRC_HI(%a6),%d0 3491 mov.l %d0,FP_SCR0_HI(%a6) 3492 mov.l FP_SRC_LO(%a6),FP_SCR0_LO(%a6) 3497 mov.l %usp,%a0 # fetch user stack pointer 3498 mov.l %a0,EXC_A7(%a6) # save on stack for calc_ea() 3499 mov.l (%a6),EXC_A6(%a6) 3502 mov.l %a0,%a1 3503 mov.l %a0,EXC_EA(%a6) # stack correct <ea> 3505 mov.l EXC_A7(%a6),%a0 3506 mov.l %a0,%usp # restore user stack pointer 3507 mov.l EXC_A6(%a6),(%a6) 3520 mov.l (%a6),EXC_A6(%a6) 3523 mov.l %a0,%a1 3524 mov.l %a0,EXC_EA(%a6) # stack correct <ea> 3526 mov.l EXC_A6(%a6),(%a6) 3538 mov.l EXC_A6(%a6),%a6 # restore frame pointer 3540 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) 3541 mov.l LOCAL_SIZE+EXC_PC+0x2(%sp),LOCAL_SIZE+EXC_PC+0x2-0xc(%sp) 3542 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) 3544 mov.l LOCAL_SIZE+FP_SCR0_EX(%sp),LOCAL_SIZE+EXC_SR(%sp) 3545 mov.l LOCAL_SIZE+FP_SCR0_HI(%sp),LOCAL_SIZE+EXC_PC+0x2(%sp) 3546 mov.l LOCAL_SIZE+FP_SCR0_LO(%sp),LOCAL_SIZE+EXC_EA(%sp) 3606 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3608 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3611 mov.l %d0,EXC_OPWORD(%a6) 3629 mov.w &0xe001,0x2+FP_SRC(%a6) 3651 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 3671 mov.b %d0,DTAG(%a6) # save dst optype tag 3675 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 3677 mov.b 1+EXC_CMDREG(%a6),%d1 3683 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr 3703 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3704 mov.b 1+EXC_CMDREG(%a6),%d1 3725 mov.b &NORM,STAG(%a6) # src is a NORM 3728 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3780 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 3782 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3785 mov.l %d0,EXC_OPWORD(%a6) 3865 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) 3866 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 3895 mov.w 0x8(%sp),(%sp) 3896 mov.l 0xa(%sp),0x2(%sp) # move "Current PC" 3897 mov.w &0x402c,0x6(%sp) 3898 mov.l 0x2(%sp),0xc(%sp) 3911 mov.l (%sp),-(%sp) 3912 mov.l 0x8(%sp),0x4(%sp) 3913 mov.b &0x20,0x6(%sp) 4030 mov.l %usp,%a0 # fetch user stack pointer 4031 mov.l %a0,EXC_A7(%a6) # store in stack frame 4038 mov.l %a0,EXC_A7(%a6) # store a7' 4039 mov.l %a0,OLD_A7(%a6) # make a copy 4044 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) 4046 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4049 mov.l %d0,EXC_OPWORD(%a6) 4083 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode 4085 mov.b 1+EXC_CMDREG(%a6),%d1 4093 mov.w (tbl_trans.w,%pc,%d1.w*2),%d1 4097 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 4130 mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x24 4137 mov.l %a0,-(%sp) 4138 mov.l EXC_A7(%a6),%a0 4139 mov.l %a0,%usp 4140 mov.l (%sp)+,%a0 4148 mov.l %d0,-(%sp) # save d0 4149 mov.l EXC_A7(%a6),%d0 # load new a7' 4151 mov.l 0x2+EXC_PC(%a6),(0x2+EXC_PC,%a6,%d0) # shift stack frame 4152 mov.l EXC_SR(%a6),(EXC_SR,%a6,%d0) # shift stack frame 4153 mov.w %d0,EXC_SR(%a6) # store incr number 4154 mov.l (%sp)+,%d0 # restore d0 4166 mov.b FPCR_MODE(%a6),%d0 4167 mov.b 1+EXC_CMDREG(%a6),%d1 4219 mov.l %d0,-(%sp) # save d0 4221 mov.l (%sp)+,%d0 # restore d0 4222 mov.w (tbl_funimp_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) 4232 mov.w &0xe005,2+FP_SRC(%a6) 4238 mov.w &0xe003,2+FP_SRC(%a6) 4300 mov.l USER_FPIAR(%a6),EXC_EA(%a6) # Address = Current PC 4301 mov.w &0x201c,EXC_VOFF(%a6) # Vector Offset = 0x01c 4315 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 4347 mov.l EXC_A7(%a6),%a0 # yes; set new USP 4348 mov.l %a0,%usp 4372 mov.l 0x2(%sp),(%sp) # shift SR,hi(PC) "down" 4373 mov.l 0x6(%sp),0x4(%sp) # shift lo(PC),voff "down" 4378 mov.l 0x2(%sp),(%sp) # shift SR,hi(PC) "down" 4379 mov.w 0x6(%sp),0x4(%sp) # shift lo(PC) 4380 mov.w &0x2024,0x6(%sp) # fmt/voff = $2024 4404 mov.w &0x00c0,2+EXC_EA(%a6) # Fmt = 0x0; Vector Offset = 0x0c0 4405 mov.l USER_FPIAR(%a6),EXC_VOFF(%a6) # PC = Current PC 4406 mov.w EXC_SR(%a6),2+EXC_PC(%a6) # shift SR "up" 4408 mov.w &0xe000,2+FP_SRC(%a6) # bsun exception enabled 4459 mov.b &0x24,0x7(%sp) # vector offset = 0x024 4982 mov.l USER_FPIAR(%a6),EXC_PC(%a6) # store current PC 4986 mov.l (%sp),-(%sp) # store SR,hi(PC) 4987 mov.w 0x8(%sp),0x4(%sp) # store lo(PC) 4988 mov.w &0x4008,0x6(%sp) # store voff 4989 mov.l 0x2(%sp),0x8(%sp) # store EA 4990 mov.l &0x09428001,0xc(%sp) # store FSLW 5122 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0 5128 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1 5138 mov.l (%a0),%d1 # put exp in hi word 5139 mov.w 4(%a0),%d1 # fetch hi(man) 5161 mov.l INT(%a6),%d1 # make a copy of N 5174 mov.l INT(%a6),%d1 5266 mov.l %d1,POSNEG1(%a6) 5305 mov.l ADJN(%a6),%d1 5312 # mov.w &0x0000,XDCARE(%a6) # JUST IN CASE 5315 mov.b &FMOV_OP,%d1 # last inst is MOVE 5343 mov.l &4,ADJN(%a6) 5348 mov.l (%a0),%d1 5349 mov.w 4(%a0),%d1 5373 mov.l INT(%a6),%d1 5383 mov.l INT(%a6),%d1 5399 mov.l %d2,-(%sp) 5400 mov.l %d1,%d2 5411 mov.l (%sp)+,%d2 5415 mov.l &0x3F800000,POSNEG1(%a6) 5488 mov.l %d1,POSNEG1(%a6) 5544 # mov.w &0x0000,XDCARE(%a6) 5551 mov.b &FMOV_OP,%d1 # last inst is MOVE 5560 mov.l %d0,-(%sp) # save d0 5563 mov.l (%sp)+,%d0 # restore d0 5573 mov.l %d2,-(%sp) # save d2 5584 mov.w &0x7ffe,FP_SCR0_EX(%a6) 5585 mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) 5589 mov.w &0x7fdc,FP_SCR1_EX(%a6) 5590 mov.l &0x85a308d3,FP_SCR1_HI(%a6) 5610 mov.w INARG(%a6),%d1 5611 mov.l %d1,%a1 # save a copy of D0 5618 mov.b &0,ENDFLAG(%a6) 5622 mov.b &1,ENDFLAG(%a6) 5631 mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI 5634 mov.l &0xA2F9836E,FP_SCR0_HI(%a6) 5635 mov.l &0x4E44152A,FP_SCR0_LO(%a6) 5636 mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) 5646 mov.l %a1,%d2 5650 mov.l %d2,TWOTO63(%a6) 5656 mov.l %d1,%d2 # d2 = L 5659 mov.w %d2,FP_SCR0_EX(%a6) 5660 mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) 5664 mov.w %d1,FP_SCR1_EX(%a6) 5665 mov.l &0x85A308D3,FP_SCR1_HI(%a6) 5668 mov.b ENDFLAG(%a6),%d1 5703 mov.l (%sp)+,%d2 # restore d2 5706 mov.l ADJN(%a6),%d1 5868 mov.l (%a0),%d1 5869 mov.w 4(%a0),%d1 5990 mov.b &FMOV_OP,%d1 # last inst is MOVE 6004 mov.l %d2,-(%sp) # save d2 6015 mov.w &0x7ffe,FP_SCR0_EX(%a6) 6016 mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) 6020 mov.w &0x7fdc,FP_SCR1_EX(%a6) 6021 mov.l &0x85a308d3,FP_SCR1_HI(%a6) 6041 mov.w INARG(%a6),%d1 6042 mov.l %d1,%a1 # save a copy of D0 6049 mov.b &0,ENDFLAG(%a6) 6053 mov.b &1,ENDFLAG(%a6) 6062 mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI 6065 mov.l &0xA2F9836E,FP_SCR0_HI(%a6) 6066 mov.l &0x4E44152A,FP_SCR0_LO(%a6) 6067 mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) 6077 mov.l %a1,%d2 6081 mov.l %d2,TWOTO63(%a6) 6087 mov.l %d1,%d2 # d2 = L 6090 mov.w %d2,FP_SCR0_EX(%a6) 6091 mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) 6095 mov.w %d1,FP_SCR1_EX(%a6) 6096 mov.l &0x85A308D3,FP_SCR1_HI(%a6) 6099 mov.b ENDFLAG(%a6),%d1 6134 mov.l (%sp)+,%d2 # restore d2 6137 mov.l INT(%a6),%d1 6350 mov.l (%a0),%d1 6351 mov.w 4(%a0),%d1 6389 mov.l &0x00000000,XFRACLO(%a6) # LOCATION OF X IS NOW F 6401 mov.l %d2,-(%sp) # SAVE d2 TEMPORARILY 6402 mov.l %d1,%d2 # THE EXP AND 16 BITS OF X 6411 mov.l (%a1)+,ATANF(%a6) 6412 mov.l (%a1)+,ATANFHI(%a6) 6413 mov.l (%a1)+,ATANFLO(%a6) # ATANF IS NOW ATAN(|F|) 6414 mov.l X(%a6),%d1 # LOAD SIGN AND EXPO. AGAIN 6417 mov.l (%sp)+,%d2 # RESTORE d2 6505 mov.b &FMOV_OP,%d1 # last inst is MOVE 6632 mov.l (%a0),%d1 6633 mov.w 4(%a0),%d1 6673 mov.l (%a0),%d1 6676 mov.l %d1,-(%sp) # push SIGN(X) IN SGL-FMT 6684 mov.b &FMOV_OP,%d1 # last inst is MOVE 6733 mov.l (%a0),%d1 # pack exp w/ upper 16 fraction 6734 mov.w 4(%a0),%d1 6749 mov.l %d0,-(%sp) # save original users fpcr 7211 mov.l (%a0),%d1 # load part of input X 7219 mov.w 4(%a0),%d1 # expo. and partial sig. of |X| 7232 mov.l &0,ADJFLAG(%a6) 7237 mov.l %d1,L_SCR1(%a6) # save N temporarily 7241 mov.l L_SCR1(%a6),%d1 7244 mov.w L2(%pc),L_SCR1(%a6) # prefetch L2, no need in CB 7275 mov.w %d1,SCALE(%a6) # SCALE is 2^(M) in extended 7276 mov.l &0x80000000,SCALE+4(%a6) 7299 mov.l ADJFLAG(%a6),%d1 7308 mov.b &FMUL_OP,%d1 # last inst is MUL 7329 mov.l &1,ADJFLAG(%a6) 7333 mov.l %d1,L_SCR1(%a6) # save N temporarily 7337 mov.l L_SCR1(%a6),%d1 7339 mov.l %d1,L_SCR1(%a6) # save K temporarily 7343 mov.w %d1,ADJSCALE(%a6) # ADJSCALE := 2^(M1) 7344 mov.l &0x80000000,ADJSCALE+4(%a6) 7346 mov.l L_SCR1(%a6),%d1 # D0 is M 7359 mov.l (%a0),-(%sp) 7375 mov.l (%a0),%d1 # load part of input X 7384 mov.w 4(%a0),%d1 # expo. and partial sig. of |X| 7401 mov.l %d1,L_SCR1(%a6) # save N temporarily 7405 mov.l L_SCR1(%a6),%d1 7407 mov.l %d1,L_SCR1(%a6) # save a copy of M 7436 mov.w %d1,SC(%a6) # SC is 2^(M) in extended 7437 mov.l &0x80000000,SC+4(%a6) 7441 mov.l L_SCR1(%a6),%d1 # D0 is M 7450 mov.w %d1,ONEBYSC(%a6) # OnebySc is -2^(-M) 7451 mov.l &0x80000000,ONEBYSC+4(%a6) 7469 mov.l L_SCR1(%a6),%d1 # retrieve M 7511 mov.l &0x80010000,SC(%a6) # SC is -2^(-16382) 7512 mov.l &0x80000000,SC+4(%a6) 7516 mov.b &FADD_OP,%d1 # last inst is ADD 7524 mov.l &0x80010000,SC(%a6) 7525 mov.l &0x80000000,SC+4(%a6) 7529 mov.b &FMUL_OP,%d1 # last inst is MUL 7586 mov.l (%a0),%d1 7623 mov.w SRC_EX(%a0),%d0 # get the exponent 7631 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 7640 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 7645 mov.w SRC_EX(%a0),%d0 # get the exp 7650 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy to tmp loc 7651 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy to tmp loc 7652 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 7658 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 7723 mov.l (%a0),%d1 7724 mov.w 4(%a0),%d1 7734 mov.l %d0,-(%sp) 7741 mov.l (%sp)+,%d0 7747 mov.b &FADD_OP,%d1 # last inst is ADD 7759 mov.l %d0,-(%sp) 7765 mov.l (%sp)+,%d0 7768 mov.b &FMUL_OP,%d1 # last inst is MUL 7835 mov.l (%a0),%d1 7836 mov.w 4(%a0),%d1 7837 mov.l %d1,%a1 # save (compacted) operand 7860 mov.l %a1,%d1 7864 mov.l %d1,-(%sp) 7867 mov.b &FMUL_OP,%d1 # last inst is MUL 7876 mov.l &0,-(%sp) 7877 mov.l &0x80000000,-(%sp) 7878 mov.l %a1,%d1 7881 mov.l %d1,-(%sp) # EXTENDED FMT 7884 mov.l %d0,-(%sp) 7891 mov.l (%sp)+,%d0 7893 mov.b &FMUL_OP,%d1 # last inst is MUL 7961 mov.l (%a0),%d1 7962 mov.w 4(%a0),%d1 7963 mov.l %d1,X(%a6) 7973 mov.l X(%a6),%d1 7974 mov.l %d1,SGN(%a6) 7977 mov.l %d1,X(%a6) 7981 mov.l %d0,-(%sp) 7987 mov.l (%sp)+,%d0 7991 mov.l SGN(%a6),%d1 8010 mov.l X(%a6),%d1 8011 mov.l %d1,SGN(%a6) 8014 mov.l %d1,X(%a6) # Y = 2|X| 8016 mov.l SGN(%a6),%d1 8019 mov.l %d0,-(%sp) 8025 mov.l (%sp)+,%d0 8026 mov.l SGN(%a6),%d1 8033 mov.l SGN(%a6),%d1 8038 mov.b &FADD_OP,%d1 # last inst is ADD 8044 mov.b &FMOV_OP,%d1 # last inst is MOVE 8050 mov.l X(%a6),%d1 8321 mov.l &0x00000000,ADJK(%a6) 8327 mov.l (%a0),%d1 8328 mov.w 4(%a0),%d1 8330 mov.l (%a0),X(%a6) 8331 mov.l 4(%a0),X+4(%a6) 8332 mov.l 8(%a0),X+8(%a6) 8363 mov.l &0x3FFF0000,X(%a6) # X IS NOW Y, I.E. 2^(-K)*X 8364 mov.l XFRAC(%a6),FFRAC(%a6) 8367 mov.l FFRAC(%a6),%d1 # READY TO GET ADDRESS OF 1/F 8375 mov.l &0x3fff0000,F(%a6) 8488 mov.l &-100,ADJK(%a6) # INPUT = 2^(ADJK) * FP0 8496 mov.l (%a0),%d3 # D3 is exponent of smallest norm. # 8497 mov.l 4(%a0),%d4 8498 mov.l 8(%a0),%d5 # (D4,D5) is (Hi_X,Lo_X) 8505 mov.l %d5,%d4 8507 mov.l &32,%d2 8513 mov.l %d3,X(%a6) 8514 mov.l %d4,XFRAC(%a6) 8515 mov.l %d5,XFRAC+4(%a6) 8517 mov.l %d2,ADJK(%a6) 8526 mov.l %d6,%d2 # get k 8528 mov.l %d5,%d7 # a copy of D5 8535 mov.l %d3,X(%a6) 8536 mov.l %d4,XFRAC(%a6) 8537 mov.l %d5,XFRAC+4(%a6) 8539 mov.l %d2,ADJK(%a6) 8553 mov.b &FMOV_OP,%d1 # last inst is MOVE 8559 mov.l &0x00000000,ADJK(%a6) 8563 mov.w XFRAC(%a6),XDCARE(%a6) 8564 mov.l X(%a6),%d1 8600 mov.l XFRAC(%a6),FFRAC(%a6) 8608 mov.l &0x3fff0000,F(%a6) 8611 mov.l FFRAC(%a6),%d1 8626 mov.l &0x3fff0000,F(%a6) 8629 mov.l FFRAC(%a6),%d1 8707 mov.l (%a0),%d1 8708 mov.w 4(%a0),%d1 8722 mov.l (%a0),%d1 8725 mov.l %d1,-(%sp) 8727 mov.l %d0,-(%sp) # save rnd prec,mode 8734 mov.l (%sp)+,%d0 # fetch old prec,mode 8736 mov.b &FMUL_OP,%d1 # last inst is MUL 8849 mov.l (%a0),%d1 8851 mov.l %d0,-(%sp) 8861 mov.l (%a0),%d1 8863 mov.l %d0,-(%sp) 8873 mov.l (%a0),%d1 8876 mov.l 8(%a0),%d1 8879 mov.l 4(%a0),%d1 8884 mov.w (%a0),%d1 8893 mov.l %d0,-(%sp) 8906 mov.l (%a0),%d1 8908 mov.l %d0,-(%sp) 9094 mov.l (%a0),%d1 9095 mov.w 4(%a0),%d1 9114 mov.l %d2,-(%sp) 9117 mov.l INT(%a6),%d1 9118 mov.l %d1,%d2 9123 mov.l %d2,%d1 9136 mov.l (%a1)+,FACT1(%a6) 9137 mov.l (%a1)+,FACT1HI(%a6) 9138 mov.l (%a1)+,FACT1LOW(%a6) 9139 mov.w (%a1)+,FACT2(%a6) 9143 mov.w (%a1)+,FACT2HI(%a6) 9166 mov.l X(%a6),%d1 9181 mov.l (%a0),%d1 9191 mov.l (%a0),%d1 9192 mov.w 4(%a0),%d1 9211 mov.l %d2,-(%sp) 9214 mov.l INT(%a6),%d1 9215 mov.l %d1,%d2 9220 mov.l %d2,%d1 9234 mov.l (%a1)+,FACT1(%a6) 9238 mov.l (%a1)+,FACT1HI(%a6) 9239 mov.l (%a1)+,FACT1LOW(%a6) 9241 mov.w (%a1)+,FACT2(%a6) 9245 mov.w (%a1)+,FACT2HI(%a6) 9291 mov.w %d2,ADJFACT(%a6) # INSERT EXPONENT 9292 mov.l (%sp)+,%d2 9293 mov.l &0x80000000,ADJFACT+4(%a6) 9295 mov.b &FMUL_OP,%d1 # last inst is MUL 9305 mov.l (%a0),%d1 9325 mov.l %d1,-(%sp) # save rom offset for a sec 9328 mov.l %d0,%d1 # make a copy 9332 mov.w %d1,%d0 # put rnd mode in lo 9334 mov.l (%sp)+,%d1 # get rom offset 9470 mov.w 0x0(%a0,%d1.w),FP_SCR1_EX(%a6) # load first word 9471 mov.l 0x4(%a0,%d1.w),FP_SCR1_HI(%a6) # load second word 9472 mov.l 0x8(%a0,%d1.w),FP_SCR1_LO(%a6) # load third word 9473 mov.l %d0,%d1 9581 mov.l %d0,-(%sp) # store off ctrl bits for now 9583 mov.w DST_EX(%a1),%d1 # get dst exponent 9587 mov.w SRC_EX(%a0),%d0 # check src bounds 9610 mov.l %d0,-(%sp) # save src for now 9612 mov.w DST_EX(%a1),FP_SCR0_EX(%a6) # make a copy 9613 mov.l DST_HI(%a1),FP_SCR0_HI(%a6) 9614 mov.l DST_LO(%a1),FP_SCR0_LO(%a6) 9633 mov.l &0x80000000,%d1 # load normalized mantissa 9640 mov.l %d1,-(%sp) # insert new high mantissa 9646 mov.l %d1,-(%sp) # insert new low mantissa 9661 mov.l &0x80000000,-(%sp) # insert new high mantissa 9662 mov.l %d0,-(%sp) # insert new lo mantissa 9666 mov.b &FMUL_OP,%d1 # last inst is MUL 9675 mov.l (%sp)+,%d0 # restore ctrl bits 9689 mov.l (%sp)+,%d0 9691 mov.b &FMOV_OP,%d1 # last inst is MOVE 9695 mov.l (%sp)+,%d0 # load control bits into d1 9696 mov.l %a1,%a0 # pass ptr to dst 9780 mov.l %d0,-(%sp) # save ctrl bits 9787 mov.l %d0,-(%sp) # save ctrl bits 9788 mov.b &0x1,Mod_Flag(%a6) 9793 mov.w SRC_EX(%a0),%d3 9794 mov.w %d3,SignY(%a6) 9798 mov.l SRC_HI(%a0),%d4 9799 mov.l SRC_LO(%a0),%d5 # (D3,D4,D5) is |Y| 9804 mov.l &0x00003FFE,%d3 # $3FFD + 1 9809 mov.l %d5,%d4 9824 mov.l %d5,%d7 # a copy of D5 9838 mov.w DST_EX(%a1),%d0 9839 mov.w %d0,SignX(%a6) 9840 mov.w SignY(%a6),%d1 9843 mov.w %d1,SignQ(%a6) # sign(Q) obtained 9845 mov.l DST_HI(%a1),%d1 9846 mov.l DST_LO(%a1),%d2 # (D0,D1,D2) is |X| 9849 mov.l &0x00003FFE,%d0 9854 mov.l %d2,%d1 9869 mov.l %d2,%d7 # a copy of D2 9884 mov.l %d3,L_SCR1(%a6) # save biased exp(Y) 9885 mov.l %d0,-(%sp) # save biased exp(X) 9890 mov.l &0,%a1 # A1 is k; j+k=L, Q=0 9898 mov.l (%sp)+,%d0 # restore d0 9948 mov.l L_SCR1(%a6),%d0 # new biased expo of R 9953 mov.l %d2,%d1 9969 mov.l %d2,%d7 # a copy of D2 9981 mov.w %d0,R(%a6) 9982 mov.l %d1,R_Hi(%a6) 9983 mov.l %d2,R_Lo(%a6) 9984 mov.l L_SCR1(%a6),%d6 9985 mov.w %d6,Y(%a6) 9986 mov.l %d4,Y_Hi(%a6) 9987 mov.l %d5,Y_Lo(%a6) 9989 mov.b &1,Sc_Flag(%a6) 9992 mov.l %d1,R_Hi(%a6) 9993 mov.l %d2,R_Lo(%a6) 9995 mov.w %d0,R(%a6) 9996 mov.l L_SCR1(%a6),%d6 9998 mov.l %d6,L_SCR1(%a6) 10000 mov.w %d6,Y(%a6) 10001 mov.l %d4,Y_Hi(%a6) 10002 mov.l %d5,Y_Lo(%a6) 10010 mov.l L_SCR1(%a6),%d6 # new biased expo(Y) 10033 mov.w SignX(%a6),%d6 10041 mov.w SignQ(%a6),%d6 # D6 is sign(Q) 10042 mov.l &8,%d7 10051 mov.b %d3,FPSR_QBYTE(%a6) # put Q in fpsr 10056 mov.l (%sp)+,%d0 10060 mov.b &FMUL_OP,%d1 # last inst is MUL 10071 mov.b &FMOV_OP,%d1 # last inst is MOVE 10094 mov.l %d3,%d6 10101 mov.w SignX(%a6),%d6 10103 mov.w %d6,SignX(%a6) 10178 mov.l %a0,%a1 # make copy of src ptr 10179 mov.l %d0,%d1 # make copy of rnd prec,mode 10192 mov.l %a1,-(%sp) 10196 mov.l (%sp)+,%a1 10200 mov.b FPCR_ENABLE(%a6),%d0 10212 mov.w LOCAL_EX(%a1),FP_SCR0_EX(%a6) 10213 mov.l LOCAL_HI(%a1),FP_SCR0_HI(%a6) 10214 mov.l LOCAL_LO(%a1),FP_SCR0_LO(%a6) 10278 mov.b %d0,%d1 # fetch rnd mode/prec 10288 mov.w LOCAL_EX(%a0),FP_SCR0_EX(%a6) 10289 mov.l LOCAL_HI(%a0),FP_SCR0_HI(%a6) 10290 mov.l LOCAL_LO(%a0),FP_SCR0_LO(%a6) 10306 mov.l LOCAL_LO(%a0),%d1 # are any of lo 11 bits of 10321 mov.b %d0,FPSR_CC(%a6) # insert new ccodes 10334 mov.b %d0,FPSR_CC(%a6) # insert new ccodes 10377 mov.b &z_bmask,FPSR_CC(%a6) 10424 mov.l %d0,%d1 # make a copy 10427 mov.b (tbl_unf_cc.b,%pc,%d0.w*1),FPSR_CC(%a6) # insert ccode bits 10492 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 10499 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bits 10525 mov.b &inf_bmask,FPSR_CC(%a6) # set 'INF' ccode bit 10534 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits 10602 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 10649 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) 10653 mov.b &z_bmask,FPSR_CC(%a6) 10700 mov.b 1+EXC_CMDREG(%a6),%d0 10702 mov.w (tbl_sto_cos.b,%pc,%d0.w*2),%d0 10745 mov.b DTAG(%a6),%d1 10759 mov.b DTAG(%a6),%d1 10773 mov.b DTAG(%a6),%d1 10787 mov.b SRC_EX(%a0),%d1 # get src sign 10788 mov.b DST_EX(%a1),%d0 # get dst sign 10791 mov.b %d1,FPSR_QBYTE(%a6) 10799 mov.l %d0,-(%sp) 10800 mov.b SRC_EX(%a0),%d1 # get src sign 10801 mov.b DST_EX(%a1),%d0 # get dst sign 10804 mov.b %d1,FPSR_QBYTE(%a6) 10808 mov.l (%sp)+,%d0 10818 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode 10826 mov.b DTAG(%a6),%d1 10840 mov.b DTAG(%a6),%d1 10854 mov.b DTAG(%a6),%d1 10871 mov.b DTAG(%a6),%d1 10885 mov.b DTAG(%a6),%d1 10899 mov.b DTAG(%a6),%d1 10914 mov.b DTAG(%a6),%d1 10926 mov.b DTAG(%a6),%d1 10956 mov.b &nan_bmask,FPSR_CC(%a6) 10959 mov.b &neg_bmask+nan_bmask,FPSR_CC(%a6) 10981 mov.b &nan_bmask,FPSR_CC(%a6) 10984 mov.b &neg_bmask+nan_bmask,FPSR_CC(%a6) 10998 mov.b STAG(%a6),%d1 11012 mov.b STAG(%a6),%d1 11026 mov.b STAG(%a6),%d1 11040 mov.b STAG(%a6),%d1 11054 mov.b STAG(%a6),%d1 11068 mov.b STAG(%a6),%d1 11082 mov.b STAG(%a6),%d1 11096 mov.b STAG(%a6),%d1 11110 mov.b STAG(%a6),%d1 11124 mov.b STAG(%a6),%d1 11138 mov.b STAG(%a6),%d1 11152 mov.b STAG(%a6),%d1 11166 mov.b STAG(%a6),%d1 11180 mov.b STAG(%a6),%d1 11194 mov.b STAG(%a6),%d1 11208 mov.b STAG(%a6),%d1 11222 mov.b STAG(%a6),%d1 11236 mov.b STAG(%a6),%d1 11250 mov.b STAG(%a6),%d1 11264 mov.b STAG(%a6),%d1 11278 mov.b STAG(%a6),%d1 11292 mov.b STAG(%a6),%d1 11306 mov.b STAG(%a6),%d1 11320 mov.b STAG(%a6),%d1 11365 mov.b &NORM,STAG(%a6) 11368 mov.b &NORM,DTAG(%a6) 11398 mov.b &DENORM,STAG(%a6) 11579 mov.l %d0,L_SCR3(%a6) # store rnd info 11582 mov.b DTAG(%a6),%d1 11588 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 11589 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 11590 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 11592 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 11593 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 11594 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 11597 mov.l %d0,-(%sp) # save scale factor 1 11603 mov.w 2+L_SCR3(%a6),%d1 # fetch precision 11605 mov.l (%sp)+,%d0 # load S.F. 11637 mov.l %d2,-(%sp) # save d2 11638 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 11639 mov.l %d1,%d2 # make a copy 11644 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 11645 mov.l (%sp)+,%d2 # restore d2 11679 mov.b FPCR_ENABLE(%a6),%d1 11687 mov.l L_SCR3(%a6),%d0 # pass rnd prec,mode 11700 mov.l L_SCR3(%a6),%d1 11707 mov.l %d2,-(%sp) # save d2 11708 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 11709 mov.w %d1,%d2 # make a copy 11716 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 11717 mov.l (%sp)+,%d2 # restore d2 11724 mov.l L_SCR3(%a6),%d1 11791 mov.b FPCR_ENABLE(%a6),%d1 11799 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 11811 mov.l L_SCR3(%a6),%d1 11827 mov.l %d2,-(%sp) # save d2 11828 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 11829 mov.l %d1,%d2 # make a copy 11836 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 11837 mov.l (%sp)+,%d2 # restore d2 11842 mov.l L_SCR3(%a6),%d1 11878 mov.l L_SCR3(%a6),%d1 11899 mov.w (tbl_fmul_op.b,%pc,%d1.w*2),%d1 11970 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11971 mov.b DST_EX(%a1),%d1 11976 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/N 11980 mov.b &z_bmask,FPSR_CC(%a6) # set Z 11994 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11995 mov.b DST_EX(%a1),%d1 12001 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/N 12005 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 12011 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 12012 mov.b DST_EX(%a1),%d1 12064 mov.l %d0,L_SCR3(%a6) # store rnd info 12066 mov.b STAG(%a6),%d1 # fetch src optype tag 12112 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12113 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12114 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12119 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp 12123 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 12138 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12139 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12140 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12164 mov.l %d2,-(%sp) # save d2 12166 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 12167 mov.w %d1,%d2 # make a copy 12172 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 12173 mov.l (%sp)+,%d2 # restore d2 12181 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12182 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12183 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12205 mov.b FPCR_ENABLE(%a6),%d1 12211 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 12222 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 12223 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 12224 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 12226 mov.l %d2,-(%sp) # save d2 12227 mov.w %d1,%d2 # make a copy 12234 mov.w %d2,FP_SCR1_EX(%a6) # insert new exponent 12236 mov.l (%sp)+,%d2 # restore d2 12256 mov.b FPCR_ENABLE(%a6),%d1 12267 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 12279 mov.l %d2,-(%sp) # save d2 12280 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 12281 mov.l %d1,%d2 # make a copy 12288 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 12289 mov.l (%sp)+,%d2 # restore d2 12335 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 12397 mov.l %d0,L_SCR3(%a6) # store rnd info 12400 mov.b DTAG(%a6),%d1 12410 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 12411 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 12412 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 12414 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12415 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12416 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12419 mov.l %d0,-(%sp) # save scale factor 1 12426 mov.w 2+L_SCR3(%a6),%d1 # fetch precision 12428 mov.l (%sp)+,%d0 # load S.F. 12451 mov.l %d2,-(%sp) # store d2 12452 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 12453 mov.l %d1,%d2 # make a copy 12458 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 12459 mov.l (%sp)+,%d2 # restore d2 12469 mov.l (%sp)+,%d0 # restore scale factor 12473 mov.l %d0,-(%sp) # save scale factor 12488 mov.w (%sp),%d0 # fetch new exponent 12494 mov.l (%sp)+,%d0 12499 mov.b FPCR_ENABLE(%a6),%d1 12506 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 12513 mov.l L_SCR3(%a6),%d1 12520 mov.l %d2,-(%sp) # save d2 12521 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 12522 mov.w %d1,%d2 # make a copy 12529 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 12530 mov.l (%sp)+,%d2 # restore d2 12537 mov.l L_SCR3(%a6),%d1 12561 mov.b FPCR_ENABLE(%a6),%d1 12569 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 12581 mov.l L_SCR3(%a6),%d1 12595 mov.l %d2,-(%sp) # save d2 12596 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 12597 mov.l %d1,%d2 # make a copy 12604 mov.w %d1,FP_SCR0_EX(%a6) # insert new exp 12605 mov.l (%sp)+,%d2 # restore d2 12610 mov.l L_SCR3(%a6),%d1 12646 mov.l L_SCR3(%a6),%d1 12667 mov.w (tbl_fdiv_op.b,%pc,%d1.w*2),%d1 12735 mov.b SRC_EX(%a0),%d0 # result sign is exclusive 12736 mov.b DST_EX(%a1),%d1 # or of input signs. 12740 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/N 12744 mov.b &z_bmask,FPSR_CC(%a6) # set Z 12755 mov.b SRC_EX(%a0),%d0 # load both signs 12756 mov.b DST_EX(%a1),%d1 12760 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/N 12764 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 12775 mov.b DST_EX(%a1),%d0 # load both signs 12776 mov.b SRC_EX(%a0),%d1 12783 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/NEG 12789 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 12838 mov.l %d0,L_SCR3(%a6) # store rnd info 12839 mov.b STAG(%a6),%d1 12854 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12855 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12856 mov.w SRC_EX(%a0),%d0 12859 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 12861 mov.w %d0,FP_SCR0_EX(%a6) 12875 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12876 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12877 mov.w SRC_EX(%a0),%d0 12880 mov.b &neg_bmask,FPSR_CC(%a6) # yes, set 'N' ccode bit 12882 mov.w %d0,FP_SCR0_EX(%a6) 12899 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp 12903 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 12918 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12919 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12920 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12944 mov.l %d2,-(%sp) # save d2 12946 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp 12947 mov.w %d1,%d2 # make a copy 12952 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 12953 mov.l (%sp)+,%d2 # restore d2 12961 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 12962 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 12963 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 12985 mov.b FPCR_ENABLE(%a6),%d1 12991 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 13002 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 13003 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 13004 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 13006 mov.l %d2,-(%sp) # save d2 13007 mov.l %d1,%d2 # make a copy 13014 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp 13016 mov.l (%sp)+,%d2 # restore d2 13036 mov.b FPCR_ENABLE(%a6),%d1 13047 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 13059 mov.l %d2,-(%sp) # save d2 13060 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 13061 mov.l %d1,%d2 # make a copy 13068 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 13070 mov.l (%sp)+,%d2 # restore d2 13115 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 13139 mov.b STAG(%a6),%d1 13150 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 13174 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 13184 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 13187 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'I','N' ccode bits 13197 mov.b &z_bmask,FPSR_CC(%a6) # set 'N' ccode bit 13200 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 13231 mov.b STAG(%a6),%d1 13275 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) # copy sign, zero exp 13276 mov.b &0x80,FP_SCR0_HI(%a6) # force DENORM ==> small NORM 13288 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 13292 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 13303 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 13306 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits 13337 mov.b STAG(%a6),%d1 13377 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) # copy sign, zero exp 13378 mov.b &0x80,FP_SCR0_HI(%a6) # force DENORM ==> small NORM 13390 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 13394 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 13405 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 13408 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits 13461 mov.l %d0,L_SCR3(%a6) # store rnd info 13462 mov.b STAG(%a6),%d1 13477 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 13478 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 13479 mov.w SRC_EX(%a0),%d1 13481 mov.w %d1,FP_SCR0_EX(%a6) # insert exponent 13495 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 13496 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 13497 mov.w SRC_EX(%a0),%d0 13499 mov.w %d0,FP_SCR0_EX(%a6) # insert exponent 13517 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp 13521 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 13536 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 13537 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 13538 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 13562 mov.l %d2,-(%sp) # save d2 13564 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp 13565 mov.l %d1,%d2 # make a copy 13570 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 13571 mov.l (%sp)+,%d2 # restore d2 13579 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 13580 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 13581 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 13600 mov.b FPCR_ENABLE(%a6),%d1 13606 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 13617 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 13618 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 13619 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 13621 mov.l %d2,-(%sp) # save d2 13622 mov.l %d1,%d2 # make a copy 13629 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp 13631 mov.l (%sp)+,%d2 # restore d2 13651 mov.b FPCR_ENABLE(%a6),%d1 13662 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 13674 mov.l %d2,-(%sp) # save d2 13675 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 13676 mov.l %d1,%d2 # make a copy 13683 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 13685 mov.l (%sp)+,%d2 # restore d2 13727 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 13730 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 13759 mov.b DTAG(%a6),%d1 13774 mov.b %d0,FPSR_CC(%a6) # set ccode bits(no exc bits are set) 13782 mov.w (tbl_fcmp_op.b,%pc,%d1.w*2),%d1 13865 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 13866 mov.l SRC_HI(%a0),%d0 13868 mov.l %d0,FP_SCR0_HI(%a6) 13869 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 13874 mov.l DST_EX(%a1),FP_SCR0_EX(%a6) 13875 mov.l DST_HI(%a1),%d0 13877 mov.l %d0,FP_SCR0_HI(%a6) 13878 mov.l DST_LO(%a1),FP_SCR0_LO(%a6) 13883 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 13884 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 13885 mov.l DST_HI(%a1),%d0 13887 mov.l %d0,FP_SCR1_HI(%a6) 13888 mov.l SRC_HI(%a0),%d0 13890 mov.l %d0,FP_SCR0_HI(%a6) 13891 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 13892 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 13898 mov.b SRC_EX(%a0),%d0 # determine if like signs 13899 mov.b DST_EX(%a1),%d1 13908 mov.b &neg_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 13912 mov.b SRC_EX(%a0),%d0 # determine if like signs 13913 mov.b DST_EX(%a1),%d1 13922 mov.b &neg_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 13960 mov.l %d0,L_SCR3(%a6) # store rnd info 13963 mov.b DTAG(%a6),%d1 13970 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 13971 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 13972 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 13974 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 13975 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 13976 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 13979 mov.l %d0,-(%sp) # save scale factor 1 14008 mov.l %d2,-(%sp) # save d2 14009 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 14010 mov.l %d1,%d2 # make a copy 14015 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 14016 mov.l (%sp)+,%d2 # restore d2 14038 mov.b FPCR_ENABLE(%a6),%d1 14045 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 14055 mov.l %d2,-(%sp) # save d2 14056 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 14057 mov.l %d1,%d2 # make a copy 14064 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 14065 mov.l (%sp)+,%d2 # restore d2 14104 mov.b FPCR_ENABLE(%a6),%d1 14112 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 14132 mov.l %d2,-(%sp) # save d2 14133 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 14134 mov.l %d1,%d2 # make a copy 14141 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 14142 mov.l (%sp)+,%d2 # restore d2 14173 mov.l L_SCR3(%a6),%d1 14194 mov.w (tbl_fsglmul_op.b,%pc,%d1.w*2),%d1 14301 mov.l %d0,L_SCR3(%a6) # store rnd info 14304 mov.b DTAG(%a6),%d1 14314 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 14315 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 14316 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 14318 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 14319 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 14320 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 14323 mov.l %d0,-(%sp) # save scale factor 1 14330 mov.w 2+L_SCR3(%a6),%d1 # fetch precision,mode 14332 mov.l (%sp)+,%d0 14355 mov.l %d2,-(%sp) # save d2 14356 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp} 14357 mov.l %d1,%d2 # make a copy 14362 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 14363 mov.l (%sp)+,%d2 # restore d2 14381 mov.w (%sp),%d1 # fetch new exponent 14391 mov.b FPCR_ENABLE(%a6),%d1 14398 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 14408 mov.l %d2,-(%sp) # save d2 14409 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 14410 mov.l %d1,%d2 # make a copy 14417 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 14418 mov.l (%sp)+,%d2 # restore d2 14437 mov.b FPCR_ENABLE(%a6),%d1 14445 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 14465 mov.l %d2,-(%sp) # save d2 14466 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 14467 mov.l %d1,%d2 # make a copy 14474 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 14475 mov.l (%sp)+,%d2 # restore d2 14529 mov.w (tbl_fsgldiv_op.b,%pc,%d1.w*2),%d1 14648 mov.l %d0,L_SCR3(%a6) # store rnd info 14651 mov.b DTAG(%a6),%d1 14678 mov.l %d2,-(%sp) # save d2 14682 mov.w 2+L_SCR3(%a6),%d1 14685 mov.w (%sp),%d2 # fetch new sign, exp 14697 mov.w (%sp),%d1 14700 mov.w %d1,(%sp) # insert new exponent 14704 mov.l (%sp)+,%d2 # restore d2 14724 mov.b FPCR_ENABLE(%a6),%d1 14732 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 14736 mov.l (%sp)+,%d2 # restore d2 14740 mov.b L_SCR3(%a6),%d1 14745 mov.w (%sp),%d1 14750 mov.w %d1,(%sp) # insert new exponent 14758 mov.l L_SCR3(%a6),%d1 14787 mov.b FPCR_ENABLE(%a6),%d1 14795 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 14799 mov.l (%sp)+,%d2 # restore d2 14805 mov.l L_SCR3(%a6),%d1 14819 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 14820 mov.l %d1,%d2 # make a copy 14827 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 14832 mov.l L_SCR3(%a6),%d1 14844 mov.l L_SCR3(%a6),%d1 14848 mov.l 0x4(%sp),%d1 # extract hi(man) 14870 mov.l L_SCR3(%a6),%d1 14893 mov.w (tbl_fadd_op.b,%pc,%d1.w*2),%d1 14961 mov.b SRC_EX(%a0),%d0 # are the signs opposite 14962 mov.b DST_EX(%a1),%d1 14971 mov.b &z_bmask,FPSR_CC(%a6) # set Z 14980 mov.b 3+L_SCR3(%a6),%d1 14985 mov.b &z_bmask,FPSR_CC(%a6) # set Z 14990 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set NEG/Z 14998 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 14999 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 15000 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 15008 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 15009 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 15010 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 15022 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 15023 mov.b DST_EX(%a1),%d1 15037 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 15047 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 15051 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 15101 mov.l %d0,L_SCR3(%a6) # store rnd info 15104 mov.b DTAG(%a6),%d1 15131 mov.l %d2,-(%sp) # save d2 15135 mov.w 2+L_SCR3(%a6),%d1 15138 mov.w (%sp),%d2 # fetch new exponent 15150 mov.w (%sp),%d1 15153 mov.w %d1,(%sp) # insert new exponent 15157 mov.l (%sp)+,%d2 # restore d2 15177 mov.b FPCR_ENABLE(%a6),%d1 15185 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 15189 mov.l (%sp)+,%d2 # restore d2 15193 mov.b L_SCR3(%a6),%d1 15198 mov.w (%sp),%d1 # fetch {sgn,exp} 15203 mov.w %d1,(%sp) # insert new exponent 15211 mov.l L_SCR3(%a6),%d1 15240 mov.b FPCR_ENABLE(%a6),%d1 15248 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 15252 mov.l (%sp)+,%d2 # restore d2 15258 mov.l L_SCR3(%a6),%d1 15272 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 15273 mov.l %d1,%d2 # make a copy 15280 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 15285 mov.l L_SCR3(%a6),%d1 15297 mov.l L_SCR3(%a6),%d1 15301 mov.l 0x4(%sp),%d1 15323 mov.l L_SCR3(%a6),%d1 15346 mov.w (tbl_fsub_op.b,%pc,%d1.w*2),%d1 15414 mov.b SRC_EX(%a0),%d0 15415 mov.b DST_EX(%a1),%d1 15423 mov.b &z_bmask,FPSR_CC(%a6) # set Z 15432 mov.b 3+L_SCR3(%a6),%d1 15437 mov.b &z_bmask,FPSR_CC(%a6) # set Z 15442 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/NEG 15450 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 15451 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 15452 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 15460 mov.w DST_EX(%a1),FP_SCR1_EX(%a6) 15461 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 15462 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 15474 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 15475 mov.b DST_EX(%a1),%d1 15486 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 15493 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG 15497 mov.b &inf_bmask,FPSR_CC(%a6) # set INF 15546 mov.l %d0,L_SCR3(%a6) # store rnd info 15548 mov.b STAG(%a6),%d1 15578 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 15579 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 15580 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 15597 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 15598 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 15599 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 15625 mov.l %d2,-(%sp) # save d2 15627 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp 15628 mov.l %d1,%d2 # make a copy 15633 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent 15634 mov.l (%sp)+,%d2 # restore d2 15642 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 15643 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 15644 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 15680 mov.b FPCR_ENABLE(%a6),%d1 15688 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 15699 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6) 15700 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6) 15701 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent 15703 mov.l %d2,-(%sp) # save d2 15704 mov.l %d1,%d2 # make a copy 15711 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp 15713 mov.l (%sp)+,%d2 # restore d2 15733 mov.b FPCR_ENABLE(%a6),%d1 15744 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 15756 mov.l %d2,-(%sp) # save d2 15757 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp} 15758 mov.l %d1,%d2 # make a copy 15765 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent 15767 mov.l (%sp)+,%d2 # restore d2 15821 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 15825 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits 15833 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit 15868 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 15869 mov.l DST_HI(%a1),FP_SCR1_HI(%a6) 15870 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 15871 mov.l DST_LO(%a1),FP_SCR1_LO(%a6) 15872 mov.w SRC_EX(%a0),%d0 15873 mov.w DST_EX(%a1),%d1 15874 mov.w %d0,FP_SCR0_EX(%a6) 15875 mov.w %d1,FP_SCR1_EX(%a6) 15879 mov.w %d0,L_SCR1(%a6) # store src exponent 15880 mov.w %d1,2+L_SCR1(%a6) # store dst exponent 15888 mov.l %d0,-(%sp) # save scale factor 15896 mov.w %d0,L_SCR1(%a6) # inset new exp 15899 mov.w 2+L_SCR1(%a6),%d0 15905 mov.w L_SCR1(%a6),%d0 15907 mov.w FP_SCR0_EX(%a6),%d1 15910 mov.w %d0,FP_SCR0_EX(%a6) # insert new dst exponent 15912 mov.l (%sp)+,%d0 # return SCALE factor 15919 mov.l (%sp)+,%d0 # return SCALE factor 15925 mov.l %d0,-(%sp) # save scale factor 15932 mov.w %d0,2+L_SCR1(%a6) # inset new exp 15935 mov.w L_SCR1(%a6),%d0 15941 mov.w 2+L_SCR1(%a6),%d0 15943 mov.w FP_SCR1_EX(%a6),%d1 15946 mov.w %d0,FP_SCR1_EX(%a6) # insert new dst exponent 15948 mov.l (%sp)+,%d0 # return SCALE factor 15955 mov.l (%sp)+,%d0 # return SCALE factor 15985 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp} 15986 mov.w %d1,%d0 # make a copy 15993 mov.w %d0,FP_SCR0_EX(%a6) # insert biased exponent 15999 mov.l &0x3fff,%d0 16008 mov.l %d0,%d1 # prepare for op_norm call 16042 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp} 16052 mov.l &0x3fff,%d0 16060 mov.l &0x3ffe,%d0 16112 mov.w FP_SCR1_EX(%a6),%d1 # extract operand's {sgn,exp} 16113 mov.w %d1,%d0 # make a copy 16120 mov.w %d0,FP_SCR1_EX(%a6) # insert biased exponent 16126 mov.l &0x3fff,%d0 16134 mov.l %d0,%d1 # prepare for op_norm call 16280 mov.l %d0,L_SCR1(%a6) # save displacement 16282 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate 16285 mov.b FPSR_CC(%a6),%d1 # fetch fp ccodes 16289 mov.w (tbl_fdbcc.b,%pc,%d0.w*2),%d1 # load table 16848 mov.b 1+EXC_OPWORD(%a6), %d1 # fetch lo opword 16863 mov.l L_SCR1(%a6),%d0 # fetch displacement 16866 mov.l %d0,EXC_PC(%a6) # set new PC 16874 mov.b &fbsun_flg,SPCOND_FLG(%a6) 16910 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate 16913 mov.b FPSR_CC(%a6),%d1 # fetch fp ccodes 16917 mov.w (tbl_ftrapcc.b,%pc,%d0.w*2), %d1 # load table 17435 mov.b &ftrapcc_flg,SPCOND_FLG(%a6) 17443 mov.b &fbsun_flg,SPCOND_FLG(%a6) 17480 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate 17483 mov.b FPSR_CC(%a6),%d1 # fetch fp ccodes 17487 mov.w (tbl_fscc.b,%pc,%d0.w*2),%d1 # load table 18062 mov.l %d0,%a0 # save result for a moment 18064 mov.b 1+EXC_OPWORD(%a6),%d1 # fetch lo opword 18065 mov.l %d1,%d0 # make a copy 18070 mov.l %d0,%d1 18072 mov.l %a0,%d0 # pass result in d0 18089 mov.l %a0,%d0 # pass result in d0 18090 mov.l EXC_EA(%a6),%a0 # fetch <ea> 18102 mov.l %a0,%d0 # pass result in d0 18103 mov.l EXC_EA(%a6),%a0 # fetch <ea> 18109 mov.b 0x1+EXC_OPWORD(%a6),%d1 # fetch opword 18120 mov.l %a0,%d0 # pass result in d0 18121 mov.l EXC_EA(%a6),%a0 # fetch <ea> 18127 mov.b 0x1+EXC_OPWORD(%a6),%d1 # fetch opword 18139 mov.b &fbsun_flg,SPCOND_FLG(%a6) 18145 mov.w &0x00a1,EXC_VOFF(%a6) 18219 mov.b 1+EXC_EXTWORD(%a6),%d1 # fetch extword 18228 mov.l %d0,-(%sp) # save strg 18229 mov.b (tbl_fmovm_size.w,%pc,%d0),%d0 18230 mov.l %d0,-(%sp) # save size 18232 mov.l (%sp)+,%d0 # restore size 18233 mov.l (%sp)+,%d1 # restore strg 18255 mov.b (tbl_fmovm_convert.w,%pc,%d1.w*1),%d1 18271 mov.l %a0,%a1 # move <ea> to a1 18279 mov.l 0x0+EXC_FP0(%a6),(%a0)+ # yes 18280 mov.l 0x4+EXC_FP0(%a6),(%a0)+ 18281 mov.l 0x8+EXC_FP0(%a6),(%a0)+ 18287 mov.l 0x0+EXC_FP1(%a6),(%a0)+ # yes 18288 mov.l 0x4+EXC_FP1(%a6),(%a0)+ 18289 mov.l 0x8+EXC_FP1(%a6),(%a0)+ 18334 mov.l %a1,L_SCR1(%a6) 18337 mov.l %d0,-(%sp) # save size 18340 mov.l (%sp)+,%d0 18352 mov.l %a0,L_SCR1(%a6) 18357 mov.l %d1,-(%sp) # save bit string for later 18358 mov.l %d0,-(%sp) # save # of bytes 18362 mov.l (%sp)+,%d0 # retrieve # of bytes 18367 mov.l (%sp)+,%d1 # load bit string 18374 mov.l (%a0)+,0x0+EXC_FP0(%a6) # yes 18375 mov.l (%a0)+,0x4+EXC_FP0(%a6) 18376 mov.l (%a0)+,0x8+EXC_FP0(%a6) 18382 mov.l (%a0)+,0x0+EXC_FP1(%a6) # yes 18383 mov.l (%a0)+,0x4+EXC_FP1(%a6) 18384 mov.l (%a0)+,0x8+EXC_FP1(%a6) 18524 mov.l %d0,%a0 # move # bytes to a0 18528 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word 18529 mov.w %d0,%d1 # make a copy 18535 mov.w (tbl_fea_mode.b,%pc,%d0.w*2),%d0 # fetch jmp distance 18616 mov.l EXC_DREGS+0x8(%a6),%a0 # Get current a0 18620 mov.l EXC_DREGS+0xc(%a6),%a0 # Get current a1 18624 mov.l %a2,%a0 # Get current a2 18628 mov.l %a3,%a0 # Get current a3 18632 mov.l %a4,%a0 # Get current a4 18636 mov.l %a5,%a0 # Get current a5 18640 mov.l (%a6),%a0 # Get current a6 18644 mov.l EXC_A7(%a6),%a0 # Get current a7 18651 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 18652 mov.l %d0,%d1 18654 mov.l %d1,EXC_DREGS+0x8(%a6) # Save incr value 18655 mov.l %d0,%a0 18659 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 18660 mov.l %d0,%d1 18662 mov.l %d1,EXC_DREGS+0xc(%a6) # Save incr value 18663 mov.l %d0,%a0 18667 mov.l %a2,%d0 # Get current a2 18668 mov.l %d0,%d1 18670 mov.l %d1,%a2 # Save incr value 18671 mov.l %d0,%a0 18675 mov.l %a3,%d0 # Get current a3 18676 mov.l %d0,%d1 18678 mov.l %d1,%a3 # Save incr value 18679 mov.l %d0,%a0 18683 mov.l %a4,%d0 # Get current a4 18684 mov.l %d0,%d1 18686 mov.l %d1,%a4 # Save incr value 18687 mov.l %d0,%a0 18691 mov.l %a5,%d0 # Get current a5 18692 mov.l %d0,%d1 18694 mov.l %d1,%a5 # Save incr value 18695 mov.l %d0,%a0 18699 mov.l (%a6),%d0 # Get current a6 18700 mov.l %d0,%d1 18702 mov.l %d1,(%a6) # Save incr value 18703 mov.l %d0,%a0 18707 mov.b &mia7_flg,SPCOND_FLG(%a6) # set "special case" flag 18709 mov.l EXC_A7(%a6),%d0 # Get current a7 18710 mov.l %d0,%d1 18712 mov.l %d1,EXC_A7(%a6) # Save incr value 18713 mov.l %d0,%a0 18720 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 18722 mov.l %d0,EXC_DREGS+0x8(%a6) # Save decr value 18723 mov.l %d0,%a0 18727 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 18729 mov.l %d0,EXC_DREGS+0xc(%a6) # Save decr value 18730 mov.l %d0,%a0 18734 mov.l %a2,%d0 # Get current a2 18736 mov.l %d0,%a2 # Save decr value 18737 mov.l %d0,%a0 18741 mov.l %a3,%d0 # Get current a3 18743 mov.l %d0,%a3 # Save decr value 18744 mov.l %d0,%a0 18748 mov.l %a4,%d0 # Get current a4 18750 mov.l %d0,%a4 # Save decr value 18751 mov.l %d0,%a0 18755 mov.l %a5,%d0 # Get current a5 18757 mov.l %d0,%a5 # Save decr value 18758 mov.l %d0,%a0 18762 mov.l (%a6),%d0 # Get current a6 18764 mov.l %d0,(%a6) # Save decr value 18765 mov.l %d0,%a0 18769 mov.b &mda7_flg,SPCOND_FLG(%a6) # set "special case" flag 18771 mov.l EXC_A7(%a6),%d0 # Get current a7 18773 mov.l %d0,EXC_A7(%a6) # Save decr value 18774 mov.l %d0,%a0 18781 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18788 mov.w %d0,%a0 # sign extend displacement 18794 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18801 mov.w %d0,%a0 # sign extend displacement 18807 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18814 mov.w %d0,%a0 # sign extend displacement 18820 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18827 mov.w %d0,%a0 # sign extend displacement 18833 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18840 mov.w %d0,%a0 # sign extend displacement 18846 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18853 mov.w %d0,%a0 # sign extend displacement 18859 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18866 mov.w %d0,%a0 # sign extend displacement 18872 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18879 mov.w %d0,%a0 # sign extend displacement 18893 mov.l %d0,-(%sp) 18895 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18902 mov.l (%sp)+,%a0 18907 mov.l %d0,L_SCR1(%a6) # hold opword 18909 mov.l %d0,%d1 18916 mov.l %d2,-(%sp) # save d2 18917 mov.l L_SCR1(%a6),%d2 # fetch opword 18923 mov.l %d2,%d1 18933 mov.l (%sp)+,%d2 # restore old d2 18940 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18947 mov.w %d0,%a0 # return <ea> in a0 18954 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18961 mov.l %d0,%a0 # return <ea> in a0 18968 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18975 mov.w %d0,%a0 # sign extend displacement 18990 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 18997 mov.l EXC_EXTWPTR(%a6),%a0 # put base in a0 19003 mov.l %d0,L_SCR1(%a6) # store opword 19005 mov.l %d0,%d1 # make extword copy 19012 mov.l %d2,-(%sp) # save d2 19013 mov.l L_SCR1(%a6),%d2 # fetch opword 19019 mov.l %d2,%d1 19029 mov.l (%sp)+,%d2 # restore temp register 19042 mov.l %d0,%d5 # put extword in d5 19043 mov.l %a0,%d3 # put base in d3 19050 mov.l %d0,L_SCR1(%a6) # save d0 (opword) 19055 mov.l %d0,%d2 # put index in d2 19056 mov.l L_SCR1(%a6),%d5 19057 mov.l %a0,%d3 19083 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19093 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19114 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19124 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19138 mov.l %d0,%d4 19143 mov.l %d3,%a0 19155 mov.l %d3,%a0 19166 mov.l %d3,%d0 19168 mov.l %d0,%a0 19175 mov.l %d3,%a0 19178 mov.w &0x0101,%d0 19187 mov.w &0x00e1,%d0 19192 mov.w &0x0161,%d0 19195 mov.l L_SCR1(%a6),%a0 19237 mov.b EXC_EXTWORD(%a6),%d0 # fetch reg select bits 19247 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19254 mov.l %d0,USER_FPSR(%a6) # store new FPSR to stack 19255 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19262 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 19267 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19274 mov.l %d0,USER_FPCR(%a6) # store new FPCR to stack 19275 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19282 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 19287 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19294 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 19295 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19302 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 19307 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19314 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 19315 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19322 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 19323 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr 19330 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to mem 19364 mov.l %d0, %a0 # move # bytes to %a0 19366 mov.b 1+EXC_OPWORD(%a6), %d0 # fetch opcode word 19367 mov.l %d0, %d1 # make a copy 19383 mov.l EXC_EA(%a6),%a0 # return <ea> 19389 mov.b &immed_flg,SPCOND_FLG(%a6) 19396 mov.l %a0,%d0 # pass amt to inc by 19399 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 19407 mov.l %a0,%d0 # pass amt to dec by 19410 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 19417 mov.l %a0,EXC_EA(%a6) # put correct <ea> on stack 19449 mov.b 1+EXC_OPWORD(%a6),%d0 # fetch opcode word 19450 mov.l %d0,%d1 # make a copy 19461 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 19468 mov.w (tbl_ceaf_pi.b,%pc,%d1.w*2),%d1 19469 mov.l EXC_EA(%a6),%a0 19505 mov.b &mia7_flg,SPCOND_FLG(%a6) 19513 mov.w (tbl_ceaf_pd.b,%pc,%d1.w*2),%d1 19514 mov.l EXC_EA(%a6),%a0 19531 mov.l %a0,EXC_DREGS+0x8(%a6) 19534 mov.l %a0,EXC_DREGS+0xc(%a6) 19537 mov.l %a0,%a2 19540 mov.l %a0,%a3 19543 mov.l %a0,%a4 19546 mov.l %a0,%a5 19549 mov.l %a0,EXC_A6(%a6) 19552 mov.l %a0,EXC_A7(%a6) 19553 mov.b &mda7_flg,SPCOND_FLG(%a6) 19629 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension word lo 19647 mov.b %d0, DTAG(%a6) # store the dst optype tag 19658 mov.b %d0, STAG(%a6) # store the src optype tag 19672 mov.w EXC_CMDREG(%a6),%d0 # fetch extension word 19690 mov.b %d0, DTAG(%a6) # store the dst optype tag 19702 mov.w (tbl_op010_dreg.b,%pc,%d0.w*2), %d0 # jmp based on optype 19730 mov.b &ZERO, STAG(%a6) # set ZERO optype flag 19743 mov.b &ZERO, STAG(%a6) # set ZERO optype flag 19756 mov.b &ZERO, STAG(%a6) # set ZERO optype flag 19767 mov.l %d0,L_SCR1(%a6) 19771 mov.b %d0, STAG(%a6) # save the src tag 19800 mov.w (tbl_fp_type.b,%pc,%d0.w*2), %d0 # index by src type field 19840 mov.b &ZERO, STAG(%a6) # set optype tag to ZERO 19876 mov.b &ZERO, STAG(%a6) # set optype tag to ZERO 19912 mov.b &ZERO, STAG(%a6) # set optype tag to ZERO 19937 mov.l %d0, L_SCR1(%a6) # store src op on stack 19945 mov.b %d0, STAG(%a6) # save src optype tag on stack 19971 mov.l %d0, FP_SRC_HI(%a6) # set ext hi(_mantissa) 19982 mov.w &0x3f81, %d1 # xprec exp = 0x3f81 19986 mov.b &NORM, STAG(%a6) # fix src type tag 19992 mov.w &0x7fff, FP_SRC_EX(%a6) # set exp of SNAN 19995 mov.l %d0, FP_SRC_HI(%a6) 20028 mov.b %d0, STAG(%a6) # set src optype tag 20055 mov.l %d0, FP_SRC_HI(%a6) 20057 mov.l &0xb, %d1 20059 mov.l %d0, FP_SRC_LO(%a6) 20068 mov.w &0x3c01, %d1 # xprec exp = 0x3c01 20072 mov.b &NORM, STAG(%a6) # fix src type tag 20078 mov.w &0x7fff, FP_SRC_EX(%a6) # set exp of SNAN 20081 mov.l %d0, FP_SRC_HI(%a6) 20083 mov.l &0xb, %d1 20085 mov.l %d0, FP_SRC_LO(%a6) 20101 mov.l &0xc, %d0 # pass: 12 (bytes) 20105 mov.l &0xc, %d0 # pass: # of bytes to read 20117 mov.b %d0, STAG(%a6) # store the src optype tag 20122 mov.b %d0, STAG(%a6) # store the src optype tag 20140 mov.b %d0,STAG(%a6) # store the src optype tag 20145 mov.b %d0,STAG(%a6) # store the src optype tag 20202 mov.w (tbl_fout.b,%pc,%d1.w*2),%a1 # use as index 20237 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 20241 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 20250 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 20256 mov.l SRC_EX(%a0),%d1 20283 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 20287 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 20296 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 20302 mov.l SRC_EX(%a0),%d1 20330 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 20334 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 20343 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 20349 mov.l SRC_EX(%a0),%d1 20367 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 20369 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 20370 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 20376 mov.l %a0,%a1 # pass: dst addr 20378 mov.l &0xc,%d0 # pass: opsize is 12 bytes 20399 mov.b FPCR_ENABLE(%a6),%d0 20427 mov.l EXC_A6(%a6),(%a6) # fix stacked a6 20436 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 20444 mov.w SRC_EX(%a0),%d0 # extract exponent 20471 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 20475 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 20484 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 20497 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 20498 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 20499 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 20500 mov.l %a0,-(%sp) 20512 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 20518 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 20522 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 20531 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 20536 mov.b FPCR_ENABLE(%a6),%d1 20556 mov.l %a0,-(%sp) 20563 mov.l L_SCR3(%a6),%d0 # pass: sgl prec,rnd mode 20568 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode 20572 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct 20581 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn 20586 mov.b FPCR_ENABLE(%a6),%d1 20601 mov.w SRC_EX(%a0),%d1 # fetch current sign 20604 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp 20605 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy hi(man) 20606 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy lo(man) 20621 mov.l (%sp)+,%a0 20623 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 20624 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 20625 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 20639 mov.l (%sp)+,%a0 # restore a0 20641 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 20642 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 20643 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 20650 mov.b 3+L_SCR3(%a6),%d1 20654 mov.b 3+L_SCR3(%a6),%d1 20674 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 20682 mov.w SRC_EX(%a0),%d0 # extract exponent 20708 mov.l EXC_EA(%a6),%a1 # pass: dst addr 20726 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) 20727 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) 20728 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) 20729 mov.l %a0,-(%sp) 20741 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode 20746 mov.l %d0,L_SCR1(%a6) 20747 mov.l %d1,L_SCR2(%a6) 20749 mov.l EXC_EA(%a6),%a1 # pass: dst addr 20757 mov.b FPCR_ENABLE(%a6),%d1 20767 mov.w 2+SRC_LO(%a0),%d0 20777 mov.l %a0,-(%sp) 20784 mov.l L_SCR3(%a6),%d0 # pass: dbl prec,rnd mode 20789 mov.l EXC_EA(%a6),%a1 # pass: dst addr 20797 mov.b FPCR_ENABLE(%a6),%d1 20812 mov.w SRC_EX(%a0),%d1 # fetch current sign 20815 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp 20816 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy hi(man) 20817 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy lo(man) 20869 mov.w FTEMP_EX(%a0),%d0 # get exponent 20882 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa 20885 mov.l %d0,L_SCR1(%a6) # put the new exp back on the stack 20886 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa 20887 mov.l &21,%d0 # load shift count 20889 mov.l %d1,L_SCR2(%a6) # build lower lword in memory 20890 mov.l FTEMP_LO(%a0),%d1 # get ls mantissa 20892 mov.l L_SCR2(%a6),%d1 20894 mov.l L_SCR1(%a6),%d0 20934 mov.w FTEMP_EX(%a0),%d0 # get exponent 20947 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa 20956 mov.l %a0,-(%sp) 20958 mov.b STAG(%a6),%d0 # fetch input type 20966 mov.b 1+EXC_CMDREG(%a6),%d1 # fetch dynamic reg 20974 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch static field 20978 mov.l %d0,-(%sp) 20989 mov.l (%sp)+,%d0 21014 mov.l (%sp)+,%a1 # pass: dst addr 21015 mov.l &0xc,%d0 # pass: opsize is 12 bytes 21075 mov.w (tbl_fdreg.b,%pc,%d1.w*2),%d0 21097 mov.l EXC_DREGS+0x0(%a6),%d0 21100 mov.l EXC_DREGS+0x4(%a6),%d0 21103 mov.l %d2,%d0 21106 mov.l %d3,%d0 21109 mov.l %d4,%d0 21112 mov.l %d5,%d0 21115 mov.l %d6,%d0 21118 mov.l %d7,%d0 21121 mov.l EXC_DREGS+0x8(%a6),%d0 21124 mov.l EXC_DREGS+0xc(%a6),%d0 21127 mov.l %a2,%d0 21130 mov.l %a3,%d0 21133 mov.l %a4,%d0 21136 mov.l %a5,%d0 21139 mov.l (%a6),%d0 21142 mov.l EXC_A7(%a6),%d0 21168 mov.w (tbl_sdregl.b,%pc,%d1.w*2),%d1 21182 mov.l %d0,EXC_DREGS+0x0(%a6) 21185 mov.l %d0,EXC_DREGS+0x4(%a6) 21188 mov.l %d0,%d2 21191 mov.l %d0,%d3 21194 mov.l %d0,%d4 21197 mov.l %d0,%d5 21200 mov.l %d0,%d6 21203 mov.l %d0,%d7 21229 mov.w (tbl_sdregw.b,%pc,%d1.w*2),%d1 21243 mov.w %d0,2+EXC_DREGS+0x0(%a6) 21246 mov.w %d0,2+EXC_DREGS+0x4(%a6) 21249 mov.w %d0,%d2 21252 mov.w %d0,%d3 21255 mov.w %d0,%d4 21258 mov.w %d0,%d5 21261 mov.w %d0,%d6 21264 mov.w %d0,%d7 21290 mov.w (tbl_sdregb.b,%pc,%d1.w*2),%d1 21304 mov.b %d0,3+EXC_DREGS+0x0(%a6) 21307 mov.b %d0,3+EXC_DREGS+0x4(%a6) 21310 mov.b %d0,%d2 21313 mov.b %d0,%d3 21316 mov.b %d0,%d4 21319 mov.b %d0,%d5 21322 mov.b %d0,%d6 21325 mov.b %d0,%d7 21356 mov.w (tbl_iareg.b,%pc,%d1.w*2),%d1 21383 iareg7: mov.b &mia7_flg,SPCOND_FLG(%a6) 21420 mov.w (tbl_dareg.b,%pc,%d1.w*2),%d1 21447 dareg7: mov.b &mda7_flg,SPCOND_FLG(%a6) 21479 mov.w (tbl_load_fpn1.b,%pc,%d0.w*2), %d0 21493 mov.l 0+EXC_FP0(%a6), 0+FP_SRC(%a6) 21494 mov.l 4+EXC_FP0(%a6), 4+FP_SRC(%a6) 21495 mov.l 8+EXC_FP0(%a6), 8+FP_SRC(%a6) 21499 mov.l 0+EXC_FP1(%a6), 0+FP_SRC(%a6) 21500 mov.l 4+EXC_FP1(%a6), 4+FP_SRC(%a6) 21501 mov.l 8+EXC_FP1(%a6), 8+FP_SRC(%a6) 21552 mov.w (tbl_load_fpn2.b,%pc,%d0.w*2), %d0 21566 mov.l 0+EXC_FP0(%a6), 0+FP_DST(%a6) 21567 mov.l 4+EXC_FP0(%a6), 4+FP_DST(%a6) 21568 mov.l 8+EXC_FP0(%a6), 8+FP_DST(%a6) 21572 mov.l 0+EXC_FP1(%a6), 0+FP_DST(%a6) 21573 mov.l 4+EXC_FP1(%a6), 4+FP_DST(%a6) 21574 mov.l 8+EXC_FP1(%a6), 8+FP_DST(%a6) 21627 mov.w (tbl_store_fpreg.b,%pc,%d0.w*2), %d0 21719 mov.w (tbl_thresh.b,%pc,%d0.w*2), %d1 # load prec threshold 21720 mov.w %d1, %d0 # copy d1 into d0 21739 mov.l &0x20000000, %d0 # set sticky bit in return value 21740 mov.w %d1, FTEMP_EX(%a0) # load exp with threshold 21768 mov.l FTEMP_LO(%a0), FTEMP_LO2(%a6) # make FTEMP_LO copy 21769 mov.l %d0, GRS(%a6) # place g,r,s after it 21775 mov.l %d1, %d0 # copy the denorm threshold 21788 mov.l GRS(%a6), %d0 # restore original g,r,s 21815 mov.l %d2, -(%sp) # create temp storage 21817 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 21818 mov.l &32, %d0 21823 mov.b GRS(%a6), %d2 21831 mov.l %d2, FTEMP_HI(%a0) # store new FTEMP_HI 21832 mov.l %d1, FTEMP_LO(%a0) # store new FTEMP_LO 21840 mov.l (%sp)+, %d2 # restore temp register 21867 mov.l %d2, -(%sp) # create temp storage 21869 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 21871 mov.l &0x20, %d0 21877 mov.b GRS(%a6), %d2 21888 mov.l %d1, %d0 # move new G,R,S to %d0 21892 mov.l %d1, %d0 # move new G,R,S to %d0 21897 mov.l %d2, FTEMP_LO(%a0) # store FTEMP_LO 21900 mov.l (%sp)+,%d2 # restore temp register 21910 mov.w %d0, FTEMP_EX(%a0) # insert denorm threshold 21924 mov.l &0x20000000, %d0 # set sticky bit 21948 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 21949 mov.l %d0, %d1 # make a copy 21976 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 22062 mov.w (tbl_mode.b,%pc,%d1.w*2), %a1 # load jump offset 22080 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 22097 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 22253 mov.l &30, %d2 # of the sgl prec. limits 22255 mov.l FTEMP_HI(%a0), %d2 # get word 2 for s-bit test 22278 mov.l &30, %d2 # of the dbl prec. limits 22280 mov.l FTEMP_LO(%a0), %d2 # get lower mantissa for s-bit test 22290 mov.l %d3, %d0 # return grs to d0 22318 mov.l %d2, -(%sp) # create some temp regs 22319 mov.l %d3, -(%sp) 22321 mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) 22322 mov.l FTEMP_LO(%a0), %d1 # load lo(mantissa) 22334 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 22335 mov.l %d1, FTEMP_LO(%a0) # store new lo(man) 22337 mov.l %d2, %d0 # return shift amount 22339 mov.l (%sp)+, %d3 # restore temp regs 22340 mov.l (%sp)+, %d2 22349 mov.l %d1, FTEMP_HI(%a0) # store hi(man) 22352 mov.l %d2, %d0 # return shift amount 22354 mov.l (%sp)+, %d3 # restore temp regs 22355 mov.l (%sp)+, %d2 22398 mov.w FTEMP_EX(%a0), %d1 # extract exponent 22408 mov.w FTEMP_EX(%a0), %d0 # load old exponent 22411 mov.w %d1, FTEMP_EX(%a0) # insert new exponent 22415 mov.b &NORM, %d0 # return new optype tag 22426 mov.l %d0, FTEMP_HI(%a0) # save new hi(man) 22428 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 22430 mov.l %d0, FTEMP_LO(%a0) # save new lo(man) 22434 mov.b &DENORM, %d0 # return new optype tag 22443 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 22446 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 22451 mov.b &DENORM, %d0 # return new optype tag 22460 mov.b &ZERO, %d0 # fix optype tag 22487 mov.w FTEMP_EX(%a0), %d0 # extract exponent 22495 mov.b &NORM, %d0 22506 mov.b &ZERO, %d0 22509 mov.b &DENORM, %d0 22520 mov.b &ZERO, %d0 22523 mov.b &UNNORM, %d0 22528 mov.l FTEMP_HI(%a0), %d0 22532 mov.b &INF, %d0 22537 mov.b &QNAN, %d0 22540 mov.b &SNAN, %d0 22565 mov.l FTEMP(%a0), %d0 22566 mov.l %d0, %d1 22575 mov.b &NORM, %d0 22583 mov.b &ZERO, %d0 22586 mov.b &DENORM, %d0 22594 mov.b &INF, %d0 22600 mov.b &SNAN, %d0 22603 mov.b &QNAN, %d0 22628 mov.l FTEMP(%a0), %d0 22629 mov.l %d0, %d1 22638 mov.b &NORM, %d0 22644 mov.b &ZERO, %d0 22647 mov.b &DENORM, %d0 22653 mov.b &INF, %d0 22659 mov.b &SNAN, %d0 22662 mov.b &QNAN, %d0 22701 mov.l %d1, -(%sp) # save rnd prec,mode on stack 22706 mov.w FTEMP_EX(%a0), %d1 # extract exponent 22709 mov.w %d1, FTEMP_EX(%a0) # insert 16 bit exponent 22711 mov.l %a0, -(%sp) # save operand ptr during calls 22713 mov.l 0x4(%sp),%d0 # pass rnd prec. 22718 mov.l (%sp),%a0 22719 mov.w 0x6(%sp),%d1 # load prec:mode into %d1 22723 mov.w 0x6(%sp),%d1 22728 mov.l (%sp)+, %a0 22765 mov.l %d1,-(%sp) # save rnd prec,mode on stack 22770 mov.w FTEMP_EX(%a0),%d1 # extract exponent 22773 mov.w %d1,FTEMP_EX(%a0) # insert 16 bit exponent 22775 mov.l %a0,-(%sp) # save operand ptr during calls 22780 mov.l (%sp),%a0 22781 mov.w &s_mode,%d1 # force rnd prec = sgl 22783 mov.w 0x6(%sp),%d1 # load rnd mode 22788 mov.l (%sp)+,%a0 22859 mov.w %d1,%d0 # make a copy 22869 mov.w %d1, %d0 # make a copy 22877 mov.b (tbl_ovfl_cc.b,%pc,%d0.w*1), %d0 # fetch result ccodes 22960 mov.l &0xc,%d0 # packed is 12 bytes 22964 mov.l &0xc,%d0 # pass: 12 bytes 22979 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 23072 mov.l 0x0(%a0),FP_SCR0_EX(%a6) # make a copy of input 23073 mov.l 0x4(%a0),FP_SCR0_HI(%a6) # so we don't alter it 23074 mov.l 0x8(%a0),FP_SCR0_LO(%a6) 23102 mov.l &EDIGITS,%d2 # # of nibbles (digits) in fraction part 23103 mov.l &ESTRT,%d3 # counter to pick up digits 23104 mov.l (%a0),%d4 # get first word of bcd 23122 mov.l %d1,-(%sp) # save exp on stack 23145 mov.l &1,%d1 # word counter, init to 1 23160 mov.l (%a0,%d1.L*4),%d4 # load mantissa lonqword into d4 23161 mov.l &FSTRT,%d3 # counter to pick up digits 23162 mov.l &FNIBS,%d2 # reset number of digits per a0 ptr 23238 mov.l (%sp),%d1 # load expA for range test 23244 mov.l (%a0),%d4 # load lword 1 to d4 23248 mov.l &1,%d5 # init lword counter 23249 mov.l (%a0,%d5.L*4),%d4 # get lword 2 to d4 23253 mov.l (%a0,%d5.L*4),%d4 # get lword 3 to d4 23256 mov.l &7,%d2 # init digit counter 23264 mov.l %d1,%d0 # copy counter to d2 23265 mov.l (%sp),%d1 # get adjusted exp from memory 23269 mov.l (%a0),%d4 # load lword 1 to d4 23280 mov.l &3,%d2 # init d2 to count bits in counter 23296 mov.l &2,%d5 # set up d5 to point to lword 3 23297 mov.l (%a0,%d5.L*4),%d4 # get lword 3 23301 mov.l (%a0,%d5.L*4),%d4 # get lword 2 23303 mov.l &28,%d3 # point to last digit 23304 mov.l &7,%d2 # init digit counter 23312 mov.l %d1,%d0 # copy counter to d0 23313 mov.l (%sp),%d1 # get adjusted exp from memory 23317 mov.l (%a0),%d4 # load lword 1 to d4 23328 mov.l &3,%d2 # init d2 to count bits in counter 23383 mov.l USER_FPCR(%a6),%d3 # get user's FPCR 23385 mov.l (%a0),%d4 # reload 1st bcd word to d4 23390 mov.b (%a1,%d2),%d0 # load new rounding bits from table 23406 mov.l %d1,%d0 # copy exp to d0;use d0 23623 mov.l (%a0),L_SCR2(%a6) # save exponent for sign check 23624 mov.l %d0,%d7 # move k-factor to d7 23634 mov.w (%a0),%d0 23636 mov.l 4(%a0),%d1 23637 mov.l 8(%a0),%d2 23652 mov.w %d0,(%a0) 23653 mov.l %d1,4(%a0) 23654 mov.l %d2,8(%a0) 23659 mov.l (%a0),FP_SCR1(%a6) # move input to work space 23660 mov.l 4(%a0),FP_SCR1+4(%a6) # move input to work space 23661 mov.l 8(%a0),FP_SCR1+8(%a6) # move input to work space 23692 mov.l &-4933,%d6 # force ILOG = -4933 23695 mov.w FP_SCR1(%a6),%d0 # move exp to d0 23696 mov.w &0x3fff,FP_SCR1(%a6) # replace exponent with 0x3fff 23755 mov.l %d7,%d4 # if k > 0, LEN = k 23758 mov.l %d6,%d4 # first load ILOG to d4 23766 mov.l &17,%d4 # set max LEN = 17 23772 mov.l &1,%d4 # min LEN is 1 23829 mov.l %d7,%d6 # if ((k<0) & (ILOG < k)) ILOG = k 23831 mov.l %d6,%d0 # calc ILOG + 1 - LEN in d0 23843 mov.l &24,%d2 # put 24 in d2 for A9 23857 mov.b (%a2,%d1),%d3 # load d3 with new rmode 23947 mov.w (%sp),%d3 # grab exponent 23962 mov.l 0x8(%a0),-(%sp) # put input op mantissa on stk 23963 mov.l 0x4(%a0),-(%sp) 23964 mov.l &0x3fff0000,-(%sp) # force exp to zero 23970 mov.l 36+8(%a1),-(%sp) # get 10^8 mantissa 23971 mov.l 36+4(%a1),-(%sp) 23972 mov.l &0x3fff0000,-(%sp) # force exp to zero 23973 mov.l 48+8(%a1),-(%sp) # get 10^16 mantissa 23974 mov.l 48+4(%a1),-(%sp) 23975 mov.l &0x3fff0000,-(%sp)# force exp to zero 24028 mov.l USER_FPCR(%a6),L_SCR1(%a6) # save it for later 24059 mov.l L_SCR1(%a6),-(%sp) 24060 mov.l L_SCR2(%a6),-(%sp) 24068 mov.l USER_FPSR(%a6),-(%sp) 24073 ## mov.l USER_FPCR(%a6),%d0 # ext prec/keep rnd mode 24083 mov.b (%sp),USER_FPSR(%a6) 24086 mov.l (%sp)+,L_SCR2(%a6) 24087 mov.l (%sp)+,L_SCR1(%a6) 24090 mov.l L_SCR2(%a6),FP_SCR1(%a6) # restore original exponent 24091 mov.l L_SCR1(%a6),USER_FPCR(%a6) # restore user's FPCR 24132 mov.l %d4,%d0 # put LEN in d0 24159 mov.w &1,%d5 # set ICTR 24173 mov.w &1,%d5 # set ICTR 24184 mov.l %d4,%d0 # put LEN in d0 24238 mov.l 4(%a0),%d2 # move 2nd word of FP_RES to d2 24239 mov.l 8(%a0),%d3 # move 3rd word of FP_RES to d3 24242 mov.l (%a0),%d0 # move exponent to d0 24264 mov.l %d4,%d0 # put LEN in d0 for binstr call 24333 mov.l 4(%a2),%d2 # move word 2 to d2 24334 mov.l 8(%a2),%d3 # move word 3 to d3 24335 mov.w (%a2),%d0 # move exp to d0 24348 mov.l &4,%d0 # put 4 in d0 for binstr call 24351 mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0 24352 mov.l &12,%d1 # use d1 for shift count 24390 mov.l &2,%d0 # move 2 in to d0 for SM 24520 mov.l &1,%d7 # init d7 for second digit 24526 mov.l %d2,%d4 # copy the fraction before muls 24527 mov.l %d3,%d5 # to d4:d5 24561 mov.b %d7,(%a0)+ # store d7b byte in memory 24568 mov.w %d1,%d7 # put new digit in d7b 24574 mov.b %d7,(%a0)+ # store it in memory string 24619 mov.w &0x0121,EXC_VOFF(%a6) # set FSLW 24626 mov.w &0x0141,EXC_VOFF(%a6) # set FSLW 24633 mov.w &0x0101,EXC_VOFF(%a6) # set FSLW 24640 mov.w &0x0161,EXC_VOFF(%a6) # set FSLW 24647 mov.w &0x0161,EXC_VOFF(%a6) # set FSLW 24656 mov.w &0x00a1,EXC_VOFF(%a6) # set FSLW 24663 mov.w &0x00c1,EXC_VOFF(%a6) # set FSLW 24670 mov.w &0x0081,EXC_VOFF(%a6) # set FSLW 24677 mov.w &0x00e1,EXC_VOFF(%a6) # set FSLW 24681 mov.l &0xc,%d0 # twelve bytes 24684 mov.w &0x00e1,EXC_VOFF(%a6) # set FSLW 24689 mov.l USER_FPIAR(%a6),EXC_PC(%a6) # store current PC 24697 mov.l (%sp),-(%sp) # store SR, hi(PC) 24698 mov.l 0x8(%sp),0x4(%sp) # store lo(PC) 24699 mov.l 0xc(%sp),0x8(%sp) # store EA 24700 mov.l &0x00000001,0xc(%sp) # store FSLW 24701 mov.w 0x6(%sp),0xc(%sp) # fix FSLW (size) 24702 mov.w &0x4008,0x6(%sp) # store voff 24719 mov.b EXC_OPWORD+0x1(%a6),%d1 24728 mov.b EXC_OPWORD+0x1(%a6),%d1 24731 mov.w (tbl_rest_inc.b,%pc,%d1.w*2),%d1
|
H A D | fplsp.S | 578 mov.b %d0,STAG(%a6) 579 mov.b %d0,%d1 584 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 635 mov.b %d0,STAG(%a6) 636 mov.b %d0,%d1 641 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 643 mov.b %d1,STAG(%a6) 690 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 691 mov.l 0x8+0x4(%a6),0x4(%a0) 692 mov.l 0x8+0x8(%a6),0x8(%a0) 694 mov.b %d0,STAG(%a6) 695 mov.b %d0,%d1 700 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 755 mov.b %d0,STAG(%a6) 756 mov.b %d0,%d1 761 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 812 mov.b %d0,STAG(%a6) 813 mov.b %d0,%d1 818 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 820 mov.b %d1,STAG(%a6) 867 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 868 mov.l 0x8+0x4(%a6),0x4(%a0) 869 mov.l 0x8+0x8(%a6),0x8(%a0) 871 mov.b %d0,STAG(%a6) 872 mov.b %d0,%d1 877 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 932 mov.b %d0,STAG(%a6) 933 mov.b %d0,%d1 938 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 989 mov.b %d0,STAG(%a6) 990 mov.b %d0,%d1 995 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 997 mov.b %d1,STAG(%a6) 1044 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 1045 mov.l 0x8+0x4(%a6),0x4(%a0) 1046 mov.l 0x8+0x8(%a6),0x8(%a0) 1048 mov.b %d0,STAG(%a6) 1049 mov.b %d0,%d1 1054 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1109 mov.b %d0,STAG(%a6) 1110 mov.b %d0,%d1 1115 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1166 mov.b %d0,STAG(%a6) 1167 mov.b %d0,%d1 1172 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1174 mov.b %d1,STAG(%a6) 1221 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 1222 mov.l 0x8+0x4(%a6),0x4(%a0) 1223 mov.l 0x8+0x8(%a6),0x8(%a0) 1225 mov.b %d0,STAG(%a6) 1226 mov.b %d0,%d1 1231 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1286 mov.b %d0,STAG(%a6) 1287 mov.b %d0,%d1 1292 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1343 mov.b %d0,STAG(%a6) 1344 mov.b %d0,%d1 1349 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1351 mov.b %d1,STAG(%a6) 1398 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 1399 mov.l 0x8+0x4(%a6),0x4(%a0) 1400 mov.l 0x8+0x8(%a6),0x8(%a0) 1402 mov.b %d0,STAG(%a6) 1403 mov.b %d0,%d1 1408 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1463 mov.b %d0,STAG(%a6) 1464 mov.b %d0,%d1 1469 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1520 mov.b %d0,STAG(%a6) 1521 mov.b %d0,%d1 1526 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1528 mov.b %d1,STAG(%a6) 1575 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 1576 mov.l 0x8+0x4(%a6),0x4(%a0) 1577 mov.l 0x8+0x8(%a6),0x8(%a0) 1579 mov.b %d0,STAG(%a6) 1580 mov.b %d0,%d1 1585 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1640 mov.b %d0,STAG(%a6) 1641 mov.b %d0,%d1 1646 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1697 mov.b %d0,STAG(%a6) 1698 mov.b %d0,%d1 1703 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1705 mov.b %d1,STAG(%a6) 1752 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 1753 mov.l 0x8+0x4(%a6),0x4(%a0) 1754 mov.l 0x8+0x8(%a6),0x8(%a0) 1756 mov.b %d0,STAG(%a6) 1757 mov.b %d0,%d1 1762 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1817 mov.b %d0,STAG(%a6) 1818 mov.b %d0,%d1 1823 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1874 mov.b %d0,STAG(%a6) 1875 mov.b %d0,%d1 1880 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1882 mov.b %d1,STAG(%a6) 1929 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 1930 mov.l 0x8+0x4(%a6),0x4(%a0) 1931 mov.l 0x8+0x8(%a6),0x8(%a0) 1933 mov.b %d0,STAG(%a6) 1934 mov.b %d0,%d1 1939 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1994 mov.b %d0,STAG(%a6) 1995 mov.b %d0,%d1 2000 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2051 mov.b %d0,STAG(%a6) 2052 mov.b %d0,%d1 2057 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2059 mov.b %d1,STAG(%a6) 2106 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 2107 mov.l 0x8+0x4(%a6),0x4(%a0) 2108 mov.l 0x8+0x8(%a6),0x8(%a0) 2110 mov.b %d0,STAG(%a6) 2111 mov.b %d0,%d1 2116 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2171 mov.b %d0,STAG(%a6) 2172 mov.b %d0,%d1 2177 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2228 mov.b %d0,STAG(%a6) 2229 mov.b %d0,%d1 2234 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2236 mov.b %d1,STAG(%a6) 2283 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 2284 mov.l 0x8+0x4(%a6),0x4(%a0) 2285 mov.l 0x8+0x8(%a6),0x8(%a0) 2287 mov.b %d0,STAG(%a6) 2288 mov.b %d0,%d1 2293 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2348 mov.b %d0,STAG(%a6) 2349 mov.b %d0,%d1 2354 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2405 mov.b %d0,STAG(%a6) 2406 mov.b %d0,%d1 2411 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2413 mov.b %d1,STAG(%a6) 2460 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 2461 mov.l 0x8+0x4(%a6),0x4(%a0) 2462 mov.l 0x8+0x8(%a6),0x8(%a0) 2464 mov.b %d0,STAG(%a6) 2465 mov.b %d0,%d1 2470 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2525 mov.b %d0,STAG(%a6) 2526 mov.b %d0,%d1 2531 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2582 mov.b %d0,STAG(%a6) 2583 mov.b %d0,%d1 2588 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2590 mov.b %d1,STAG(%a6) 2637 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 2638 mov.l 0x8+0x4(%a6),0x4(%a0) 2639 mov.l 0x8+0x8(%a6),0x8(%a0) 2641 mov.b %d0,STAG(%a6) 2642 mov.b %d0,%d1 2647 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2702 mov.b %d0,STAG(%a6) 2703 mov.b %d0,%d1 2708 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2759 mov.b %d0,STAG(%a6) 2760 mov.b %d0,%d1 2765 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2767 mov.b %d1,STAG(%a6) 2814 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 2815 mov.l 0x8+0x4(%a6),0x4(%a0) 2816 mov.l 0x8+0x8(%a6),0x8(%a0) 2818 mov.b %d0,STAG(%a6) 2819 mov.b %d0,%d1 2824 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2879 mov.b %d0,STAG(%a6) 2880 mov.b %d0,%d1 2885 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2936 mov.b %d0,STAG(%a6) 2937 mov.b %d0,%d1 2942 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2944 mov.b %d1,STAG(%a6) 2991 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 2992 mov.l 0x8+0x4(%a6),0x4(%a0) 2993 mov.l 0x8+0x8(%a6),0x8(%a0) 2995 mov.b %d0,STAG(%a6) 2996 mov.b %d0,%d1 3001 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3056 mov.b %d0,STAG(%a6) 3057 mov.b %d0,%d1 3062 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3113 mov.b %d0,STAG(%a6) 3114 mov.b %d0,%d1 3119 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3121 mov.b %d1,STAG(%a6) 3168 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 3169 mov.l 0x8+0x4(%a6),0x4(%a0) 3170 mov.l 0x8+0x8(%a6),0x8(%a0) 3172 mov.b %d0,STAG(%a6) 3173 mov.b %d0,%d1 3178 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3233 mov.b %d0,STAG(%a6) 3234 mov.b %d0,%d1 3239 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3290 mov.b %d0,STAG(%a6) 3291 mov.b %d0,%d1 3296 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3298 mov.b %d1,STAG(%a6) 3345 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 3346 mov.l 0x8+0x4(%a6),0x4(%a0) 3347 mov.l 0x8+0x8(%a6),0x8(%a0) 3349 mov.b %d0,STAG(%a6) 3350 mov.b %d0,%d1 3355 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3410 mov.b %d0,STAG(%a6) 3411 mov.b %d0,%d1 3416 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3467 mov.b %d0,STAG(%a6) 3468 mov.b %d0,%d1 3473 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3475 mov.b %d1,STAG(%a6) 3522 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 3523 mov.l 0x8+0x4(%a6),0x4(%a0) 3524 mov.l 0x8+0x8(%a6),0x8(%a0) 3526 mov.b %d0,STAG(%a6) 3527 mov.b %d0,%d1 3532 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3587 mov.b %d0,STAG(%a6) 3588 mov.b %d0,%d1 3593 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3644 mov.b %d0,STAG(%a6) 3645 mov.b %d0,%d1 3650 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3652 mov.b %d1,STAG(%a6) 3699 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 3700 mov.l 0x8+0x4(%a6),0x4(%a0) 3701 mov.l 0x8+0x8(%a6),0x8(%a0) 3703 mov.b %d0,STAG(%a6) 3704 mov.b %d0,%d1 3709 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3764 mov.b %d0,STAG(%a6) 3765 mov.b %d0,%d1 3770 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3821 mov.b %d0,STAG(%a6) 3822 mov.b %d0,%d1 3827 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3829 mov.b %d1,STAG(%a6) 3876 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 3877 mov.l 0x8+0x4(%a6),0x4(%a0) 3878 mov.l 0x8+0x8(%a6),0x8(%a0) 3880 mov.b %d0,STAG(%a6) 3881 mov.b %d0,%d1 3886 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3941 mov.b %d0,STAG(%a6) 3942 mov.b %d0,%d1 3947 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3998 mov.b %d0,STAG(%a6) 3999 mov.b %d0,%d1 4004 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4006 mov.b %d1,STAG(%a6) 4053 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 4054 mov.l 0x8+0x4(%a6),0x4(%a0) 4055 mov.l 0x8+0x8(%a6),0x8(%a0) 4057 mov.b %d0,STAG(%a6) 4058 mov.b %d0,%d1 4063 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4118 mov.b %d0,STAG(%a6) 4119 mov.b %d0,%d1 4124 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4177 mov.b %d0,STAG(%a6) 4178 mov.b %d0,%d1 4183 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4185 mov.b %d1,STAG(%a6) 4234 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input 4235 mov.l 0x8+0x4(%a6),0x4(%a0) 4236 mov.l 0x8+0x8(%a6),0x8(%a0) 4238 mov.b %d0,STAG(%a6) 4239 mov.b %d0,%d1 4244 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4301 mov.b %d0,DTAG(%a6) 4307 mov.b %d0,STAG(%a6) 4308 mov.l %d0,%d1 4313 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4367 mov.b %d0,DTAG(%a6) 4373 mov.b %d0,STAG(%a6) 4374 mov.l %d0,%d1 4379 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4430 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst 4431 mov.l 0x8+0x4(%a6),0x4(%a0) 4432 mov.l 0x8+0x8(%a6),0x8(%a0) 4434 mov.b %d0,DTAG(%a6) 4437 mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src 4438 mov.l 0x14+0x4(%a6),0x4(%a0) 4439 mov.l 0x14+0x8(%a6),0x8(%a0) 4441 mov.b %d0,STAG(%a6) 4442 mov.l %d0,%d1 4447 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4505 mov.b %d0,DTAG(%a6) 4511 mov.b %d0,STAG(%a6) 4512 mov.l %d0,%d1 4517 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4571 mov.b %d0,DTAG(%a6) 4577 mov.b %d0,STAG(%a6) 4578 mov.l %d0,%d1 4583 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4634 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst 4635 mov.l 0x8+0x4(%a6),0x4(%a0) 4636 mov.l 0x8+0x8(%a6),0x8(%a0) 4638 mov.b %d0,DTAG(%a6) 4641 mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src 4642 mov.l 0x14+0x4(%a6),0x4(%a0) 4643 mov.l 0x14+0x8(%a6),0x8(%a0) 4645 mov.b %d0,STAG(%a6) 4646 mov.l %d0,%d1 4651 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4709 mov.b %d0,DTAG(%a6) 4715 mov.b %d0,STAG(%a6) 4716 mov.l %d0,%d1 4721 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4775 mov.b %d0,DTAG(%a6) 4781 mov.b %d0,STAG(%a6) 4782 mov.l %d0,%d1 4787 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4838 mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst 4839 mov.l 0x8+0x4(%a6),0x4(%a0) 4840 mov.l 0x8+0x8(%a6),0x8(%a0) 4842 mov.b %d0,DTAG(%a6) 4845 mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src 4846 mov.l 0x14+0x4(%a6),0x4(%a0) 4847 mov.l 0x14+0x8(%a6),0x8(%a0) 4849 mov.b %d0,STAG(%a6) 4850 mov.l %d0,%d1 4855 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 5016 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0 5022 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1 5032 mov.l (%a0),%d1 # put exp in hi word 5033 mov.w 4(%a0),%d1 # fetch hi(man) 5055 mov.l INT(%a6),%d1 # make a copy of N 5068 mov.l INT(%a6),%d1 5160 mov.l %d1,POSNEG1(%a6) 5199 mov.l ADJN(%a6),%d1 5206 # mov.w &0x0000,XDCARE(%a6) # JUST IN CASE 5209 mov.b &FMOV_OP,%d1 # last inst is MOVE 5237 mov.l &4,ADJN(%a6) 5242 mov.l (%a0),%d1 5243 mov.w 4(%a0),%d1 5267 mov.l INT(%a6),%d1 5277 mov.l INT(%a6),%d1 5293 mov.l %d2,-(%sp) 5294 mov.l %d1,%d2 5305 mov.l (%sp)+,%d2 5309 mov.l &0x3F800000,POSNEG1(%a6) 5382 mov.l %d1,POSNEG1(%a6) 5438 # mov.w &0x0000,XDCARE(%a6) 5445 mov.b &FMOV_OP,%d1 # last inst is MOVE 5454 mov.l %d0,-(%sp) # save d0 5457 mov.l (%sp)+,%d0 # restore d0 5467 mov.l %d2,-(%sp) # save d2 5478 mov.w &0x7ffe,FP_SCR0_EX(%a6) 5479 mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) 5483 mov.w &0x7fdc,FP_SCR1_EX(%a6) 5484 mov.l &0x85a308d3,FP_SCR1_HI(%a6) 5504 mov.w INARG(%a6),%d1 5505 mov.l %d1,%a1 # save a copy of D0 5512 mov.b &0,ENDFLAG(%a6) 5516 mov.b &1,ENDFLAG(%a6) 5525 mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI 5528 mov.l &0xA2F9836E,FP_SCR0_HI(%a6) 5529 mov.l &0x4E44152A,FP_SCR0_LO(%a6) 5530 mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) 5540 mov.l %a1,%d2 5544 mov.l %d2,TWOTO63(%a6) 5550 mov.l %d1,%d2 # d2 = L 5553 mov.w %d2,FP_SCR0_EX(%a6) 5554 mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) 5558 mov.w %d1,FP_SCR1_EX(%a6) 5559 mov.l &0x85A308D3,FP_SCR1_HI(%a6) 5562 mov.b ENDFLAG(%a6),%d1 5597 mov.l (%sp)+,%d2 # restore d2 5600 mov.l ADJN(%a6),%d1 5762 mov.l (%a0),%d1 5763 mov.w 4(%a0),%d1 5884 mov.b &FMOV_OP,%d1 # last inst is MOVE 5898 mov.l %d2,-(%sp) # save d2 5909 mov.w &0x7ffe,FP_SCR0_EX(%a6) 5910 mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) 5914 mov.w &0x7fdc,FP_SCR1_EX(%a6) 5915 mov.l &0x85a308d3,FP_SCR1_HI(%a6) 5935 mov.w INARG(%a6),%d1 5936 mov.l %d1,%a1 # save a copy of D0 5943 mov.b &0,ENDFLAG(%a6) 5947 mov.b &1,ENDFLAG(%a6) 5956 mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI 5959 mov.l &0xA2F9836E,FP_SCR0_HI(%a6) 5960 mov.l &0x4E44152A,FP_SCR0_LO(%a6) 5961 mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) 5971 mov.l %a1,%d2 5975 mov.l %d2,TWOTO63(%a6) 5981 mov.l %d1,%d2 # d2 = L 5984 mov.w %d2,FP_SCR0_EX(%a6) 5985 mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) 5989 mov.w %d1,FP_SCR1_EX(%a6) 5990 mov.l &0x85A308D3,FP_SCR1_HI(%a6) 5993 mov.b ENDFLAG(%a6),%d1 6028 mov.l (%sp)+,%d2 # restore d2 6031 mov.l INT(%a6),%d1 6244 mov.l (%a0),%d1 6245 mov.w 4(%a0),%d1 6283 mov.l &0x00000000,XFRACLO(%a6) # LOCATION OF X IS NOW F 6295 mov.l %d2,-(%sp) # SAVE d2 TEMPORARILY 6296 mov.l %d1,%d2 # THE EXP AND 16 BITS OF X 6305 mov.l (%a1)+,ATANF(%a6) 6306 mov.l (%a1)+,ATANFHI(%a6) 6307 mov.l (%a1)+,ATANFLO(%a6) # ATANF IS NOW ATAN(|F|) 6308 mov.l X(%a6),%d1 # LOAD SIGN AND EXPO. AGAIN 6311 mov.l (%sp)+,%d2 # RESTORE d2 6399 mov.b &FMOV_OP,%d1 # last inst is MOVE 6526 mov.l (%a0),%d1 6527 mov.w 4(%a0),%d1 6567 mov.l (%a0),%d1 6570 mov.l %d1,-(%sp) # push SIGN(X) IN SGL-FMT 6578 mov.b &FMOV_OP,%d1 # last inst is MOVE 6627 mov.l (%a0),%d1 # pack exp w/ upper 16 fraction 6628 mov.w 4(%a0),%d1 6643 mov.l %d0,-(%sp) # save original users fpcr 7105 mov.l (%a0),%d1 # load part of input X 7113 mov.w 4(%a0),%d1 # expo. and partial sig. of |X| 7126 mov.l &0,ADJFLAG(%a6) 7131 mov.l %d1,L_SCR1(%a6) # save N temporarily 7135 mov.l L_SCR1(%a6),%d1 7138 mov.w L2(%pc),L_SCR1(%a6) # prefetch L2, no need in CB 7169 mov.w %d1,SCALE(%a6) # SCALE is 2^(M) in extended 7170 mov.l &0x80000000,SCALE+4(%a6) 7193 mov.l ADJFLAG(%a6),%d1 7202 mov.b &FMUL_OP,%d1 # last inst is MUL 7223 mov.l &1,ADJFLAG(%a6) 7227 mov.l %d1,L_SCR1(%a6) # save N temporarily 7231 mov.l L_SCR1(%a6),%d1 7233 mov.l %d1,L_SCR1(%a6) # save K temporarily 7237 mov.w %d1,ADJSCALE(%a6) # ADJSCALE := 2^(M1) 7238 mov.l &0x80000000,ADJSCALE+4(%a6) 7240 mov.l L_SCR1(%a6),%d1 # D0 is M 7253 mov.l (%a0),-(%sp) 7269 mov.l (%a0),%d1 # load part of input X 7278 mov.w 4(%a0),%d1 # expo. and partial sig. of |X| 7295 mov.l %d1,L_SCR1(%a6) # save N temporarily 7299 mov.l L_SCR1(%a6),%d1 7301 mov.l %d1,L_SCR1(%a6) # save a copy of M 7330 mov.w %d1,SC(%a6) # SC is 2^(M) in extended 7331 mov.l &0x80000000,SC+4(%a6) 7335 mov.l L_SCR1(%a6),%d1 # D0 is M 7344 mov.w %d1,ONEBYSC(%a6) # OnebySc is -2^(-M) 7345 mov.l &0x80000000,ONEBYSC+4(%a6) 7363 mov.l L_SCR1(%a6),%d1 # retrieve M 7405 mov.l &0x80010000,SC(%a6) # SC is -2^(-16382) 7406 mov.l &0x80000000,SC+4(%a6) 7410 mov.b &FADD_OP,%d1 # last inst is ADD 7418 mov.l &0x80010000,SC(%a6) 7419 mov.l &0x80000000,SC+4(%a6) 7423 mov.b &FMUL_OP,%d1 # last inst is MUL 7480 mov.l (%a0),%d1 7517 mov.w SRC_EX(%a0),%d0 # get the exponent 7525 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 7534 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 7539 mov.w SRC_EX(%a0),%d0 # get the exp 7544 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy to tmp loc 7545 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy to tmp loc 7546 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 7552 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 7617 mov.l (%a0),%d1 7618 mov.w 4(%a0),%d1 7628 mov.l %d0,-(%sp) 7635 mov.l (%sp)+,%d0 7641 mov.b &FADD_OP,%d1 # last inst is ADD 7653 mov.l %d0,-(%sp) 7659 mov.l (%sp)+,%d0 7662 mov.b &FMUL_OP,%d1 # last inst is MUL 7729 mov.l (%a0),%d1 7730 mov.w 4(%a0),%d1 7731 mov.l %d1,%a1 # save (compacted) operand 7754 mov.l %a1,%d1 7758 mov.l %d1,-(%sp) 7761 mov.b &FMUL_OP,%d1 # last inst is MUL 7770 mov.l &0,-(%sp) 7771 mov.l &0x80000000,-(%sp) 7772 mov.l %a1,%d1 7775 mov.l %d1,-(%sp) # EXTENDED FMT 7778 mov.l %d0,-(%sp) 7785 mov.l (%sp)+,%d0 7787 mov.b &FMUL_OP,%d1 # last inst is MUL 7855 mov.l (%a0),%d1 7856 mov.w 4(%a0),%d1 7857 mov.l %d1,X(%a6) 7867 mov.l X(%a6),%d1 7868 mov.l %d1,SGN(%a6) 7871 mov.l %d1,X(%a6) 7875 mov.l %d0,-(%sp) 7881 mov.l (%sp)+,%d0 7885 mov.l SGN(%a6),%d1 7904 mov.l X(%a6),%d1 7905 mov.l %d1,SGN(%a6) 7908 mov.l %d1,X(%a6) # Y = 2|X| 7910 mov.l SGN(%a6),%d1 7913 mov.l %d0,-(%sp) 7919 mov.l (%sp)+,%d0 7920 mov.l SGN(%a6),%d1 7927 mov.l SGN(%a6),%d1 7932 mov.b &FADD_OP,%d1 # last inst is ADD 7938 mov.b &FMOV_OP,%d1 # last inst is MOVE 7944 mov.l X(%a6),%d1 8215 mov.l &0x00000000,ADJK(%a6) 8221 mov.l (%a0),%d1 8222 mov.w 4(%a0),%d1 8224 mov.l (%a0),X(%a6) 8225 mov.l 4(%a0),X+4(%a6) 8226 mov.l 8(%a0),X+8(%a6) 8257 mov.l &0x3FFF0000,X(%a6) # X IS NOW Y, I.E. 2^(-K)*X 8258 mov.l XFRAC(%a6),FFRAC(%a6) 8261 mov.l FFRAC(%a6),%d1 # READY TO GET ADDRESS OF 1/F 8269 mov.l &0x3fff0000,F(%a6) 8382 mov.l &-100,ADJK(%a6) # INPUT = 2^(ADJK) * FP0 8390 mov.l (%a0),%d3 # D3 is exponent of smallest norm. # 8391 mov.l 4(%a0),%d4 8392 mov.l 8(%a0),%d5 # (D4,D5) is (Hi_X,Lo_X) 8399 mov.l %d5,%d4 8401 mov.l &32,%d2 8407 mov.l %d3,X(%a6) 8408 mov.l %d4,XFRAC(%a6) 8409 mov.l %d5,XFRAC+4(%a6) 8411 mov.l %d2,ADJK(%a6) 8420 mov.l %d6,%d2 # get k 8422 mov.l %d5,%d7 # a copy of D5 8429 mov.l %d3,X(%a6) 8430 mov.l %d4,XFRAC(%a6) 8431 mov.l %d5,XFRAC+4(%a6) 8433 mov.l %d2,ADJK(%a6) 8447 mov.b &FMOV_OP,%d1 # last inst is MOVE 8453 mov.l &0x00000000,ADJK(%a6) 8457 mov.w XFRAC(%a6),XDCARE(%a6) 8458 mov.l X(%a6),%d1 8494 mov.l XFRAC(%a6),FFRAC(%a6) 8502 mov.l &0x3fff0000,F(%a6) 8505 mov.l FFRAC(%a6),%d1 8520 mov.l &0x3fff0000,F(%a6) 8523 mov.l FFRAC(%a6),%d1 8601 mov.l (%a0),%d1 8602 mov.w 4(%a0),%d1 8616 mov.l (%a0),%d1 8619 mov.l %d1,-(%sp) 8621 mov.l %d0,-(%sp) # save rnd prec,mode 8628 mov.l (%sp)+,%d0 # fetch old prec,mode 8630 mov.b &FMUL_OP,%d1 # last inst is MUL 8743 mov.l (%a0),%d1 8745 mov.l %d0,-(%sp) 8755 mov.l (%a0),%d1 8757 mov.l %d0,-(%sp) 8767 mov.l (%a0),%d1 8770 mov.l 8(%a0),%d1 8773 mov.l 4(%a0),%d1 8778 mov.w (%a0),%d1 8787 mov.l %d0,-(%sp) 8800 mov.l (%a0),%d1 8802 mov.l %d0,-(%sp) 8988 mov.l (%a0),%d1 8989 mov.w 4(%a0),%d1 9008 mov.l %d2,-(%sp) 9011 mov.l INT(%a6),%d1 9012 mov.l %d1,%d2 9017 mov.l %d2,%d1 9030 mov.l (%a1)+,FACT1(%a6) 9031 mov.l (%a1)+,FACT1HI(%a6) 9032 mov.l (%a1)+,FACT1LOW(%a6) 9033 mov.w (%a1)+,FACT2(%a6) 9037 mov.w (%a1)+,FACT2HI(%a6) 9060 mov.l X(%a6),%d1 9075 mov.l (%a0),%d1 9085 mov.l (%a0),%d1 9086 mov.w 4(%a0),%d1 9105 mov.l %d2,-(%sp) 9108 mov.l INT(%a6),%d1 9109 mov.l %d1,%d2 9114 mov.l %d2,%d1 9128 mov.l (%a1)+,FACT1(%a6) 9132 mov.l (%a1)+,FACT1HI(%a6) 9133 mov.l (%a1)+,FACT1LOW(%a6) 9135 mov.w (%a1)+,FACT2(%a6) 9139 mov.w (%a1)+,FACT2HI(%a6) 9185 mov.w %d2,ADJFACT(%a6) # INSERT EXPONENT 9186 mov.l (%sp)+,%d2 9187 mov.l &0x80000000,ADJFACT+4(%a6) 9189 mov.b &FMUL_OP,%d1 # last inst is MUL 9199 mov.l (%a0),%d1 9222 mov.l %d0,-(%sp) # store off ctrl bits for now 9224 mov.w DST_EX(%a1),%d1 # get dst exponent 9228 mov.w SRC_EX(%a0),%d0 # check src bounds 9251 mov.l %d0,-(%sp) # save src for now 9253 mov.w DST_EX(%a1),FP_SCR0_EX(%a6) # make a copy 9254 mov.l DST_HI(%a1),FP_SCR0_HI(%a6) 9255 mov.l DST_LO(%a1),FP_SCR0_LO(%a6) 9274 mov.l &0x80000000,%d1 # load normalized mantissa 9281 mov.l %d1,-(%sp) # insert new high mantissa 9287 mov.l %d1,-(%sp) # insert new low mantissa 9302 mov.l &0x80000000,-(%sp) # insert new high mantissa 9303 mov.l %d0,-(%sp) # insert new lo mantissa 9307 mov.b &FMUL_OP,%d1 # last inst is MUL 9316 mov.l (%sp)+,%d0 # restore ctrl bits 9330 mov.l (%sp)+,%d0 9332 mov.b &FMOV_OP,%d1 # last inst is MOVE 9336 mov.l (%sp)+,%d0 # load control bits into d1 9337 mov.l %a1,%a0 # pass ptr to dst 9421 mov.l %d0,-(%sp) # save ctrl bits 9428 mov.l %d0,-(%sp) # save ctrl bits 9429 mov.b &0x1,Mod_Flag(%a6) 9434 mov.w SRC_EX(%a0),%d3 9435 mov.w %d3,SignY(%a6) 9439 mov.l SRC_HI(%a0),%d4 9440 mov.l SRC_LO(%a0),%d5 # (D3,D4,D5) is |Y| 9445 mov.l &0x00003FFE,%d3 # $3FFD + 1 9450 mov.l %d5,%d4 9465 mov.l %d5,%d7 # a copy of D5 9479 mov.w DST_EX(%a1),%d0 9480 mov.w %d0,SignX(%a6) 9481 mov.w SignY(%a6),%d1 9484 mov.w %d1,SignQ(%a6) # sign(Q) obtained 9486 mov.l DST_HI(%a1),%d1 9487 mov.l DST_LO(%a1),%d2 # (D0,D1,D2) is |X| 9490 mov.l &0x00003FFE,%d0 9495 mov.l %d2,%d1 9510 mov.l %d2,%d7 # a copy of D2 9525 mov.l %d3,L_SCR1(%a6) # save biased exp(Y) 9526 mov.l %d0,-(%sp) # save biased exp(X) 9531 mov.l &0,%a1 # A1 is k; j+k=L, Q=0 9539 mov.l (%sp)+,%d0 # restore d0 9589 mov.l L_SCR1(%a6),%d0 # new biased expo of R 9594 mov.l %d2,%d1 9610 mov.l %d2,%d7 # a copy of D2 9622 mov.w %d0,R(%a6) 9623 mov.l %d1,R_Hi(%a6) 9624 mov.l %d2,R_Lo(%a6) 9625 mov.l L_SCR1(%a6),%d6 9626 mov.w %d6,Y(%a6) 9627 mov.l %d4,Y_Hi(%a6) 9628 mov.l %d5,Y_Lo(%a6) 9630 mov.b &1,Sc_Flag(%a6) 9633 mov.l %d1,R_Hi(%a6) 9634 mov.l %d2,R_Lo(%a6) 9636 mov.w %d0,R(%a6) 9637 mov.l L_SCR1(%a6),%d6 9639 mov.l %d6,L_SCR1(%a6) 9641 mov.w %d6,Y(%a6) 9642 mov.l %d4,Y_Hi(%a6) 9643 mov.l %d5,Y_Lo(%a6) 9651 mov.l L_SCR1(%a6),%d6 # new biased expo(Y) 9674 mov.w SignX(%a6),%d6 9682 mov.w SignQ(%a6),%d6 # D6 is sign(Q) 9683 mov.l &8,%d7 9692 mov.b %d3,FPSR_QBYTE(%a6) # put Q in fpsr 9697 mov.l (%sp)+,%d0 9701 mov.b &FMUL_OP,%d1 # last inst is MUL 9712 mov.b &FMOV_OP,%d1 # last inst is MOVE 9735 mov.l %d3,%d6 9742 mov.w SignX(%a6),%d6 9744 mov.w %d6,SignX(%a6) 9773 mov.w FTEMP_EX(%a0), %d0 # extract exponent 9781 mov.b &NORM, %d0 9792 mov.b &ZERO, %d0 9795 mov.b &DENORM, %d0 9801 mov.b &UNNORM, %d0 9806 mov.l FTEMP_HI(%a0), %d0 9810 mov.b &INF, %d0 9813 mov.b &QNAN, %d0 9986 mov.b %d0,FPSR_CC(%a6) 9997 mov.b %d0,FPSR_CC(%a6) 10033 mov.b %d0,%d1 # fetch rnd prec,mode 10040 mov.w LOCAL_EX(%a0),FP_SCR0_EX(%a6) 10041 mov.l LOCAL_HI(%a0),FP_SCR0_HI(%a6) 10042 mov.l LOCAL_LO(%a0),FP_SCR0_LO(%a6) 10057 mov.l LOCAL_LO(%a0),%d1 # are any of lo 11 bits of 10078 mov.b %d0,FPSR_CC(%a6) 10087 mov.b %d0,FPSR_CC(%a6) 10099 mov.b %d0,FPSR_CC(%a6) 10189 mov.b &z_bmask,FPSR_CC(%a6) 10256 mov.b &nan_bmask,FPSR_CC(%a6) 10259 mov.b &nan_bmask+neg_bmask,FPSR_CC(%a6) 10271 mov.b &nan_bmask,FPSR_CC(%a6) 10274 mov.b &nan_bmask+neg_bmask,FPSR_CC(%a6) 10473 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit 10480 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bits 10506 mov.b &inf_bmask,FPSR_CC(%a6) # set 'INF' ccode bit 10515 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits 10583 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit 10630 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) 10634 mov.b &z_bmask,FPSR_CC(%a6) 10662 mov.b DTAG(%a6),%d1 10674 mov.b DTAG(%a6),%d1 10686 mov.b DTAG(%a6),%d1 10698 mov.b SRC_EX(%a0),%d1 # get src sign 10699 mov.b DST_EX(%a1),%d0 # get dst sign 10702 mov.b %d1,FPSR_QBYTE(%a6) 10710 mov.l %d0,-(%sp) 10711 mov.b SRC_EX(%a0),%d1 # get src sign 10712 mov.b DST_EX(%a1),%d0 # get dst sign 10715 mov.b %d1,FPSR_QBYTE(%a6) 10719 mov.l (%sp)+,%d0 10729 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' code 10737 mov.b DTAG(%a6),%d1 10749 mov.b DTAG(%a6),%d1 10761 mov.b DTAG(%a6),%d1 10777 mov.b DTAG(%a6),%d1 10789 mov.b DTAG(%a6),%d1 10801 mov.b DTAG(%a6),%d1 10811 mov.b DTAG(%a6),%d1 10837 mov.l %d2, -(%sp) # create some temp regs 10838 mov.l %d3, -(%sp) 10840 mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) 10841 mov.l FTEMP_LO(%a0), %d1 # load lo(mantissa) 10853 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 10854 mov.l %d1, FTEMP_LO(%a0) # store new lo(man) 10856 mov.l %d2, %d0 # return shift amount 10858 mov.l (%sp)+, %d3 # restore temp regs 10859 mov.l (%sp)+, %d2 10868 mov.l %d1, FTEMP_HI(%a0) # store hi(man) 10871 mov.l %d2, %d0 # return shift amount 10873 mov.l (%sp)+, %d3 # restore temp regs 10874 mov.l (%sp)+, %d2 10917 mov.w FTEMP_EX(%a0), %d1 # extract exponent 10927 mov.w FTEMP_EX(%a0), %d0 # load old exponent 10930 mov.w %d1, FTEMP_EX(%a0) # insert new exponent 10934 mov.b &NORM, %d0 # return new optype tag 10945 mov.l %d0, FTEMP_HI(%a0) # save new hi(man) 10947 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 10949 mov.l %d0, FTEMP_LO(%a0) # save new lo(man) 10953 mov.b &DENORM, %d0 # return new optype tag 10962 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 10965 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 10970 mov.b &DENORM, %d0 # return new optype tag 10979 mov.b &ZERO, %d0 # fix optype tag
|
/linux-4.1.27/arch/mn10300/kernel/ |
H A D | head.S | 43 mov (CPUID),d3 53 mov 0x1,a0 55 mov a0,a1 68 mov d0,a3 71 mov swapper_pg_dir,d0 72 mov d0,(PTBR) 77 mov MMUCTR_IIV|MMUCTR_DIV,d0 78 mov d0,(MMUCTR) 80 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0 82 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0 84 mov d0,(MMUCTR) 90 mov CONFIG_INTERRUPT_VECTOR_BASE,d0 91 mov d0,(TBR) 95 mov ECHCTR,a0 97 mov d0,(a0) 99 mov CHCTR,a0 102 mov CHCTR_ICINV|CHCTR_DCINV,d0 105 mov (a0),d0 112 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 114 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0 117 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 128 mov __bss_start,a0 129 mov __bss_stop,a1 134 mov d0,(a0) 145 mov redboot_command_line,a0 146 mov a0,a1 156 mov redboot_platform_name,a0 157 mov a0,a1 159 mov d2,a3 171 mov init_thread_union+THREAD_SIZE-12,sp 173 mov 0xea01eaea,d0 174 mov d0,(4,sp) # EPSW save area 175 mov 0xea02eaea,d0 176 mov d0,(8,sp) # PC save area 178 mov 0xeb0060ed,d0 179 mov d0,mdr 180 mov 0xeb0061ed,d0 181 mov d0,mdrq 182 mov 0xeb0062ed,d0 183 mov d0,mcrh 184 mov 0xeb0063ed,d0 185 mov d0,mcrl 186 mov 0xeb0064ed,d0 187 mov d0,mcvf 188 mov 0xed0065ed,a3 189 mov a3,usp 191 mov 0xed00e0ed,e0 192 mov 0xed00e1ed,e1 193 mov 0xed00e2ed,e2 194 mov 0xed00e3ed,e3 195 mov 0xed00e4ed,e4 196 mov 0xed00e5ed,e5 197 mov 0xed00e6ed,e6 198 mov 0xed00e7ed,e7 200 mov 0xed00d0ed,d0 201 mov 0xed00d1ed,d1 202 mov 0xed00d2ed,d2 203 mov 0xed00d3ed,d3 204 mov 0xed00a0ed,a0 205 mov 0xed00a1ed,a1 206 mov 0xed00a2ed,a2 207 mov 0,a3 211 mov 0xffffffff,d0 212 mov d0,(REG_ORIG_D0,fp) 215 mov 0xfb0060ed,d0 216 mov d0,mdr 217 mov 0xfb0061ed,d0 218 mov d0,mdrq 219 mov 0xfb0062ed,d0 220 mov d0,mcrh 221 mov 0xfb0063ed,d0 222 mov d0,mcrl 223 mov 0xfb0064ed,d0 224 mov d0,mcvf 225 mov 0xfd0065ed,a0 226 mov a0,usp 228 mov 0xfd00e0ed,e0 229 mov 0xfd00e1ed,e1 230 mov 0xfd00e2ed,e2 231 mov 0xfd00e3ed,e3 232 mov 0xfd00e4ed,e4 233 mov 0xfd00e5ed,e5 234 mov 0xfd00e6ed,e6 235 mov 0xfd00e7ed,e7 237 mov 0xfd00d0ed,d0 238 mov 0xfd00d1ed,d1 239 mov 0xfd00d2ed,d2 240 mov 0xfd00d3ed,d3 241 mov 0xfd00a0ed,a0 242 mov 0xfd00a1ed,a1 243 mov 0xfd00a2ed,a2 247 mov init_task,e2 256 mov cpu_boot_map,a0 257 mov 0x1,d0 258 mov d0,(a0) 261 mov 0x1,d2 # CPU ID 264 mov d2,a0 276 mov DELAY_TIME_BOOT_IPI,d0 279 mov cpu_boot_map,a0 280 mov (a0),d0 313 mov swapper_pg_dir,d0 314 mov d0,(PTBR) 319 mov MMUCTR_IIV|MMUCTR_DIV,d0 320 mov d0,(MMUCTR) 322 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0 324 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0 326 mov d0,(MMUCTR) 334 mov CONFIG_INTERRUPT_VECTOR_BASE,d0 335 mov d0,(TBR) 338 mov ECHCTR,a0 340 mov d0,(a0) 341 mov CHCTR,a0 344 mov CHCTR_ICINV|CHCTR_DCINV,d0 347 mov (a0),d0 354 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 356 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0 359 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 371 mov CONFIG_INTERRUPT_VECTOR_BASE + CONFIG_BOOT_STACK_OFFSET,a0 372 mov (CPUID),d0 376 mov a0,sp 382 mov (CPUID),d0 383 mov 0x1,d1 385 mov cpu_boot_map,a0 395 mov (CHCTR),d0 402 mov CPUM_SLEEP,d0
|
H A D | switch_to.S | 35 mov (44,sp),d2 37 mov d0,a0 38 mov d1,a1 41 mov __switch_back,d0 42 mov sp,a2 43 mov a2,(THREAD_SP,a0) 44 mov a3,(THREAD_A3,a0) 51 mov d0,(THREAD_PC,a0) 53 mov (THREAD_A3,a1),a3 54 mov (THREAD_SP,a1),a2 57 mov a2,sp 61 mov a2,(__current_ti) 62 mov (TI_task,a2),a2 63 mov a2,(__current) 65 mov a2,e2 68 mov (THREAD_PC,a1),a2 69 mov d2,d0 # for ret_from_fork 70 mov d0,a0 # for __switch_to 88 mov a0,e4 89 mov a1,e5 96 mov (kgdb_sstep_bp_addr),a2 102 mov a2,d0 103 mov a2,d1 110 mov (kgdb_sstep_bp_addr+4),a2 116 mov a2,d0 117 mov a2,d1 124 mov __switch_back__reinstall_sstep_bp,d0 125 mov e4,a0 126 mov e5,a1 138 mov a0,e4 # save the return value 139 mov 0xff,d3 142 mov (kgdb_sstep_bp_addr),a2 149 mov a2,d0 150 mov a2,d1 157 mov (kgdb_sstep_bp_addr+4),a2 164 mov a2,d0 165 mov a2,d1 171 mov d3,(kgdb_single_step) 174 mov e4,a0 175 mov a0,d0
|
H A D | gdb-low.S | 35 mov d0,a0 36 mov d1,a1 47 mov d0,a0 48 mov d1,a1 59 mov d0,a0 60 mov d1,a1 63 mov (a0),d1 65 mov d1,(a1) 78 mov d0,a0 79 mov d1,a1 89 mov d0,a0 90 mov d1,a1 100 mov d0,a0 101 mov d1,a1 104 mov a0,(a1)
|
H A D | mn10300-serial-low.S | 52 mov (a2+),a3 53 mov (__iobase,a3),e2 54 mov (a2),a2 69 mov (__rx_icr,a3),e3 70 mov GxICR_DETECT,d2 74 mov (__rx_inp,a3),d3 75 mov d3,a2 78 mov (__rx_outp,a3),d2 82 mov (__rx_buffer,a3),d2 88 mov d3,(__rx_inp,a3) 92 mov (__tm_icr,a3),a2 93 mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2 116 mov (__tx_icr,a3),e3 117 mov GxICR_DETECT,d2 133 mov (__uart_state,a3),a2 # see if the TTY Tx queue has anything in it 134 mov (__xmit_tail,a2),d3 135 mov (__xmit_head,a2),d2 139 mov (__xmit_buffer,a2),d2 # get a char from the buffer and 146 mov (__xmit_head,a2),d2 147 mov d3,(__xmit_tail,a2) 157 mov (__tm_icr,a3),a2 158 mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2 167 mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2 181 mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2
|
H A D | gdb-io-serial-low.S | 41 mov (gdbstub_rx_inp),a3 43 mov a3,a2 46 mov (gdbstub_rx_outp),d3 56 mov a3,(gdbstub_rx_inp) 60 mov GxICR_DETECT,d2 77 mov 0xffffffff,d0 78 mov d0,(REG_ORIG_D0,fp) 79 mov 0x280,d1 81 mov fp,d0
|
H A D | gdb-io-ttysm-low.S | 37 mov (gdbstub_rx_inp),a3 39 mov a3,a2 42 mov (gdbstub_rx_outp),d3 52 mov a3,(gdbstub_rx_inp) 56 mov GxICR_DETECT,d2 79 mov 0xffffffff,d0 80 mov d0,(REG_ORIG_D0,fp) 81 mov 0x280,d1 83 mov fp,d0
|
H A D | profile-low.S | 37 mov (12,sp),d2 42 mov (prof_buffer),a2 48 mov (16,sp),d2 50 mov (prof_shift),d3 52 mov (prof_len),d3 59 mov (a2,d2),d3 61 mov d3,(a2,d2) 63 mov GxICR_DETECT,d2 71 mov d3,d2
|
H A D | smp-low.S | 33 mov d0,(sp) 44 mov (sp),d0 59 mov (sp),d0 65 mov GxICR_DETECT,d2 83 mov (sp),d0 87 mov (CPUID),a0 91 mov (start_stack,a0),a0 92 mov a0,sp
|
H A D | entry.S | 55 mov d0,(REG_D0,fp) 60 mov (REG_D0,fp),d0 61 mov (REG_A0,fp),a0 65 mov d0,(REG_D0,fp) 76 mov d0,(REG_ORIG_D0,fp) 85 mov (REG_A0,fp),d0 86 mov (sys_call_table,a1),a0 88 mov d0,(REG_D0,fp) 93 mov (TI_flags,a2),d2 107 mov (REG_EPSW,fp),d0 115 mov fp,d0 133 mov (TI_flags,a2),d2 143 mov fp,d0 144 mov d2,d1 150 mov -ENOSYS,d0 151 mov d0,(REG_D0,fp) 152 mov fp,d0 154 mov (REG_D1,fp),d1 160 mov -ENOSYS,d0 161 mov d0,(REG_D0,fp) 171 mov (REG_EPSW,fp),d0 # need to deliver signals before 179 mov (TI_preempt_count,a2),d0 # non-zero preempt_count ? 186 mov (REG_EPSW,fp),d0 208 mov 0xffffffff,d0 209 mov d0,(REG_ORIG_D0,fp) 211 mov fp,d0 229 mov a0,(__df_stack-4) # PC as was 230 mov d0,(__df_stack-8) # EPSW as was 232 mov 0xaa55aa55,d0 233 mov d0,(__df_stack-12) # no ORIG_D0 234 mov sp,a0 # save corrupted SP 235 mov __df_stack-12,sp # emergency supervisor stack 237 mov a0,(REG_A0,fp) # save corrupted SP as A0 (which got 239 mov fp,d0 252 mov d0,(sp) 254 mov (MMUCTR),d0 255 mov d0,(MMUCTR) 257 mov (BCBERR),d0 # what 262 mov (BCBEAR),d1 # destination of erroneous access 264 mov (REG_ORIG_D0,fp),d2 265 mov d2,(REG_D0,fp) 266 mov -1,d2 267 mov d2,(REG_ORIG_D0,fp) 270 mov fp,(12,sp) # frame pointer 285 mov d0,(sp) 286 mov (TBR),d0 290 mov d0,(sp) # save d0(TBR) 299 mov GxICR_DETECT,d0 # clear NMI request 304 mov (sp),d0 # restore d0 316 mov GxICR_DETECT,d0 # clear NMI 321 mov (sp),d0 323 mov fp,d0 # arg 0: stacked register file 324 mov a2,d1 # arg 1: exception number 330 mov (sp),d0 # restore TBR to d0 343 mov d0,(sp) 345 mov (MMUCTR),d0 346 mov d0,(MMUCTR) 350 mov (TBR),d0 365 mov (REG_D0,fp),a2 # get the exception number 366 mov (REG_ORIG_D0,fp),d0 367 mov d0,(REG_D0,fp) 368 mov -1,d0 369 mov d0,(REG_ORIG_D0,fp) 381 mov fp,d0 382 mov a2,d1 388 mov fp,d0 # arg 0: stacked register file 389 mov a2,d1 # arg 1: exception number 392 mov (exception_table,a2),a2 419 mov d1,(d0) 420 mov 4,d1
|
H A D | fpu-low.S | 88 mov \dreg,(\areg) 124 mov (\areg),\dreg 137 mov epsw,d0 151 mov d0,epsw 166 mov epsw,d1 173 mov d0,a0 180 mov d1,epsw 200 mov sp,a1 201 mov (a1),d1 /* get epsw of user context */ 203 mov (TI_task,a1),a2 /* a2: (task_struct *tsk) */ 208 mov d1,(sp) 209 mov (TASK_THREAD+THREAD_FPU_FLAGS,a2),d1 212 mov d1,(TASK_THREAD+THREAD_FPU_FLAGS,a2) 214 mov (fpu_state_owner),a0 218 mov (TASK_THREAD+THREAD_UREGS,a0),a1 222 mov (REG_EPSW,a1),d0 224 mov d0,(REG_EPSW,a1) 227 mov a2,(fpu_state_owner) 249 mov -1,d0 250 mov d0,(REG_ORIG_D0,fp) 254 mov fp,d0
|
H A D | mn10300-watchdog-low.S | 35 mov 0xffffffff,d0 36 mov d0,(REG_ORIG_D0,fp) 38 mov fp,d0 58 mov watchdog_alert_counter, a0 60 mov d0, (a0+)
|
H A D | fpu-nofpu-low.S | 30 mov -1,d0 31 mov d0,(REG_ORIG_D0,fp) 35 mov fp,d0
|
/linux-4.1.27/arch/sh/boot/compressed/ |
H A D | head_32.S | 15 mov.l init_sr, r1 20 mov.l 1f, r2 24 mov.l bss_start_addr, r0 25 mov #0xffffffe0, r1 27 mov.l text_start_addr, r3 28 mov r0, r1 31 mov.l @r1, r4 32 mov.l @(4,r1), r5 33 mov.l @(8,r1), r6 34 mov.l @(12,r1), r7 35 mov.l @(16,r1), r8 36 mov.l @(20,r1), r9 37 mov.l @(24,r1), r10 38 mov.l @(28,r1), r11 39 mov.l r4, @r0 40 mov.l r5, @(4,r0) 41 mov.l r6, @(8,r0) 42 mov.l r7, @(12,r0) 43 mov.l r8, @(16,r0) 44 mov.l r9, @(20,r0) 45 mov.l r10, @(24,r0) 46 mov.l r11, @(28,r0) 54 mov.l 2f, r0 66 mov.l end_addr, r1 67 mov.l bss_start_addr, r2 68 mov #0, r0 70 mov.l r0, @-r1 75 mov.l init_stack_addr, r0 76 mov.l @r0, r15 79 mov.l decompress_kernel_addr, r0 84 mov.l kernel_start_addr, r0
|
/linux-4.1.27/arch/sh/kernel/cpu/sh3/ |
H A D | swsusp.S | 27 mov.l 1f, r15 28 mov.l 2f, r4 29 mov.l @r4, r4 32 mov r4, r0 36 mov.l @(PBE_ADDRESS, r4), r2 37 mov.l @(PBE_ORIG_ADDRESS, r4), r5 39 mov #(PAGE_SIZE >> 10), r3 44 mov.l @r2+,r1 /* 16n+0 */ 45 mov.l r1,@r5 47 mov.l @r2+,r1 /* 16n+4 */ 48 mov.l r1,@r5 50 mov.l @r2+,r1 /* 16n+8 */ 51 mov.l r1,@r5 53 mov.l @r2+,r1 /* 16n+12 */ 54 mov.l r1,@r5 59 mov.l @(PBE_NEXT, r4), r4 63 mov.l 3f, r8 64 mov.l 4f, r5 72 mov.l @r15+, r0 73 mov.l @r15+, r1 74 mov.l @r15+, r2 75 mov.l @r15+, r3 76 mov.l @r15+, r4 77 mov.l @r15+, r5 78 mov.l @r15+, r6 79 mov.l @r15+, r7 98 mov r15, r2 ! save sp in r2 99 mov r8, r5 ! save r8 in r5 102 mov.l 1f, r1 104 mov.l 5f, r15 ! use swsusp_arch_regs_cpu0 as stack 105 mov.l 6f, r3 109 mov.l 2f, r3 ! get new SR value for bank1 110 mov #0, r4 111 mov.l 7f, r1 117 mov.l 3f, k4 ! SR bits to clear in k4 118 mov.l 8f, k1 123 mov r2, r15 ! restore old sp 124 mov r5, r8 ! restore old r8 128 mov.l 4f, r0 133 mov r2, r15 ! restore old sp 134 mov r5, r8 ! restore old r8 137 mov #0, r0
|
H A D | entry.S | 113 mov #0, r5 118 mov #FAULT_CODE_WRITE, r5 123 mov #FAULT_CODE_INITIAL, r5 128 mov #FAULT_CODE_PROT, r5 133 mov #(FAULT_CODE_PROT | FAULT_CODE_WRITE), r5 136 mov.l 1f, r0 137 mov r5, r8 138 mov.l @r0, r6 139 mov.l 2f, r0 142 mov r15, r4 150 mov r8, r5 152 mov.l 1f, r0 153 mov.l @r0, r6 155 mov.l 3f, r0 156 mov.l 4f, r1 157 mov r15, r4 170 mov #0,r5 ! writeaccess = 0 175 mov #1,r5 ! writeaccess = 1 179 mov.l 1f, r0 180 mov.l @r0, r6 ! address 181 mov.l 2f, r0 183 mov r15, r4 ! regs 193 mov.l 1f, r8 198 mov k4, r15 200 mov.l 2f, k0 201 mov.l @k0, k0 222 mov.l @r15+, r0 223 mov.l @r15+, r1 224 mov.l @r15+, r2 225 mov.l @r15+, r3 226 mov.l @r15+, r4 227 mov.l @r15+, r5 228 mov.l @r15+, r6 229 mov.l @r15+, r7 235 mov.l @r15+, r8 236 mov.l @r15+, r9 237 mov.l @r15+, r10 238 mov.l @r15+, r11 239 mov.l @r15+, r12 240 mov.l @r15+, r13 241 mov.l @r15+, r14 242 mov.l @r15+, k4 ! original stack pointer 244 mov.l @r15+, k2 ! original PR 245 mov.l @r15+, k3 ! original SR 253 mov.l 7f, r8 260 mov k3, k2 ! original SR value 261 mov #0xfffffff0, k1 266 mov k3, k0 ! Calculate IMASK-bits 272 mov g_imask, k0 277 mov k4, r15 313 mov r15, k0 327 2: mov k1, r15 ! SP = r1 335 mov r15, k0 ! save original stack to k0 337 mov #(THREAD_SIZE >> 10), k1 341 mov k1, r15 ! change to kernel stack 362 mov.l 5f, k2 ! vector register address 363 mov.l 1f, k4 ! SR bits to clear in k4 365 mov.l @k2, k2 ! read out vector and keep in k2 371 mov.l 7f, r9 ! fetch return address 373 mov.l 6f, r10 376 mov.l @(r0, r10), r10 394 mov #-1, r1 395 mov.l k1, @-r15 ! set TRA (default: -1) 400 mov.l k3, @-r15 ! original pr in k3 403 mov.l k0, @-r15 ! original stack pointer in k0 404 mov.l r14, @-r15 405 mov.l r13, @-r15 406 mov.l r12, @-r15 407 mov.l r11, @-r15 408 mov.l r10, @-r15 409 mov.l r9, @-r15 410 mov.l r8, @-r15 412 mov.l 0f, k3 ! SR bits to set in k3 428 mov.l r7, @-r15 429 mov.l r6, @-r15 430 mov.l r5, @-r15 431 mov.l r4, @-r15 432 mov.l r3, @-r15 433 mov.l r2, @-r15 434 mov.l r1, @-r15 436 mov.l r0, @-r15 451 mov.l 1f, k4 ! SR bits to clear in k4 453 mov #-1, k2 ! default vector kept in k2 466 mov.l 4f, r9 ! fetch return address 468 mov.l 2f, r4 469 mov.l 3f, r9 470 mov.l @r4, r4 ! pass INTEVT vector as arg0 474 mov r4, r0 ! save vector->jmp table offset for later 491 mov.l 6f, r9 492 mov.l @(r0, r9), r9 494 mov r15, r8 ! trap handlers take saved regs in r8 498 mov r15, r5 ! pass saved registers as arg1
|
/linux-4.1.27/arch/mn10300/lib/ |
H A D | memcpy.S | 25 mov d0,(12,sp) 26 mov d1,(16,sp) 27 mov (20,sp),d2 # count 28 mov d0,a0 # dst 29 mov d1,a1 # src 30 mov d0,e3 # the return value 47 mov +32,d3 50 mov (a1+),d0 51 mov (a1+),d1 52 mov (a1+),e0 53 mov (a1+),e1 54 mov (a1+),e4 55 mov (a1+),e5 56 mov (a1+),e6 57 mov (a1+),e7 58 mov d0,(a0+) 59 mov d1,(a0+) 60 mov e0,(a0+) 61 mov e1,(a0+) 62 mov e4,(a0+) 63 mov e5,(a0+) 64 mov e6,(a0+) 65 mov e7,(a0+) 78 mov (a1+),d0 79 mov (a1+),d1 80 mov (a1+),e0 81 mov (a1+),e1 82 mov d0,(a0+) 83 mov d1,(a0+) 84 mov e0,(a0+) 85 mov e1,(a0+) 94 mov (a1+),d0 95 mov d0,(a0+) 97 mov (a1+),d0 98 mov d0,(a0+) 100 mov (a1+),d0 101 mov d0,(a0+) 107 mov (20,sp),d1 115 mov e3,a0 121 mov +1,d3 131 mov e3,a0
|
H A D | memmove.S | 31 mov d0,(12,sp) 32 mov d1,(16,sp) 33 mov (20,sp),d2 # count 36 mov d0,e3 # the return value 53 mov +32,d3 56 mov (a1),d0 58 mov d0,(a0) 59 mov (a1),d1 61 mov d1,(a0) 63 mov (a1),d0 65 mov d0,(a0) 66 mov (a1),d1 68 mov d1,(a0) 70 mov (a1),d0 72 mov d0,(a0) 73 mov (a1),d1 75 mov d1,(a0) 77 mov (a1),d0 79 mov d0,(a0) 80 mov (a1),d1 82 mov d1,(a0) 94 mov (a1),d0 96 mov d0,(a0) 97 mov (a1),d1 99 mov d1,(a0) 100 mov (a1),e0 102 mov e0,(a0) 103 mov (a1),e1 105 mov e1,(a0) 114 mov (a1),d0 116 mov d0,(a0) 118 mov (a1),d0 120 mov d0,(a0) 122 mov (a1),d0 124 mov d0,(a0) 136 mov e3,a0 143 mov +1,d3 153 mov e3,a0
|
H A D | memset.S | 25 mov d0,(12,sp) 26 mov d1,(16,sp) 27 mov (20,sp),d2 # count 28 mov d0,a0 # dst 29 mov d0,e3 # the return value 50 mov +32,d3 53 mov d1,(a0+) 54 mov d1,(a0+) 55 mov d1,(a0+) 56 mov d1,(a0+) 57 mov d1,(a0+) 58 mov d1,(a0+) 59 mov d1,(a0+) 60 mov d1,(a0+) 72 mov d1,(a0+) 73 mov d1,(a0+) 74 mov d1,(a0+) 75 mov d1,(a0+) 84 mov d1,(a0+) 86 mov d1,(a0+) 88 mov d1,(a0+) 94 mov (20,sp),d1 102 mov e3,a0 108 mov +1,d3 117 mov e3,a0
|
H A D | do_csum.S | 25 mov d1,d2 # count 26 mov d0,a0 # buff 27 mov a0,a1 62 mov +32,d3 65 mov (a0+),d0 66 mov (a0+),e0 67 mov (a0+),e1 68 mov (a0+),e3 73 mov (a0+),d0 74 mov (a0+),e0 75 mov (a0+),e1 76 mov (a0+),e3 93 mov (a0+),d0 94 mov (a0+),e0 95 mov (a0+),e1 96 mov (a0+),e3 113 mov (a0+),d0 117 mov (a0+),d0 121 mov (a0+),d0 142 mov +0xffff0000,d0
|
H A D | __ucmpdi2.S | 27 mov (12,sp),a0 # b.lsw 28 mov (16,sp),a1 # b.msw 33 mov +1,d0
|
/linux-4.1.27/arch/sh/boot/romimage/ |
H A D | head.S | 17 mov.l empty_zero_page_dst, r4 18 mov.l empty_zero_page_dst_adj, r5 20 mov.l bytes_to_load, r5 21 mov.l loader_function, r7 23 mov r4, r15 25 mov.l empty_zero_page_dst, r4 26 mov.l empty_zero_page_dst_adj, r5 28 mov.l loaded_code_offs, r5 47 mov.l extra_data_size, r1 49 mov.l empty_zero_page_dst, r1 50 mov #(PAGE_SHIFT - 4), r4 51 mov #1, r3 55 mov.l @r0, r4 56 mov.l @(4, r0), r5 57 mov.l @(8, r0), r6 58 mov.l @(12, r0), r7 60 mov.l r4, @r1 61 mov.l r5, @(4, r1) 62 mov.l r6, @(8, r1) 63 mov.l r7, @(12, r1) 69 mov #PAGE_SHIFT, r4 70 mov #1, r1 74 mov.l extra_data_size, r1
|
/linux-4.1.27/arch/sh/include/asm/ |
H A D | bitops-grb.h | 16 " mov r15, r1 \n\t" /* r1 = saved sp */ set_bit() 17 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ set_bit() 18 " mov.l @%1, %0 \n\t" /* load old value */ set_bit() 20 " mov.l %0, @%1 \n\t" /* store new value */ set_bit() 21 "1: mov r1, r15 \n\t" /* LOGOUT */ set_bit() 39 " mov r15, r1 \n\t" /* r1 = saved sp */ clear_bit() 40 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ clear_bit() 41 " mov.l @%1, %0 \n\t" /* load old value */ clear_bit() 43 " mov.l %0, @%1 \n\t" /* store new value */ clear_bit() 44 "1: mov r1, r15 \n\t" /* LOGOUT */ clear_bit() 62 " mov r15, r1 \n\t" /* r1 = saved sp */ change_bit() 63 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ change_bit() 64 " mov.l @%1, %0 \n\t" /* load old value */ change_bit() 66 " mov.l %0, @%1 \n\t" /* store new value */ change_bit() 67 "1: mov r1, r15 \n\t" /* LOGOUT */ change_bit() 86 " mov r15, r1 \n\t" /* r1 = saved sp */ test_and_set_bit() 87 " mov #-14, r15 \n\t" /* LOGIN: r15 = size */ test_and_set_bit() 88 " mov.l @%2, %0 \n\t" /* load old value */ test_and_set_bit() 89 " mov %0, %1 \n\t" test_and_set_bit() 91 " mov #-1, %1 \n\t" /* retvat = -1 */ test_and_set_bit() 94 " mov.l %0, @%2 \n\t" /* store new value */ test_and_set_bit() 95 "1: mov r1, r15 \n\t" /* LOGOUT */ test_and_set_bit() 119 " mov r15, r1 \n\t" /* r1 = saved sp */ test_and_clear_bit() 120 " mov #-14, r15 \n\t" /* LOGIN */ test_and_clear_bit() 121 " mov.l @%2, %0 \n\t" /* load old value */ test_and_clear_bit() 122 " mov %0, %1 \n\t" /* %1 = *a */ test_and_clear_bit() 124 " mov #-1, %1 \n\t" /* retvat = -1 */ test_and_clear_bit() 127 " mov.l %0, @%2 \n\t" /* store new value */ test_and_clear_bit() 128 "1: mov r1, r15 \n\t" /* LOGOUT */ test_and_clear_bit() 151 " mov r15, r1 \n\t" /* r1 = saved sp */ test_and_change_bit() 152 " mov #-14, r15 \n\t" /* LOGIN */ test_and_change_bit() 153 " mov.l @%2, %0 \n\t" /* load old value */ test_and_change_bit() 154 " mov %0, %1 \n\t" /* %1 = *a */ test_and_change_bit() 156 " mov #-1, %1 \n\t" /* retvat = -1 */ test_and_change_bit() 159 " mov.l %0, @%2 \n\t" /* store new value */ test_and_change_bit() 160 "1: mov r1, r15 \n\t" /* LOGOUT */ test_and_change_bit()
|
H A D | atomic-grb.h | 12 " mov r15, r1 \n\t" /* r1 = saved sp */ \ 13 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ \ 14 " mov.l @%1, %0 \n\t" /* load old value */ \ 16 " mov.l %0, @%1 \n\t" /* store new value */ \ 17 "1: mov r1, r15 \n\t" /* LOGOUT */ \ 32 " mov r15, r1 \n\t" /* r1 = saved sp */ \ 33 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ \ 34 " mov.l @%1, %0 \n\t" /* load old value */ \ 36 " mov.l %0, @%1 \n\t" /* store new value */ \ 37 "1: mov r1, r15 \n\t" /* LOGOUT */ \ 63 " mov r15, r1 \n\t" /* r1 = saved sp */ atomic_clear_mask() 64 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ atomic_clear_mask() 65 " mov.l @%1, %0 \n\t" /* load old value */ atomic_clear_mask() 67 " mov.l %0, @%1 \n\t" /* store new value */ atomic_clear_mask() 68 "1: mov r1, r15 \n\t" /* LOGOUT */ atomic_clear_mask() 82 " mov r15, r1 \n\t" /* r1 = saved sp */ atomic_set_mask() 83 " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ atomic_set_mask() 84 " mov.l @%1, %0 \n\t" /* load old value */ atomic_set_mask() 86 " mov.l %0, @%1 \n\t" /* store new value */ atomic_set_mask() 87 "1: mov r1, r15 \n\t" /* LOGOUT */ atomic_set_mask()
|
H A D | romimage-macros.h | 10 mov.l 1f, r1 11 mov.l 2f, r0 12 mov.l r0, @r1 23 mov.l 1f, r1 24 mov.l 2f, r0 25 mov.w r0, @r1 36 mov.l 1f, r1 37 mov.l 2f, r0 38 mov.b r0, @r1 49 mov.l 2f, r3 64 mov.l 1f, r1 65 mov.l @r1, r0
|
H A D | cmpxchg-grb.h | 12 " mov r15, r1 \n\t" /* r1 = saved sp */ xchg_u32() 13 " mov #-4, r15 \n\t" /* LOGIN */ xchg_u32() 14 " mov.l @%1, %0 \n\t" /* load old value */ xchg_u32() 15 " mov.l %2, @%1 \n\t" /* store new value */ xchg_u32() 16 "1: mov r1, r15 \n\t" /* LOGOUT */ xchg_u32() 33 " mov r15, r1 \n\t" /* r1 = saved sp */ xchg_u8() 34 " mov #-6, r15 \n\t" /* LOGIN */ xchg_u8() 35 " mov.b @%1, %0 \n\t" /* load old value */ xchg_u8() 37 " mov.b %2, @%1 \n\t" /* store new value */ xchg_u8() 38 "1: mov r1, r15 \n\t" /* LOGOUT */ xchg_u8() 57 " mov r15, r1 \n\t" /* r1 = saved sp */ __cmpxchg_u32() 58 " mov #-8, r15 \n\t" /* LOGIN */ __cmpxchg_u32() 59 " mov.l @%3, %0 \n\t" /* load old value */ __cmpxchg_u32() 62 " mov.l %2, @%3 \n\t" /* store new value */ __cmpxchg_u32() 63 "1: mov r1, r15 \n\t" /* LOGOUT */ __cmpxchg_u32()
|
H A D | cmpxchg-llsc.h | 12 "mov %0, %1 \n\t" xchg_u32() 13 "mov %3, %0 \n\t" xchg_u32() 33 "mov %0, %1 \n\t" xchg_u8() 34 "mov %3, %0 \n\t" xchg_u8() 55 "mov %0, %1 \n\t" __cmpxchg_u32() 58 "mov %4, %0 \n\t" __cmpxchg_u32()
|
H A D | uaccess_32.h | 39 "mov." insn " %2, %1\n\t" \ 43 "mov #0, %1\n\t" \ 44 "mov.l 4f, %0\n\t" \ 46 " mov %3, %0\n\t" \ 59 "mov." insn " %1, %0\n\t" \ 94 "mov." insn " %1, %2\n\t" \ 98 "mov.l 4f, %0\n\t" \ 100 " mov %3, %0\n\t" \ 117 "mov." insn " %0, %1\n\t" \ 130 "mov.l %R1,%2\n\t" \ 131 "mov.l %S1,%T2\n\t" \ 135 "mov.l 4f,%0\n\t" \ 137 " mov %3,%0\n\t" \ 152 "mov.l %S1,%2\n\t" \ 153 "mov.l %R1,%T2\n\t" \ 157 "mov.l 4f,%0\n\t" \ 159 " mov %3,%0\n\t" \
|
H A D | kexec.h | 39 __asm__ __volatile__ ("mov r0, %0" : "=r" (newregs->regs[0])); crash_setup_regs() 40 __asm__ __volatile__ ("mov r1, %0" : "=r" (newregs->regs[1])); crash_setup_regs() 41 __asm__ __volatile__ ("mov r2, %0" : "=r" (newregs->regs[2])); crash_setup_regs() 42 __asm__ __volatile__ ("mov r3, %0" : "=r" (newregs->regs[3])); crash_setup_regs() 43 __asm__ __volatile__ ("mov r4, %0" : "=r" (newregs->regs[4])); crash_setup_regs() 44 __asm__ __volatile__ ("mov r5, %0" : "=r" (newregs->regs[5])); crash_setup_regs() 45 __asm__ __volatile__ ("mov r6, %0" : "=r" (newregs->regs[6])); crash_setup_regs() 46 __asm__ __volatile__ ("mov r7, %0" : "=r" (newregs->regs[7])); crash_setup_regs() 47 __asm__ __volatile__ ("mov r8, %0" : "=r" (newregs->regs[8])); crash_setup_regs() 48 __asm__ __volatile__ ("mov r9, %0" : "=r" (newregs->regs[9])); crash_setup_regs() 49 __asm__ __volatile__ ("mov r10, %0" : "=r" (newregs->regs[10])); crash_setup_regs() 50 __asm__ __volatile__ ("mov r11, %0" : "=r" (newregs->regs[11])); crash_setup_regs() 51 __asm__ __volatile__ ("mov r12, %0" : "=r" (newregs->regs[12])); crash_setup_regs() 52 __asm__ __volatile__ ("mov r13, %0" : "=r" (newregs->regs[13])); crash_setup_regs() 53 __asm__ __volatile__ ("mov r14, %0" : "=r" (newregs->regs[14])); crash_setup_regs() 54 __asm__ __volatile__ ("mov r15, %0" : "=r" (newregs->regs[15])); crash_setup_regs()
|
H A D | string_32.h | 18 "mov.b @%1+, %2\n\t" strcpy() 19 "mov.b %2, @%0\n\t" strcpy() 41 "mov.b @%1+, %2\n\t" strncpy() 42 "mov.b %2, @%0\n\t" strncpy() 63 "mov.b @%1+, %3\n" strcmp() 65 "mov.b @%0+, %2\n\t" strcmp() 70 " mov.b @%1+, %3\n\t" strcmp() 72 "mov.b @%1, %3\n\t" strcmp() 92 "mov.b @%1+, %3\n" strncmp() 94 "mov.b @%0+, %2\n\t" strncmp() 101 " mov.b @%1+, %3\n\t" strncmp() 103 "mov.b @%1, %3\n" strncmp()
|
H A D | switch_to_32.h | 93 "mov.l r8, @-r15\n\t" \ 94 "mov.l r9, @-r15\n\t" \ 95 "mov.l r10, @-r15\n\t" \ 96 "mov.l r11, @-r15\n\t" \ 97 "mov.l r12, @-r15\n\t" \ 98 "mov.l r13, @-r15\n\t" \ 99 "mov.l r14, @-r15\n\t" \ 100 "mov.l r15, @r1\t! save SP\n\t" \ 101 "mov.l @r6, r15\t! change to new stack\n\t" \ 103 "mov.l %0, @r2\t! save PC\n\t" \ 104 "mov.l 2f, %0\n\t" \ 111 "mov.l @r15+, r14\n\t" \ 112 "mov.l @r15+, r13\n\t" \ 113 "mov.l @r15+, r12\n\t" \ 114 "mov.l @r15+, r11\n\t" \ 115 "mov.l @r15+, r10\n\t" \ 116 "mov.l @r15+, r9\n\t" \ 117 "mov.l @r15+, r8\n\t" \
|
H A D | spinlock.h | 45 "mov %0, %1 \n\t" arch_spin_lock() 46 "mov #0, %0 \n\t" arch_spin_lock() 62 "mov #1, %0 ! arch_spin_unlock \n\t" arch_spin_unlock() 63 "mov.l %0, @%1 \n\t" arch_spin_unlock() 77 "mov %0, %1 \n\t" arch_spin_trylock() 78 "mov #0, %0 \n\t" arch_spin_trylock() 166 "mov.l %1, @%0 ! arch_write_unlock \n\t" arch_write_unlock() 180 "mov %0, %1 \n\t" arch_read_trylock() 203 "mov %0, %1 \n\t" arch_write_trylock()
|
H A D | mmu_context_32.h | 28 __asm__ __volatile__ ("mov.l %2, %0\n\t" set_asid() 31 "mov.l %0, %2" set_asid() 41 __asm__ __volatile__ ("mov.l %1, %0" get_asid()
|
H A D | checksum_32.h | 94 "mov.l @%1+, %0\n\t" ip_fast_csum() 95 "mov.l @%1+, %3\n\t" ip_fast_csum() 101 "mov.l @%1+, %3\n\t" ip_fast_csum() 169 "mov.l @(0,%2), %1\n\t" csum_ipv6_magic() 171 "mov.l @(4,%2), %1\n\t" csum_ipv6_magic() 173 "mov.l @(8,%2), %1\n\t" csum_ipv6_magic() 175 "mov.l @(12,%2), %1\n\t" csum_ipv6_magic() 177 "mov.l @(0,%3), %1\n\t" csum_ipv6_magic() 179 "mov.l @(4,%3), %1\n\t" csum_ipv6_magic() 181 "mov.l @(8,%3), %1\n\t" csum_ipv6_magic() 183 "mov.l @(12,%3), %1\n\t" csum_ipv6_magic()
|
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/ |
H A D | entry.S | 46 mov.l r2,@-sp 48 mov.l $cpu_mode,r2 54 mov.l $current_thread_info,r2 55 mov.l @r2,r2 56 mov #(THREAD_SIZE >> 8),r0 59 mov r15,r2 ! r2 = user stack top 60 mov r0,r15 ! switch kernel stack 61 mov.l r1,@-r15 ! TRA 65 mov.l @(4*4,r2),r0 66 mov.l r0,@-r15 ! original SR 68 mov.l @(3*4,r2),r0 69 mov.l r0,@-r15 ! original PC 70 mov r2,r0 74 mov r2,r8 ! r8 = previus stack top 75 mov r1,r9 ! r9 = interrupt vector 77 mov.l @r8+,r2 78 mov.l @r8+,r0 79 mov.l @r8+,r1 84 mov r15,r2 87 mov r2,r8 ! r8 = previous stack top 88 mov r1,r9 ! r9 = interrupt vector 90 mov.l @r8+,r2 ! old R2 91 mov.l @r8+,r0 ! old R0 92 mov.l @r8+,r1 ! old R1 93 mov.l @r8+,r10 ! old PC 94 mov.l @r8+,r11 ! old SR 96 mov.l r10,@(OFF_PC,r15) 97 mov.l r11,@(OFF_SR,r15) 98 mov.l r8,@(OFF_SP,r15) ! save old sp 99 mov r15,r8 101 mov.l r9,@-r8 109 mov #64,r8 112 mov #32,r8 116 mov.l 4f,r8 117 mov r9,r4 120 mov.l @r8,r8 ! exception handler address 123 mov.l 8f,r8 ! unhandled exception 125 mov.l 5f,r10 130 mov r9,r4 131 mov r15,r5 132 mov.l 7f,r8 133 mov.l 6f,r9 145 mov #0x30,r8 152 mov r9,r8 157 mov r15,r0 162 mov r15,r0 163 mov.l @(OFF_SP,r0),r1 164 mov.l @(OFF_SR,r2),r3 165 mov.l r3,@-r1 166 mov.l @(OFF_SP,r2),r3 167 mov.l r3,@-r1 168 mov r15,r0 170 mov.l 1f,r2 171 mov.l @r2,r2 173 mov.l r2,@r0 174 mov.l r3,@(4,r0) 175 mov.l r1,@(8,r0) 179 mov.l @r15+,r15 187 mov r15,r4 ! regs 188 mov.l @(OFF_PC,r15),r6 ! pc 189 mov.l 1f,r0 191 mov #0,r5 ! writeaccess is unknown 202 mov r15,r0 209 mov r15,r0 210 mov.l $cpu_mode,r2 213 mov.l @(OFF_SR,r0),r1 216 mov.l @(OFF_SP,r0),r2 218 mov.l r2,@(OFF_SP,r0) ! point exception frame top 219 mov.l r1,@(4,r2) ! set sr 220 mov.l @(OFF_PC,r0),r1 221 mov.l r1,@r2 ! set pc 223 mov.l $current_thread_info,r1 224 mov.l r0,@r1 226 mov.l @r15,r15
|
H A D | ex.S | 23 mov.l r1,@-sp 25 mov #no,r1 29 mov.l r0,@-sp 30 mov.l 1f,r0 42 mov.l r1,@-sp 44 mov #no,r1 48 mov.l r0,@-sp 52 mov.l 1f,r0
|
H A D | opcode_helper.c | 27 * 0011nnnnmmmm0001 mov.b, mov.w, mov.l, fmov.d, 43 case 0x3001: /* 32-bit mov/fmov/movu variants */ instruction_size()
|
/linux-4.1.27/arch/sparc/prom/ |
H A D | cif.S | 18 mov %g4, %l0 19 mov %g5, %l1 20 mov %g6, %l3 22 mov %i0, %o0 ! prom_args 23 mov %l0, %g4 24 mov %l1, %g5 25 mov %l3, %g6 38 mov 0, %o0 41 mov %i0, %o0 42 mov %o0, %l1 44 mov 1, %o0
|
/linux-4.1.27/arch/mn10300/boot/compressed/ |
H A D | head.S | 30 mov (CPUID), d3 33 mov CONFIG_KERNEL_TEXT_ADDRESS,a0 40 mov param_save_area,a0 41 mov d0,(a0) 42 mov d1,(4,a0) 43 mov d2,(8,a0) 45 mov sp,a3 46 mov decomp_stack+0x2000-4,a0 47 mov a0,sp 50 mov CHCTR,a0 53 mov CHCTR_ICINV|CHCTR_DCINV,d0 56 mov (a0),d0 62 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 64 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 70 mov __bss_start,a0 71 mov _end,a1 88 mov CHCTR,a0 92 mov (a0),d0 96 mov param_save_area,a0 97 mov (a0),d0 98 mov (4,a0),d1 99 mov (8,a0),d2 102 mov a3,sp 103 mov CONFIG_KERNEL_TEXT_ADDRESS,a0 118 mov L1_CACHE_NENTRIES,d1 122 mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge 123 mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge 124 mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge 125 mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
|
/linux-4.1.27/arch/x86/platform/efi/ |
H A D | efi_stub_64.S | 16 mov %rsp, %rax; \ 19 mov %rax, (%rsp); \ 20 mov %cr0, %rax; \ 22 mov %rax, 0x8(%rsp); \ 37 mov 0x8(%rsp), %rsi; \ 38 mov %rsi, %cr0; \ 39 mov (%rsp), %rsp 78 mov (%rsp), %rax 79 mov 8(%rax), %rax 81 mov %r9, 32(%rsp) 82 mov %rax, 40(%rsp) 83 mov %r8, %r9 84 mov %rcx, %r8 85 mov %rsi, %rcx
|
/linux-4.1.27/arch/sh/boards/mach-hp6xx/ |
H A D | pm_wakeup.S | 25 mov #-126, k1 27 mov.b k0, @k1 29 mov.l 5f, k1 30 mov.w 6f, k0 31 mov.w k0, @k1 33 mov.l 4f, k1
|
/linux-4.1.27/arch/sparc/lib/ |
H A D | mcount.S | 33 mov %i7, %g3 35 mov %g3, %o1 37 mov %i7, %o0 54 5: mov %i7, %g2 55 mov %fp, %g3 57 mov %g2, %l0 59 mov %g3, %l1 80 mov %i7, %g2 81 mov %fp, %g3 83 mov %g2, %o1 84 mov %g2, %l0 85 mov %g3, %l1 89 mov %i7, %o0 108 mov %l0, %o0 109 mov %i7, %o1 111 mov %l1, %o2 119 mov %fp, %o0
|
H A D | udivdi3.S | 25 mov %i3,%o3 28 mov %i1,%i3 31 mov %i3,%o1 33 mov 32,%g1 57 mov 0,%o2 61 mov %i0,%o2 62 mov 1,%o0 63 mov 0,%o1 66 mov %o0,%o3 67 mov %i0,%o2 69 mov 0,%o4 71 mov 32,%g1 94 mov %o4,%i0 95 mov %i3,%o1 97 mov 32,%g1 121 mov %o1,%l1 127 mov 0,%o1 132 mov %i2,%o1 142 mov 24,%o2 143 mov 16,%o2 150 mov 32,%o1 153 mov 32,%o0 158 mov 0,%o1 161 mov 1,%o1 173 mov %i0,%o5 174 mov %o1,%o4 176 mov 32,%g1 199 mov %o4,%i0 200 mov %o5,%o1 245 mov 0,%o2 248 mov 0,%o2 251 mov 0,%o2 253 mov %o1,%l1 255 mov %o2,%l0 256 mov %l0,%i0 257 mov %l1,%i1
|
H A D | divdi3.S | 27 mov 0,%l4 28 mov -1,%l4 30 mov %o0,%o5 34 mov %o4,%i0 35 mov %o5,%i1 39 mov %i3,%o4 42 mov %o0,%o3 46 mov %o2,%i2 47 mov %o3,%i3 48 mov %i3,%o4 52 mov %i1,%i3 55 mov %i3,%o1 56 mov 32,%g1 79 mov 0,%o2 83 mov %i0,%o2 84 mov 1,%o0 85 mov 0,%o1 88 mov %o0,%o4 89 mov %i0,%o2 91 mov 0,%g3 92 mov 32,%g1 114 mov %g3,%i0 115 mov %i3,%o1 116 mov 32,%g1 139 mov %o1,%l1 145 mov 0,%o1 150 mov %i2,%o1 160 mov 24,%o2 161 mov 16,%o2 168 mov 32,%o1 176 mov 0,%o1 179 mov 1,%o1 190 mov %i0,%o1 191 mov 32,%g1 213 mov %o2,%i0 257 mov 0,%o2 260 mov 0,%o2 263 mov 0,%o2 265 mov %o1,%l1 267 mov %o2,%l0 268 mov %l0,%i0 269 mov %l1,%i1 273 mov %o0,%l3 277 mov %l2,%i0 278 mov %l3,%i1
|
H A D | csum_copy_from_user.S | 11 mov -1, %o0; \
|
H A D | csum_copy_to_user.S | 11 mov -1, %o0; \
|
H A D | muldi3.S | 64 mov %o1, %l3 65 mov %i1, %o0 66 mov %i2, %o1 68 mov %o0, %l0 69 mov %i0, %o0 70 mov %i3, %o1 73 mov %l2, %i0
|
H A D | locks.S | 36 mov %g4, %o7 59 mov %g4, %o7 70 mov %g4, %o7 81 mov %g4, %o7 92 mov %g4, %o7
|
H A D | NG4memset.S | 17 mov %o2, %o1 33 mov %o0, %o3 57 mov 0x20, %g2 88 mov %o3, %o0 90 mov 0x08, %g3 91 mov 0x28, %o5
|
H A D | strlen.S | 16 mov %o0, %o1 73 mov 0, %o0 76 mov 1, %o0 79 mov 2, %o0
|
H A D | GENbzero.S | 22 mov %o2, %o1 36 mov %o0, %o3 42 mov ASI_P, %o4 50 mov 8, %g2 61 mov 64, %g2 112 mov %o3, %o0 126 mov ASI_AIUS, %o4
|
H A D | memset.S | 69 mov %o0, %g1 70 mov 1, %g4 77 mov %o2, %o1 96 mov %g0, %g3 107 mov %g3, %g2 175 mov %g1, %o0 195 mov 8, %o0 204 mov %i5, %o0 205 mov %i7, %o1 207 mov %i4, %o2
|
/linux-4.1.27/arch/ia64/kernel/ |
H A D | pal.S | 45 mov r8=-1 60 mov r28 = in0 61 mov r29 = in1 62 mov r8 = ip 67 mov loc4=ar.rsc // save RSE configuration 69 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 70 mov loc3 = psr 71 mov loc0 = rp 73 mov r30 = in2 75 mov r31 = in3 76 mov b7 = loc2 80 mov rp = r8 82 1: mov psr.l = loc3 83 mov ar.rsc = loc4 // restore RSE configuration 84 mov ar.pfs = loc1 85 mov rp = loc0 103 mov r28 = in0 // Index MUST be copied to r28 104 mov out0 = in0 // AND in0 of PAL function 105 mov loc0 = rp 109 mov out1 = in1 110 mov out2 = in2 111 mov out3 = in3 112 mov loc3 = psr 115 mov b7 = loc2 118 .ret0: mov psr.l = loc3 119 mov ar.pfs = loc1 120 mov rp = loc0 150 mov r28 = in0 // copy procedure index 151 mov r8 = ip // save ip to compute branch 152 mov loc0 = rp // save rp 157 mov r29 = in1 // first argument 158 mov r30 = in2 // copy arg2 159 mov r31 = in3 // copy arg3 161 mov loc3 = psr // save psr 164 mov loc4=ar.rsc // save RSE configuration 168 mov b7 = loc2 // install target to branch reg 169 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 177 mov rp = r8 // install return address (physical) 178 mov loc5 = r19 179 mov loc6 = r20 182 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 183 mov r16=loc3 // r16= original psr 184 mov r19=loc5 185 mov r20=loc6 187 mov psr.l = loc3 // restore init PSR 189 mov ar.pfs = loc1 190 mov rp = loc0 192 mov ar.rsc=loc4 // restore RSE configuration 209 mov r28 = in0 // copy procedure index 210 mov loc0 = rp // save rp 215 mov loc3 = psr // save psr 217 mov loc4=ar.rsc // save RSE configuration 220 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 225 mov b7 = loc2 // install target to branch reg 230 mov out0 = in0 // first argument 231 mov out1 = in1 // copy arg2 232 mov out2 = in2 // copy arg3 233 mov out3 = in3 // copy arg3 234 mov loc5 = r19 235 mov loc6 = r20 239 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 240 mov r16=loc3 // r16= original psr 241 mov r19=loc5 242 mov r20=loc6 245 mov psr.l = loc3 // restore init PSR 246 mov ar.pfs = loc1 247 mov rp = loc0 249 mov ar.rsc=loc4 // restore RSE configuration
|
H A D | efi_stub.S | 49 mov loc0=rp 52 mov loc2=gp // save global pointer 53 mov loc4=ar.rsc // save RSE configuration 54 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 58 mov loc3=psr // save processor status word 62 mov b6=r2 66 .ret0: mov out4=in5 67 mov out0=in1 68 mov out1=in2 69 mov out2=in3 70 mov out3=in4 71 mov out5=in6 72 mov out6=in7 73 mov loc5=r19 74 mov loc6=r20 76 .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode 77 mov r16=loc3 78 mov r19=loc5 79 mov r20=loc6 81 .ret2: mov ar.rsc=loc4 // restore RSE configuration 82 mov ar.pfs=loc1 83 mov rp=loc0 84 mov gp=loc2
|
H A D | relocate_kernel.S | 28 mov r2=ip 41 mov ar.rsc=0 // put RSE in enforced lazy mode 46 mov r18=ar.rnat 47 mov ar.bspstore=r8 49 mov cr.ipsr=r16 50 mov cr.iip=r3 51 mov cr.ifs=r0 54 mov ar.rnat=r18 59 mov b6=in1 75 mov r24=r0 83 mov ar.lc=r20 99 mov r18=KERNEL_TR_PAGE_SHIFT<<2 108 mov r16=in3 109 mov r18=IA64_GRANULE_SHIFT<<2 117 mov r16=IA64_KR(CURRENT_STACK) 123 mov r18=IA64_GRANULE_SHIFT<<2 132 mov r30=in0 // in0 is page_list 156 mov ar.lc=r14;; 193 mov ar.rsc=0 // put RSE in enforced lazy mode 205 mov r4=ar.rnat 209 mov r5=pr 213 mov r4=b0 217 mov r5=b1; 221 mov r4=b2 225 mov r5=b3 229 mov r4=b4 233 mov r5=b5 237 mov r4=b6 241 mov r5=b7 245 mov r4=b0 249 mov r5=loc0 253 mov r4=r0 // user mask 260 mov r5=ar.rsc 264 mov r4=ar.bsp 268 mov r5=ar.bspstore 272 mov r4=ar.rnat 276 mov r5=ar.ccv 280 mov r4=ar.unat 284 mov r5 = ar.fpsr 288 mov r4 = ar.unat 292 mov r5 = ar.fpsr 296 mov r4 = ar.pfs 300 mov r5 = ar.lc 304 mov r4 = ar.ec 308 mov r5 = ar.csd 312 mov r4 = ar.ssd 320 mov ar.pfs=loc0
|
H A D | esi_stub.S | 51 mov loc0=rp 69 mov loc2=gp // save global pointer 70 mov loc4=ar.rsc // save RSE configuration 71 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 75 mov loc3=psr // save processor status word 79 mov b6=r2 83 .ret0: mov loc5=r19 // old ar.bsp 84 mov loc6=r20 // old sp 86 .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode 87 mov r16=loc3 // save virtual mode psr 88 mov r19=loc5 // save virtual mode bspstore 89 mov r20=loc6 // save virtual mode sp 91 .ret2: mov ar.rsc=loc4 // restore RSE configuration 92 mov ar.pfs=loc1 93 mov rp=loc0 94 mov gp=loc2
|
H A D | minstate.h | 10 (pUStk) mov.m r20=ar.itc; 48 mov r16=IA64_KR(CURRENT); /* M */ \ 49 mov r27=ar.rsc; /* M */ \ 50 mov r20=r1; /* A */ \ 51 mov r25=ar.unat; /* M */ \ 53 mov r26=ar.pfs; /* I */ \ 55 mov r21=ar.fpsr; /* M */ \ 69 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ 71 (pUStk) mov.m r24=ar.rnat; \ 73 (pKStk) mov r1=sp; /* get sp */ \ 77 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \ 79 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \ 82 (pUStk) mov r18=ar.bsp; \ 83 (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ 92 mov r29=b0 \ 97 (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \ 108 mov r8=ar.ccv; \ 109 mov r9=ar.csd; \ 110 mov r10=ar.ssd; \ 135 mov r13=IA64_KR(CURRENT); /* establish `current' */ \ 175 mov r18=b6; \ 179 mov r19=b7; \ 193 mov ar.fpsr=r11; /* M-unit */ \ 222 (p6) mov r17=0x310; \ 223 (p7) mov r17=0x308; \ 230 mov ar.pfs=r17; \ 232 mov b0=r16; \ 237 mov ar.rsc=r0 \ 241 mov ar.bspstore=r22 \ 243 mov r18=ar.bsp; \ 248 #define SAVE_MIN_WITH_COVER DO_SAVE_MIN(COVER, mov r30=cr.ifs, , RSE_WORKAROUND) 249 #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(COVER, mov r30=cr.ifs, mov r15=r19, RSE_WORKAROUND) 250 #define SAVE_MIN DO_SAVE_MIN( , mov r30=r0, , )
|
H A D | mca_asm.S | 73 mov r24=0 82 mov ar.lc=r20 100 mov r18=KERNEL_TR_PAGE_SHIFT<<2 113 mov r18=IA64_GRANULE_SHIFT<<2 120 mov r16=IA64_KR(CURRENT_STACK) 126 mov r18=IA64_GRANULE_SHIFT<<2 141 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack 143 mov r19=1 // All MCA events are treated as monarch (for now) 162 mov b1=r18;; 168 mov r18=KERNEL_TR_PAGE_SHIFT<<2 171 mov cr.itir=r18 172 mov cr.ifa=r17 173 mov r16=IA64_TR_KERNEL 174 mov r19=ip 196 mov r19=IA64_GRANULE_SHIFT<<2 198 mov cr.itir=r19 199 mov cr.ifa=r16 200 mov r20=IA64_TR_PALCODE 207 mov r16=IA64_KR(CURRENT_STACK) 216 mov r19=IA64_GRANULE_SHIFT<<2 218 mov cr.itir=r19 219 mov cr.ifa=r18 220 mov r20=IA64_TR_CURRENT_STACK 224 mov r18 = 1 234 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack 240 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack 248 mov r7=r2 262 mov ar.rsc=3 // set eager mode for C handler 263 mov r2=r7 // see GET_IA64_MCA_DATA above 284 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack 289 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack 294 mov b0=r12 // SAL_CHECK return address 313 mov r8=r0 // IA64_INIT_RESUME 314 mov r9=r10 // SAL_GP 315 mov r22=r17 // *minstate 317 mov r10=r0 // return to same context 318 mov b0=r12 // SAL_CHECK return address 329 mov r19=1 // Bow, bow, ye lower middle classes! 333 mov r19=0 // <igor>yeth, mathter</igor> 337 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack 343 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack 349 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack 357 mov r7=r2 371 mov ar.rsc=3 // set eager mode for C handler 372 mov r2=r7 // see GET_IA64_MCA_DATA above 391 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack 398 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack 403 mov b0=r12 // SAL_CHECK return address 458 mov b0=r2 // save return address 466 mov regs=temp1 // save the start of sos 472 mov r11=cr.iipa 476 mov r6=IA64_KR(CURRENT) 482 mov r12=cr.isr 486 mov r6=IA64_KR(CURRENT_STACK) 490 mov r6=cr.ifa 494 mov r12=cr.itir 498 mov r12=cr.iim 501 (p1) mov r12=IA64_MCA_COLD_BOOT 502 (p2) mov r12=IA64_INIT_WARM_BOOT 503 mov r6=cr.iha 509 mov r6=IA64_MCA_SAME_CONTEXT 518 mov temp3=b6 519 mov temp4=b7 524 mov temp3=ar.csd 525 mov temp4=ar.ssd 530 mov temp3=ar.unat 531 mov temp4=ar.pfs 535 mov temp3=ar.rnat 536 mov temp4=ar.bspstore 540 mov temp3=ar.bsp 543 mov temp4=ar.fpsr 549 mov temp3=ar.ccv 604 mov temp3=b2 605 mov temp4=b3 609 mov temp3=b4 610 mov temp4=b5 614 mov temp3=ar.lc 719 mov b0=r2 // save return address 767 mov b2=temp3 768 mov b3=temp4 772 mov b4=temp3 773 mov b5=temp4 776 mov ar.lc=temp3 788 mov b6=temp3 789 mov b7=temp4 793 mov ar.csd=temp3 794 mov ar.ssd=temp4 799 mov ar.unat=temp3 800 mov ar.pfs=temp4 805 mov ar.ccv=temp3 806 mov ar.fpsr=temp4 834 mov cr.isr=temp3 835 mov cr.ifa=temp4 839 mov cr.itir=temp3 840 mov cr.iipa=temp4 846 mov cr.iim=temp3 847 mov cr.iha=temp4 849 mov IA64_KR(CURRENT)=r13 863 mov r15=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK 868 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps 878 mov IA64_KR(CURRENT_STACK)=r16 883 mov cr.itir=r18 884 mov cr.ifa=r13 885 mov r20=IA64_TR_CURRENT_STACK 918 mov b0=r2 // save return address 930 mov temp3=IA64_RBS_OFFSET-MCA_PT_REGS_OFFSET 936 mov ar.bspstore=temp4 // switch RBS to MCA/INIT stack 971 mov b0=r2 // save return address 975 mov cr.ipsr=r0 976 mov cr.ifs=r0 977 mov cr.iip=temp1 990 mov ar.rsc=temp2 995 mov ar.bspstore=temp3 // back to old stack 997 mov ar.rnat=temp4 1021 mov b0=r2 // save return address 1031 mov IA64_KR(CURRENT)=r13 1038 mov r16=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK 1043 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps 1052 mov IA64_KR(CURRENT_STACK)=r16 1055 mov cr.itir=r18 1056 mov cr.ifa=r13 1057 mov r20=IA64_TR_CURRENT_STACK 1061 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value 1085 mov ar.rsc=0 1087 mov r14=ar.bspstore 1092 (p7) mov r8=ar.rnat 1093 mov ar.rsc=3 1106 mov r14 = psr // get psr{36:35,31:0} 1115 mov cr.ipsr = r14 1116 mov cr.ifs = r0 1117 mov cr.iip = r15
|
H A D | entry.S | 65 mov loc0=rp 67 mov out0=in0 // filename 69 mov out1=in1 // argv 70 mov out2=in2 // envp 74 mov ar.pfs=loc1 // restore ar.pfs 78 mov rp=loc0 79 (p6) mov ar.pfs=r0 // clear ar.pfs on success 88 mov ar.unat=0; mov ar.lc=0 89 mov r4=0; mov f2=f0; mov b1=r0 90 mov r5=0; mov f3=f0; mov b2=r0 91 mov r6=0; mov f4=f0; mov b3=r0 92 mov r7=0; mov f5=f0; mov b4=r0 93 ldf.fill f12=[sp]; mov f13=f0; mov b5=r0 94 ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0 95 ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0 96 ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0 97 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0 98 ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0 99 ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0 115 mov loc0=rp 116 mov loc1=r16 // save ar.pfs across do_fork 118 mov out1=in1 119 mov out2=in2 121 mov out3=in3 // parent_tidptr: valid only w/CLONE_PARENT_SETTID 124 mov out4=in4 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID 125 mov out0=in0 // out0 = clone_flags 129 mov ar.pfs=loc1 130 mov rp=loc0 146 mov loc0=rp 147 mov loc1=r16 // save ar.pfs across do_fork 149 mov out1=in1 150 mov out2=16 // stacksize (compensates for 16-byte scratch area) 152 mov out3=in2 // parent_tidptr: valid only w/CLONE_PARENT_SETTID 155 mov out4=in3 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID 156 mov out0=in0 // out0 = clone_flags 160 mov ar.pfs=loc1 161 mov rp=loc0 180 mov r27=IA64_KR(CURRENT_STACK) 197 mov r8=r13 // return pointer to previously running task 198 mov r13=in0 // set "current" pointer 213 mov r25=IA64_GRANULE_SHIFT<<2 218 mov r25=IA64_TR_CURRENT_STACK 248 mov r17=ar.unat // preserve caller's 281 mov.m ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0 285 mov.m r18=ar.fpsr // preserve fpsr 289 mov.m r19=ar.rnat 290 mov r21=b0 294 mov r22=b1 297 mov.m r29=ar.unat 298 mov.m r20=ar.bspstore 299 mov r23=b2 302 mov r24=b3 306 mov r25=b4 307 mov r26=b5 311 mov r21=ar.lc // I-unit 349 mov r21=pr 356 mov ar.rsc=3 // put RSE back into eager mode, pl 0 374 mov ar.rsc=0 // put RSE into enforced lazy mode 416 mov b0=r21 420 mov b1=r22 424 mov b2=r23 426 mov ar.bspstore=r27 427 mov ar.unat=r29 // establish unat holding the NaT bits for r4-r7 428 mov b3=r24 432 mov b4=r25 436 mov b5=r26 440 mov ar.pfs=r16 444 mov ar.lc=r17 448 mov pr=r28,-1 453 mov ar.unat=r18 // restore caller's unat 454 mov ar.rnat=r30 // must restore after bspstore but before rsc! 455 mov ar.fpsr=r19 // restore fpsr 456 mov ar.rsc=3 // put RSE back into eager mode, pl 0 510 mov r10=0 528 mov r3=NR_syscalls - 1 539 mov b6=r20 545 mov r10=0 564 (p6) mov r10=-1 565 (p6) mov r8=r9 590 mov loc0=rp 591 mov loc2=gp 592 mov out0=r5 // arg 595 mov b6 = r14 599 .ret12: mov gp=loc2 600 mov rp=loc0 601 mov ar.pfs=loc1 628 mov r8=0 640 mov r10=r0 // clear error indication in r10 717 (pUStk) mov r21=0 // r21 <- 0 746 mov r16=ar.bsp // M2 get existing backing store pointer 773 mov r22=r0 // A clear r22 786 mov f6=f0 // F clear f6 790 mov f7=f0 // F clear f7 794 (pUStk) mov r17=1 // A 802 mov f8=f0 // F clear f8 806 mov b6=r18 // I0 restore b6 809 mov f9=f0 // F clear f9 817 mov r19=ar.bsp // M2 get new backing store pointer 819 mov f10=f0 // F clear f10 821 mov r22=r0 // A clear r22 825 mov r19=ar.bsp // M2 get new backing store pointer 826 mov f10=f0 // F clear f10 832 mov.m ar.csd=r0 // M2 clear ar.csd 833 mov.m ar.ccv=r0 // M2 clear ar.ccv 834 mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc) 836 mov.m ar.ssd=r0 // M2 clear ar.ssd 837 mov f11=f0 // F clear f11 861 (pUStk) mov r21=0 // r21 <- 0 910 mov ar.csd=r30 911 mov ar.ssd=r31 918 mov b6=r28 922 mov b7=r29 942 mov ar.ccv=r15 947 (pUStk) mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency) 998 (pUStk) mov r17=1 1002 // mib : mov add br -> mib : ld8 add br 1003 // bbb_ : br nop cover;; mbb_ : mov br cover;; 1013 mov r16=ar.bsp // get existing backing store pointer 1019 mov r16=ar.bsp // get existing backing store pointer 1032 mov r19=ar.bsp // get new backing store pointer 1060 mov ar.rsc=r19 // load ar.rsc to be used for "loadrs" 1062 mov in1=0 1078 mov loc1=0 1080 mov loc2=0 1082 mov loc3=0 1083 mov loc4=0 1087 mov loc5=0 1091 mov loc6=0 1092 mov loc7=0 1100 mov loc1=0 1101 mov loc2=0 1103 mov loc3=0 1104 mov loc4=0 1105 mov loc5=0 1106 mov loc6=0 1107 mov loc7=0 1110 mov loc8=0 1111 mov loc9=0 1113 mov loc10=0 1114 mov loc11=0 1125 mov ar.unat=r25 // M2 1127 (pLvSys)mov r19=r0 // A clear r19 for leave_syscall, no-op otherwise 1129 (pUStk) mov ar.bspstore=r23 // M2 1131 (pLvSys)mov r16=r0 // A clear r16 for leave_syscall, no-op otherwise 1134 mov ar.pfs=r26 // I0 1135 (pLvSys)mov r17=r0 // A clear r17 for leave_syscall, no-op otherwise 1138 mov b0=r21 // I0 1139 (pLvSys)mov r18=r0 // A clear r18 for leave_syscall, no-op otherwise 1141 mov ar.fpsr=r20 // M2 1145 (pUStk) mov ar.rnat=r24 // M2 must happen with RSE in lazy mode 1147 (pLvSys)mov r2=r0 1149 mov ar.rsc=r27 // M2 1150 mov pr=r31,-1 // I0 1206 (p7) mov r10=-1 1218 mov loc0=rp 1219 mov out0=r8 // Address of previous task 1222 .ret11: mov ar.pfs=loc1 1223 mov rp=loc0 1238 mov r9=ar.unat 1239 mov loc0=rp // save return address 1240 mov out0=0 // there is no "oldset" 1242 (pSys) mov out2=1 // out2==1 => we're in a syscall 1244 (pNonSys) mov out2=0 // out2==0 => not a syscall 1255 mov rp=loc0 1257 mov ar.unat=r9 1258 mov ar.pfs=loc1 1297 mov.sptk b7=r8,ia64_native_leave_kernel 1299 mov ar.unat=r9 1308 mov r16=r0 1326 mov loc0=rp 1327 mov r16=loc1 1338 mov out1=r13 // current 1342 mov b6=loc2 1343 mov loc2=gp // save gp across indirect function call 1346 mov out1=in1 // arg 1348 1: mov gp=loc2 // restore gp 1356 mov ar.pfs=loc1 1357 mov rp=loc0 1372 mov out3 = r0 1374 mov out2 = b0 1376 mov out1 = r1; 1381 mov b0 = r3 1392 mov loc1 = b0 1393 mov out0 = b0 1394 mov loc2 = r8 1395 mov loc3 = r15 1398 mov out1 = in2 1399 mov b6 = r3 1403 mov ar.pfs = loc0 1404 mov b0 = loc1 1405 mov r8 = loc2 1406 mov r15 = loc3 1423 mov loc1 = b0 1424 mov out0 = b0 1425 mov loc2 = r8 1426 mov loc3 = r15 1429 mov out1 = in2 1430 mov b6 = r3 1434 mov ar.pfs = loc0 1435 mov b0 = loc1 1436 mov r8 = loc2 1437 mov r15 = loc3 1444 mov r3 = b0 1447 mov b6 = r2 1448 mov b7 = r3 1452 mov b0 = r42 1453 mov r1 = r41 1454 mov ar.pfs = r40
|
H A D | head.S | 42 mov dest=src;; \ 47 mov reg=_tmp 50 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 51 mov _idx=0;; \ 58 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 59 mov _idx=0;; \ 66 mov _reg=rr[_tmp] 89 mov ar.lc=0x08-1;; \ 94 mov rr[_idx2]=_tmp;; \ 166 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \ 167 mov rr[_tmp1]=_tmp2 211 mov r25=pr;; 237 mov r18=KERNEL_TR_PAGE_SHIFT<<2 240 mov cr.itir=r18 241 mov cr.ifa=r17 242 mov r16=IA64_TR_KERNEL 243 mov r3=ip 264 mov cr.ipsr=r16 267 mov cr.iip=r17 268 mov cr.ifs=r0 283 mov cr.iva=r3 289 mov ar.fpsr=r2 307 (isAP) mov r2=r3 314 mov r16=-1 327 mov r17=rr[r2] 332 mov cr.itir=r17 333 mov cr.ifa=r2 335 mov r19=IA64_TR_CURRENT_STACK 345 mov IA64_KR(CURRENT)=r2 // virtual address 346 mov IA64_KR(CURRENT_STACK)=r16 347 mov r13=r2 358 mov ar.rsc=0 // place RSE in enforced lazy mode 362 mov r18=PERCPU_PAGE_SIZE 378 mov r19=r20 385 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0 386 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base 388 mov ar.bspstore=r2 // establish the new RSE stack 390 mov ar.rsc=0x3 // place RSE in eager mode 401 mov r16=num_hypervisor_hooks 410 (p7) mov b1=r9 461 mov r20=ar.lc // preserve ar.lc 462 mov ar.lc=IA64_NUM_DBG_REGS-1 463 mov r18=0 466 1: mov r16=dbr[r18] 471 mov r17=ibr[r18] 478 mov ar.lc=r20 // restore ar.lc 485 mov r20=ar.lc // preserve ar.lc 487 mov ar.lc=IA64_NUM_DBG_REGS-1 488 mov r18=-1 494 mov dbr[r18]=r16 499 mov ibr[r18]=r17 502 mov ar.lc=r20 // restore ar.lc 676 mov loc0=512 677 mov loc1=-1024+16 803 mov f32=f0 // F 808 mov f37=f0 // F 813 mov f40=f0 // F 817 mov f45=f0 // F 821 mov f48=f0 // F 825 mov f53=f0 // F 829 mov f56=f0 // F 833 mov f61=f0 // F 837 mov f64=f0 // F 841 mov f69=f0 // F 845 mov f72=f0 // F 849 mov f77=f0 // F 853 mov f80=f0 // F 857 mov f85=f0 // F 861 mov f88=f0 // F 865 * the remaining registers with simply mov instructions (F-unit). 873 mov f93=f0 // F 877 mov f96=f0 // F 881 mov f101=f0 // F 885 mov f104=f0 // F 889 mov f109=f0 // F 893 mov f112=f0 // F 897 mov f117=f0 // F 901 mov f120=f0 // F 905 mov f125=f0 // F 926 mov r15=ip 934 mov cr.ipsr=r16 // set new PSR 937 mov r19=ar.bsp 938 mov r20=sp 939 mov r14=rp // get return address into a general register 949 mov r18=ar.rnat // save ar.rnat 950 mov ar.bspstore=r17 // this steps on ar.rnat 951 mov cr.iip=r3 952 mov cr.ifs=r0 954 mov ar.rnat=r18 // restore ar.rnat 957 1: mov rp=r14 974 mov r15=ip 982 mov cr.ipsr=r16 // set new PSR 985 mov r14=rp // get return address into a general register 994 mov sp=r20 1000 mov r18=ar.rnat // save ar.rnat 1001 mov ar.bspstore=r19 // this steps on ar.rnat 1002 mov cr.iip=r3 1003 mov cr.ifs=r0 1005 mov ar.rnat=r18 // restore ar.rnat 1008 1: mov rp=r14 1016 mov r2=ar.lc 1019 mov ar.lc=r32 1027 mov ar.lc=r2 1051 mov.m r9=ar.itc // fetch cycle-counter (35 cyc) 1102 mov reg=r32; \ 1128 mov b1=r18 // Return location 1131 mov b2=r18 // doing tlb_flush work 1132 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode 1135 mov cr.iip=r17 1137 mov cr.ipsr=r16 1138 mov cr.ifs=r0;; 1176 mov pr=r17,-1;;
|
H A D | ivt.S | 72 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16 80 mov r31=pr; \ 81 mov r19=n;; /* prepare to save predicates */ \ 118 mov r31=pr // save the predicate registers 119 mov r19=IA64_KR(PT_BASE) // get page table base address 234 mov r27=PAGE_SHIFT<<2 242 mov pr=r31,-1 // restore predicate registers 258 mov r29=b0 // save b0 259 mov r31=pr // save predicates 266 mov b0=r29 280 mov r20=PAGE_SHIFT<<2 // setup page size for purge 286 mov pr=r31,-1 302 mov r29=b0 // save b0 303 mov r31=pr // save predicates 310 mov b0=r29 324 mov r20=PAGE_SHIFT<<2 // setup page size for purge 330 mov pr=r31,-1 343 mov r31=pr 353 (p8) mov r29=b0 // save b0 368 mov pr=r31,-1 382 mov r31=pr 383 mov r24=PERCPU_ADDR 393 (p8) mov r29=b0 // save b0 398 mov r25=PERCPU_PAGE_SHIFT << 2 399 mov r26=PERCPU_PAGE_SIZE 403 (p10) mov r19=IA64_KR(PER_CPU_DATA) 423 mov pr=r31,-1 454 mov r19=IA64_KR(PT_BASE) // get the page table base address 504 mov b0=r30 542 mov r29=b0 // save b0 in case of nested fault 543 mov r31=pr // save pr 545 mov r28=ar.ccv // save ar.ccv 549 mov ar.ccv=r18 // set compare value for cmpxchg 554 mov r24=PAGE_SHIFT<<2 571 mov b0=r29 // restore b0 572 mov ar.ccv=r28 578 mov b0=r29 // restore b0 583 mov pr=r31,-1 // restore pr 595 mov r31=pr // save predicates 605 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa 609 mov r29=b0 // save b0 in case of nested fault) 611 mov r28=ar.ccv // save ar.ccv 615 mov ar.ccv=r18 // set compare value for cmpxchg 620 mov r24=PAGE_SHIFT<<2 637 mov b0=r29 // restore b0 638 mov ar.ccv=r28 644 mov b0=r29 // restore b0 649 mov pr=r31,-1 663 mov r31=pr 664 mov r29=b0 // save b0 in case of nested fault) 666 mov r28=ar.ccv // save ar.ccv 670 mov ar.ccv=r18 // set compare value for cmpxchg 675 mov r24=PAGE_SHIFT<<2 691 mov ar.ccv=r28 701 mov b0=r29 // restore b0 702 mov pr=r31,-1 726 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc) 728 mov r31=pr // I0 (2 cyc) 731 mov.m r27=ar.rsc // M2 (12 cyc) 732 mov r18=__IA64_BREAK_SYSCALL // A 734 mov.m ar.rsc=0 // M2 735 mov.m r21=ar.fpsr // M2 (12 cyc) 736 mov r19=b6 // I0 (2 cyc) 738 mov.m r23=ar.bspstore // M2 (12 cyc) 739 mov.m r24=ar.rnat // M2 (5 cyc) 740 mov.i r26=ar.pfs // I0 (2 cyc) 744 mov r20=r1 // A save r1 757 mov r1=r16 // A move task-pointer to "addl"-addressable reg 758 mov r2=r16 // A setup r2 for ia64_syscall_setup 763 mov r3=NR_syscalls - 1 778 mov.m ar.bspstore=r22 // M2 switch to kernel RBS 782 (p8) mov r8=0 // A clear ei to 0 789 mov b6=r30 // I0 setup syscall handler branch reg early 795 mov.m r25=ar.unat // M2 (5 cyc) 807 mov b6=r30 // I0 setup syscall handler branch reg early 812 mov r18=ar.bsp // M2 (12 cyc) 821 // mov.m r30=ar.itc is called in advance, and r13 is current 844 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0 853 mov rp=r3 // I0 set the real return addr 866 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT 868 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE 955 (pKStk) mov r18=r0 // make sure r18 isn't NaT 960 mov r28=b0 // save b0 (2 cyc) 965 (p8) mov in0=-1 974 (p9) mov in1=-1 985 (p10) mov in2=-1 987 (p11) mov in3=-1 999 (p12) mov in4=-1 1004 (p13) mov in5=-1 1010 mov r8=1 1018 mov r13=r2 // establish `current' 1022 (p13) mov in6=-1 1023 (p8) mov in7=-1 1028 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value 1029 (p10) mov r8=-EINVAL 1057 // mov.m r20=ar.itc is called in advance, and r13 is current 1114 mov r17=PAGE_SHIFT<<2 1118 mov r31=pr 1130 mov r31=pr 1143 mov r31=pr 1156 mov r31=pr 1168 mov r31=pr 1173 mov r19=24 // fault number 1185 mov r31=pr 1186 mov r19=25 1198 mov r31=pr // save PR 1208 mov pr=r31,-1 1212 1: mov pr=r31,-1 1273 mov r31=pr // prepare to save predicates 1533 mov rp=r14 1540 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER 1560 mov rp=r15 1567 mov r31=pr // prepare to save predicates 1584 mov rp=r14 1610 mov rp=r14 1637 mov out0=r15 1645 mov rp=r14 1669 mov out0=ar.ec 1677 mov out0=r9 1678 mov out1=r10 1679 mov out2=r11 1682 mov rp=r15 1683 mov b6=r8
|
H A D | gate.S | 128 mov.m r9=ar.bsp // fetch ar.bsp 153 mov b6=r10 167 mov r14=ar.bsp 190 mov r15=__NR_rt_sigreturn 197 mov ar.rsc=0 // put RSE into enforced lazy mode 200 mov r19=ar.rnat // save RNaT before switching backing store area 203 mov r18=ar.bspstore 204 mov ar.bspstore=r15 // switch over to new register backing store area 210 mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16 217 mov ar.rsc=0xf // set RSE into eager mode, pl 3 252 mov ar.rsc=r17 // put RSE into enforced lazy mode 291 mov ar.bspstore=r15 // switch back to old register backing store area 293 mov ar.rnat=r16 // restore RNaT 294 mov ar.rsc=0xf // (will be restored later on from sc_ar_rsc) 324 mov r10=0 // A default to successful syscall execution 331 mov r16=IA64_KR(CURRENT) // M2 (12 cyc) 333 mov r19=NR_syscalls-1 // A 340 mov r21=ar.fpsr // M2 (12 cyc) 342 mov.i r26=ar.pfs // I0 (would stall anyhow due to srlz.d...) 349 (p6) tbit.z.unc p8,p0=r18,0 // I0 (dual-issues with "mov b7=r18"!) 353 (p6) mov b7=r18 // I0 356 mov r27=ar.rsc // M2 (12 cyc) 368 (p6) mov b7=r14 374 mov r10=-1 375 (p10) mov r8=EINVAL 376 (p9) mov r8=ENOSYS
|
/linux-4.1.27/arch/mn10300/mm/ |
H A D | tlb-mn10300.S | 41 mov (MMUCTR),d2 42 mov d2,(MMUCTR) 46 mov (IPTEU),d3 47 mov (PTBR),a2 48 mov d3,d2 51 mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22] 56 mov d3,d2 60 mov (a2),d2 # get pte from PTD[addr 21..12] 73 mov d2,(IPTEL2) # change the TLB 80 mov _PAGE_VALID,d2 # force address error handler to be 104 mov (MMUCTR),d2 105 mov d2,(MMUCTR) 109 mov (DPTEU),d3 110 mov (PTBR),a2 111 mov d3,d2 114 mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22] 119 mov d3,d2 123 mov (a2),d2 # get pte from PTD[addr 21..12] 136 mov d2,(DPTEL2) # change the TLB 143 mov _PAGE_VALID,d2 # force address error handler to be 159 mov (MMUCTR),d1 160 mov d1,(MMUCTR) 171 mov (IPTEU),d0 173 mov d0,(12,sp) 176 mov d0,(IPTEL2) 179 mov fp,d0 196 mov (MMUCTR),d1 197 mov d1,(MMUCTR) 207 mov (DPTEU),a2 208 mov a2,d0 210 mov d0,(12,sp) 213 mov d0,(DPTEL2) 216 mov fp,d0
|
H A D | cache-dbg-flush-by-reg.S | 39 mov DCPGCR,a0 41 mov epsw,d1 51 mov (a0),d0 57 mov d0,(DCPGMR) 63 mov DCPGCR_DCP,d0 64 mov d0,(a0) 68 mov (a0),d0 76 mov CHCTR,a0 84 mov d1,epsw 109 mov d0,a1 110 mov d0,d1 113 mov DCACHE_PURGE(0,0),a0 121 mov d1,(L1_CACHE_WAYDISP*0,a0) 127 mov CHCTR,a0 134 mov ICIVCR,a0 138 mov (a0),d0 143 mov L1_CACHE_TAG_MASK,d0 144 mov d0,(ICIVMR) 148 mov a1,(a0) 152 mov (a0),d0
|
H A D | cache-dbg-inv-by-reg.S | 33 mov d0,a1 35 mov CHCTR,a0 42 mov ICIVCR,a0 46 mov (a0),d0 51 mov ~L1_CACHE_TAG_MASK,d0 52 mov d0,(ICIVMR) 57 mov a1,(a0) 61 mov (a0),d0
|
H A D | cache-flush-by-reg.S | 56 mov DCPGCR,a0 62 mov (a0),d0 68 mov d0,(DCPGMR) 74 mov DCPGCR_DCP,d0 75 mov d0,(a0) 79 mov (a0),d0 106 mov PAGE_SIZE,d1 123 mov L1_CACHE_BYTES,d2 133 mov d1,a1 # a1 = end 136 mov DCPGCR,a0 140 mov (a0),d1 145 mov d2,d1 148 mov d1,(DCPGMR) 154 mov a2,d0 156 mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCP 160 mov (a0),d1 192 mov DCPGCR,a0 198 mov (a0),d0 204 mov d0,(DCPGMR) 207 mov DCPGCR_DCP|DCPGCR_DCI,d0 208 mov d0,(a0) 212 mov (a0),d0 239 mov PAGE_SIZE,d1 256 mov L1_CACHE_BYTES,d2 266 mov d1,a1 # a1 = end 269 mov DCPGCR,a0 273 mov (a0),d1 278 mov d2,d1 281 mov d1,(DCPGMR) 287 mov a2,d0 289 mov d0,(a0) # DCPGCR = (mask & start)|DCPGCR_DCP|DCPGCR_DCI 293 mov (a0),d1
|
H A D | cache-inv-by-reg.S | 60 mov CHCTR,a0 82 mov CHCTR,a0 111 mov PAGE_SIZE,d1 130 mov CHCTR,a0 141 mov L1_CACHE_BYTES-1,d2 147 mov d0,a2 # A2 = start address 148 mov d1,a1 # A1 = end address 152 mov DCPGCR,a0 # make sure the purger isn't busy 154 mov (a0),d0 159 mov d2,d1 172 mov L1_CACHE_BYTES,d1 176 mov d1,d0 197 mov d2,d1 199 mov 0x80000000,d0 # start from 31bit=1 202 mov d0,e0 205 mov d0,d1 213 mov d1,d0 216 mov d0,(DCPGMR) 219 mov a2,d0 221 mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCI 224 mov (a0),d0 265 mov PAGE_SIZE,d1 271 mov CHCTR,a0 284 mov L1_CACHE_BYTES,d2 296 mov d1,a1 300 mov ICIVCR,a0 303 mov (a0),d1 312 mov d2,d1 315 mov d1,(ICIVMR) 324 mov a2,d0 326 mov d0,(a0) 330 mov (a0),d1
|
H A D | cache-dbg-flush-by-tag.S | 46 mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address 47 mov DCACHE_PURGE(0,0),a1 # dcache purge request address 48 mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,e0 # total number of entries 51 mov (a0),d0 55 mov d0,(a1) # conditional purge 66 mov CHCTR,a0 96 mov d0,a1 99 mov DCACHE_PURGE(0,0),a0 107 mov a1,(L1_CACHE_WAYDISP*0,a0)
|
H A D | misalignment.c | 189 { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, 190 { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, 191 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, 192 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, 193 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, 194 { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, 195 { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, 196 { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}}, 197 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, 198 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, 199 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}}, 200 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}}, 201 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, 202 { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, 203 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, 204 { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, 205 { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, 206 { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, 207 { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, 208 { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, 209 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, 210 { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, 211 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, 212 { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, 213 { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, 214 { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, 215 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, 216 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, 217 { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, 218 { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, 219 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, 220 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, 221 { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, 222 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, 223 { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, 224 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, 225 { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, 226 { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, 227 { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, 228 { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, 229 { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, 230 { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, 231 { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, 232 { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, 233 { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, 234 { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, 235 { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, 236 { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, 237 { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, 238 { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, 239 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, 240 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, 241 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, 242 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, 243 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 244 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, 245 { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, 246 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 247 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, 248 { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, 249 { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, 250 { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, 251 { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, 252 { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, 485 if (pop->name[3] == 0 || /* "mov" */ misalignment() 504 kdebug("mov%u (%p),DARn", datasz, address); misalignment() 527 kdebug("mov%u %lx,(%p)", datasz, data, address); misalignment() 842 asm volatile("mov (%0),%1" : "+a"(q), "=d"(x)); test_misalignment() 848 asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x)); test_misalignment() 855 asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp)); test_misalignment() 862 asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y)); test_misalignment() 868 asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y)); test_misalignment() 874 asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y)); test_misalignment() 881 "mov +0x11,%0 \n" test_misalignment() 883 "mov +0x22,%0 \n" test_misalignment() 885 "mov +0x33,%0 \n" test_misalignment() 887 "mov +0x44,%0 \n" test_misalignment() 889 "mov (7,sp),%1 \n" test_misalignment() 897 "mov +0x11,%0 \n" test_misalignment() 899 "mov +0x22,%0 \n" test_misalignment() 901 "mov +0x33,%0 \n" test_misalignment() 903 "mov +0x55,%0 \n" test_misalignment() 905 "mov (259,sp),%1 \n" test_misalignment() 913 "mov +0x11,%0 \n" test_misalignment() 915 "mov +0x22,%0 \n" test_misalignment() 917 "mov +0x33,%0 \n" test_misalignment() 919 "mov +0x55,%0 \n" test_misalignment() 921 "mov (260,sp),%1 \n" test_misalignment() 933 "mov %2,%3 \n" test_misalignment() 934 "mov %1,%2 \n" test_misalignment() 949 "mov %1,%3 \n" test_misalignment() 950 "mov (%0+),%1 \n" test_misalignment()
|
H A D | cache-dbg-inv-by-tag.S | 37 mov CHCTR,a2 42 mov d0,a1 47 mov ICACHE_TAG(0,0),a0 48 mov a1,d0 55 mov L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_VALID,d1 71 mov (a0),d0 # read the tag in the way 0 slot 77 mov (a0),d0 # read the tag in the way 1 slot 83 mov (a0),d0 # read the tag in the way 2 slot 89 mov (a0),d0 # read the tag in the way 3 slot 95 mov d0,(a0) # kill the tag (D0 is 0 at this point)
|
H A D | cache-flush-by-tag.S | 59 mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address 60 mov DCACHE_PURGE(0,0),a1 # dcache purge request address 61 mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries 64 mov (a0),d0 68 mov d0,(a1) # conditional purge 96 mov PAGE_SIZE,d1 116 mov d0,a1 122 mov DCACHE_PURGE(0,0),a0 123 mov a1,d0 136 mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line 166 mov L1_CACHE_NENTRIES,d1 170 mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge 171 mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge 172 mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge 173 mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge 200 mov PAGE_SIZE,d1 219 mov d0,a1 226 mov DCACHE_PURGE(0,0),a0 227 mov a1,d0 237 mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line
|
H A D | cache-inv-by-tag.S | 68 mov CHCTR,a0 90 mov CHCTR,a0 119 mov PAGE_SIZE,d1 138 mov CHCTR,a2 149 mov d0,a1 156 mov DCACHE_TAG(0,0),a0 157 mov a1,d0 185 mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot 194 mov d2,(L1_CACHE_WAYDISP*0,a0) # kill the tag 199 mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot 208 mov d2,(L1_CACHE_WAYDISP*1,a0) # kill the tag 213 mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot 222 mov d2,(L1_CACHE_WAYDISP*2,a0) # kill the tag 227 mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot 236 mov d2,(L1_CACHE_WAYDISP*3,a0) # kill the tag
|
/linux-4.1.27/arch/x86/kernel/ |
H A D | vsyscall_emu_64.S | 21 mov $__NR_gettimeofday, %rax 26 mov $__NR_time, %rax 31 mov $__NR_getcpu, %rax
|
/linux-4.1.27/firmware/keyspan_pda/ |
H A D | xircom_pgs.S | 219 start: mov SP,STACK-1 ; set stack 222 mov tx_ring_in, a 223 mov tx_ring_out, a 224 mov rx_ring_in, a 225 mov rx_ring_out, a 226 mov tx_unthrottle_threshold, a 231 mov r1, 0 232 mov a, #0xfe 233 mov dptr, #tx_ring 239 mov a, #0xfd 240 mov dptr, #rx_ring 248 mov dptr, PORTBCFG 249 mov a, #0xBf 251 mov dptr, PORTCCFG 252 mov a, #0xef 256 mov a, #0x10 257 mov dptr,OEC 261 mov a, #0x00 262 mov dptr,OUTC 266 mov a, #0x40 267 mov dptr,OEB 271 mov a, #0x00 272 mov dptr,OUTB 276 mov a, #0x82 277 mov dptr,OEC 282 mov dptr, PORTCCFG 283 mov a, #0x03 288 mov dptr, USBBAV 293 mov a,#0x01 ; enable SUDAV: setup data available (for ep0) 294 mov dptr, USBIRQ 296 mov dptr, USBIEN 299 mov dptr, IN07IEN 300 mov a,#0x04 ; enable IN2 int 303 mov dptr, OUT07IEN 304 mov a,#0x04 ; enable OUT2 int 306 mov dptr, OUT2BC 309 ;; mov a, #0x84 ; turn on RTS, DTR 310 ;; mov dptr,OUTC 313 mov a, #0x7 ; turn on DTR 314 mov dptr,USBBAV 317 mov a, #0x20 ; turn on the RED led 318 mov dptr,OEA 321 mov a, #0x80 ; turn on RTS 322 mov dptr,OUTC 326 mov a,#0x53 ; mode 1, enable rx, clear int 327 mov SCON, a 339 mov T2CON, #030h ; rclk=1,tclk=1,cp=0,tr2=0(enable later) 340 mov r3, #5 343 mov SCON, #050h 346 mov r1, #0x40 347 mov a, #0x41 349 mov SBUF, a 368 mov a, #0 369 mov dps, a 370 mov dptr, USBCS 371 mov a, #0x02 ; DISCON=0, DISCOE=0, RENUM=1 374 mov r1, #46 376 mov r2, #0 378 mov r3, #0 383 mov a, #0x06 ; DISCON=0, DISCOE=1, RENUM=1 399 mov a,EXIF 401 mov EXIF,a ; clear INT2 first 402 mov dptr, USBIRQ ; clear USB int 403 mov a,#01h 407 mov dptr, SETUPDAT 409 mov r1, a ; r1 = bmRequestType 412 mov r2, a ; r2 = bRequest 415 mov r3, a ; r3 = wValueL 418 mov r4, a ; r4 = wValueH 421 mov a, r1 457 mov dptr, PORTCCFG 464 mov dptr, OUTC 468 mov dptr, PORTCCFG 482 mov a, tx_ring_out 489 mov a, tx_ring_in 498 mov tx_unthrottle_threshold, r3; wValue[0] is threshold value 515 mov dptr, IN0BUF 520 mov dptr, IN0BC 521 mov a, #2 568 mov dptr, SUDPTRH 569 mov a, #HIGH(desc_device) 571 mov dptr, SUDPTRL 572 mov a, #LOW(desc_device) 580 mov dptr, SUDPTRH 581 mov a, #HIGH(desc_config1) 583 mov dptr, SUDPTRL 584 mov a, #LOW(desc_config1) 591 mov a, #((desc_strings_end-desc_strings)/2) 596 mov a, r3 598 mov dptr, #desc_strings 600 mov dpl, a 601 mov a, #0 603 mov dph, a ; dph = desc_strings[a]. big endian! (handy) 616 mov r1, a 619 mov r2, a 620 mov dptr, SUDPTRH 621 mov a, r1 623 mov dptr, SUDPTRL 624 mov a, r2 636 mov a, #1 638 mov dptr, IN0BUF 640 mov a, #1 641 mov dptr, IN0BC 652 mov a, #0 664 mov dptr, EP0CS 665 mov a, #0x02 671 mov dptr, EP0CS 690 mov a, r3 695 mov a, r3 698 mov dpl, a 699 mov a, #HIGH(baud_table) 701 mov dph, a 706 mov RCAP2H, a 707 mov TH2, a 710 mov RCAP2L, a 711 mov TL2, a 725 mov a, r3 ; wValue[0] holds new bits: b7 is new RTS 728 mov r3, a 729 mov dptr, OUTC 736 mov dptr, PINSC 750 mov a,EXIF 752 mov EXIF,a ; clear INT2 first 753 mov dptr, IN07IRQ ; clear USB int 754 mov a,#04h 757 mov a, #0x20 ; Turn off the green LED 758 mov dptr,OEA 765 mov a, #0x20 ; Turn off the green LED 766 mov dptr,OEA 787 mov a, #0x10 ; Turn the green LED 788 mov dptr,OEA 793 mov a,EXIF 795 mov EXIF,a ; clear INT2 first 796 mov dptr, OUT07IRQ ; clear USB int 797 mov a,#04h 803 mov dptr, OUT2BC ; get byte count 805 mov r1, a 807 mov dps, a 808 mov dptr, OUT2BUF ; load DPTR0 with source 809 mov dph1, #HIGH(tx_ring) ; load DPTR1 with target 810 mov dpl1, tx_ring_in 816 mov a,dpl1 830 mov dptr,OUT2BC 837 mov a, #0x20 ; Turn off the green LED 838 mov dptr,OEA 857 mov dps, a 859 mov dptr, IN4CS 862 mov dptr, IN4BUF 864 mov a, tx_ring_in 867 mov a, tx_ring_out 871 mov a, rx_ring_in 874 mov a, rx_ring_out 886 mov dptr, #tx_ring ; DPTR1: source 887 mov r1, #16 898 mov a, #0xfc 904 mov dptr, #rx_ring ; DPTR1: source 905 mov r1, #16 917 mov dps, a 918 mov dptr, IN4BC 919 mov a, #38 931 mov a, tx_ring_in 937 mov dph, #HIGH(tx_ring) 938 mov dpl, tx_ring_out 940 mov sbuf, a 945 mov a, #0 952 mov a, tx_ring_out 960 mov tx_unthrottle_threshold, #0 993 mov dph, #HIGH(rx_ring) 994 mov dpl, rx_ring_in 996 mov a, sbuf 999 mov a, dpl 1011 mov a,#0x10 1012 mov dptr, OEA 1015 mov dptr, IN2CS 1021 mov a, rx_ring_in 1027 mov dps, a 1028 mov dph, #HIGH(rx_ring) ; load DPTR0 with source 1030 mov dptr, IN2BUF ; load DPTR1 with target 1035 mov r1, #1 ; INbuf size counter 1037 mov a, rx_ring_in 1042 mov dpl, rx_ring_out 1053 mov a, #0x10 ; Turn the green LED 1054 mov dptr,OEA 1056 mov dptr, IN2BC 1057 mov a, r1 1068 mov dps, a 1069 mov dptr, IN2BUF 1070 mov a, #1 1073 mov a, #2 1075 mov dptr, IN2BC 1081 mov SBUF, a
|
H A D | keyspan_pda.S | 217 start: mov SP,STACK-1 ; set stack 220 mov tx_ring_in, a 221 mov tx_ring_out, a 222 mov rx_ring_in, a 223 mov rx_ring_out, a 224 mov tx_unthrottle_threshold, a 229 mov r1, 0 230 mov a, #0xfe 231 mov dptr, #tx_ring 237 mov a, #0xfd 238 mov dptr, #rx_ring 246 mov a, #02H 247 mov dptr,OEB 250 mov a, #00H 251 mov dptr,OUTB 254 mov a, #0x86 255 mov dptr,OEC 258 mov dptr, PORTCCFG 259 mov a, #0x03 263 mov dptr, USBBAV 268 mov a,#0x01 ; enable SUDAV: setup data available (for ep0) 269 mov dptr, USBIRQ 271 mov dptr, USBIEN 274 mov dptr, IN07IEN 275 mov a,#0x04 ; enable IN2 int 278 mov dptr, OUT07IEN 279 mov a,#0x04 ; enable OUT2 int 281 mov dptr, OUT2BC 284 mov a, #0x84 ; turn on RTS, DTR 285 mov dptr,OUTC 288 mov a,#01010011 ; mode 1, enable rx, clear int 289 mov SCON, a 301 mov T2CON, #030h ; rclk=1,tclk=1,cp=0,tr2=0(enable later) 302 mov r3, #5 305 mov SCON, #050h 308 mov r1, #0x40 309 mov a, #0x41 311 mov SBUF, a 330 mov a, #0 331 mov dps, a 332 mov dptr, USBCS 333 mov a, #0x02 ; DISCON=0, DISCOE=0, RENUM=1 336 mov r1, #46 338 mov r2, #0 340 mov r3, #0 345 mov a, #0x06 ; DISCON=0, DISCOE=1, RENUM=1 361 mov a,EXIF 363 mov EXIF,a ; clear INT2 first 364 mov dptr, USBIRQ ; clear USB int 365 mov a,#01h 369 mov dptr, SETUPDAT 371 mov r1, a ; r1 = bmRequestType 374 mov r2, a ; r2 = bRequest 377 mov r3, a ; r3 = wValueL 380 mov r4, a ; r4 = wValueH 383 mov a, r1 419 mov dptr, PORTCCFG 426 mov dptr, OUTC 430 mov dptr, PORTCCFG 444 mov a, tx_ring_out 451 mov a, tx_ring_in 460 mov tx_unthrottle_threshold, r3; wValue[0] is threshold value 477 mov dptr, IN0BUF 482 mov dptr, IN0BC 483 mov a, #2 530 mov dptr, SUDPTRH 531 mov a, #HIGH(desc_device) 533 mov dptr, SUDPTRL 534 mov a, #LOW(desc_device) 542 mov dptr, SUDPTRH 543 mov a, #HIGH(desc_config1) 545 mov dptr, SUDPTRL 546 mov a, #LOW(desc_config1) 553 mov a, #((desc_strings_end-desc_strings)/2) 558 mov a, r3 560 mov dptr, #desc_strings 562 mov dpl, a 563 mov a, #0 565 mov dph, a ; dph = desc_strings[a]. big endian! (handy) 578 mov r1, a 581 mov r2, a 582 mov dptr, SUDPTRH 583 mov a, r1 585 mov dptr, SUDPTRL 586 mov a, r2 598 mov a, #1 600 mov dptr, IN0BUF 602 mov a, #1 603 mov dptr, IN0BC 614 mov a, #0 626 mov dptr, EP0CS 627 mov a, #0x02 633 mov dptr, EP0CS 652 mov a, r3 657 mov a, r3 660 mov dpl, a 661 mov a, #HIGH(baud_table) 663 mov dph, a 668 mov RCAP2H, a 669 mov TH2, a 672 mov RCAP2L, a 673 mov TL2, a 686 mov a, r3 ; wValue[0] holds new bits: b7 is new DTR, b2 is new RTS 689 mov r3, a 690 mov dptr, OUTC 697 mov dptr, PINSC 711 mov a,EXIF 713 mov EXIF,a ; clear INT2 first 714 mov dptr, IN07IRQ ; clear USB int 715 mov a,#04h 736 mov a,EXIF 738 mov EXIF,a ; clear INT2 first 739 mov dptr, OUT07IRQ ; clear USB int 740 mov a,#04h 746 mov dptr, OUT2BC ; get byte count 748 mov r1, a 750 mov dps, a 751 mov dptr, OUT2BUF ; load DPTR0 with source 752 mov dph1, #HIGH(tx_ring) ; load DPTR1 with target 753 mov dpl1, tx_ring_in 759 mov a,dpl1 773 mov dptr,OUT2BC 796 mov dps, a 798 mov dptr, IN4CS 801 mov dptr, IN4BUF 803 mov a, tx_ring_in 806 mov a, tx_ring_out 810 mov a, rx_ring_in 813 mov a, rx_ring_out 825 mov dptr, #tx_ring ; DPTR1: source 826 mov r1, #16 837 mov a, #0xfc 843 mov dptr, #rx_ring ; DPTR1: source 844 mov r1, #16 856 mov dps, a 857 mov dptr, IN4BC 858 mov a, #38 870 mov a, tx_ring_in 876 mov dph, #HIGH(tx_ring) 877 mov dpl, tx_ring_out 879 mov sbuf, a 884 mov a, #0 891 mov a, tx_ring_out 899 mov tx_unthrottle_threshold, #0 932 mov dph, #HIGH(rx_ring) 933 mov dpl, rx_ring_in 935 mov a, sbuf 938 mov a, dpl 950 mov dptr, IN2CS 956 mov a, rx_ring_in 962 mov dps, a 963 mov dph, #HIGH(rx_ring) ; load DPTR0 with source 965 mov dptr, IN2BUF ; load DPTR1 with target 970 mov r1, #1 ; INbuf size counter 972 mov a, rx_ring_in 977 mov dpl, rx_ring_out 988 mov dptr, IN2BC 989 mov a, r1 1000 mov dps, a 1001 mov dptr, IN2BUF 1002 mov a, #1 1005 mov a, #2 1007 mov dptr, IN2BC 1013 mov SBUF, a
|
/linux-4.1.27/arch/x86/um/ |
H A D | stub_32.S | 9 mov $(STUB_DATA+8), %esp 13 mov 0x0(%esp), %eax 17 mov %eax, STUB_DATA+4 22 mov %esp, STUB_DATA+4 48 mov %eax, STUB_DATA
|
H A D | stub_64.S | 19 mov $(STUB_DATA >> 32), %rbx 21 mov $(STUB_DATA & 0xffffffff), %rax 24 mov %rbx, %rsp 28 mov 0x0(%rsp), %rax 32 mov %rax, 8(%rbx) 37 mov %rsp, 8(%rbx) 63 mov %rax, (%rbx)
|
/linux-4.1.27/arch/mn10300/include/asm/ |
H A D | atomic.h | 54 "1: mov %4,(_AAR,%3) \n" \ 55 " mov (_ADR,%3),%1 \n" \ 57 " mov %1,(_ADR,%3) \n" \ 58 " mov (_ADR,%3),%0 \n" /* flush */ \ 59 " mov (_ASR,%3),%0 \n" \ 73 "1: mov %4,(_AAR,%3) \n" \ 74 " mov (_ADR,%3),%1 \n" \ 76 " mov %1,(_ADR,%3) \n" \ 77 " mov (_ADR,%3),%0 \n" /* flush */ \ 78 " mov (_ASR,%3),%0 \n" \ 143 "1: mov %3,(_AAR,%2) \n" atomic_clear_mask() 144 " mov (_ADR,%2),%0 \n" atomic_clear_mask() 146 " mov %0,(_ADR,%2) \n" atomic_clear_mask() 147 " mov (_ADR,%2),%0 \n" /* flush */ atomic_clear_mask() 148 " mov (_ASR,%2),%0 \n" atomic_clear_mask() 177 "1: mov %3,(_AAR,%2) \n" atomic_set_mask() 178 " mov (_ADR,%2),%0 \n" atomic_set_mask() 180 " mov %0,(_ADR,%2) \n" atomic_set_mask() 181 " mov (_ADR,%2),%0 \n" /* flush */ atomic_set_mask() 182 " mov (_ASR,%2),%0 \n" atomic_set_mask()
|
H A D | cmpxchg.h | 25 "1: mov %4,(_AAR,%3) \n" __xchg() 26 " mov (_ADR,%3),%1 \n" __xchg() 27 " mov %5,(_ADR,%3) \n" __xchg() 28 " mov (_ADR,%3),%0 \n" /* flush */ __xchg() 29 " mov (_ASR,%3),%0 \n" __xchg() 46 "1: mov %4,(_AAR,%3) \n" __cmpxchg() 47 " mov (_ADR,%3),%1 \n" __cmpxchg() 50 " mov %6,(_ADR,%3) \n" __cmpxchg() 51 "2: mov (_ADR,%3),%0 \n" /* flush */ __cmpxchg() 52 " mov (_ASR,%3),%0 \n" __cmpxchg()
|
H A D | rwlock.h | 35 " mov (%0),d3 \n" \ 37 " mov d3,(%0) \n" \ 54 " mov (%0),d3 \n" \ 56 " mov d3,(%0) \n" \ 81 " mov (%0),d3 \n" \ 83 " mov d3,(%0) \n" \ 100 " mov (%0),d3 \n" \ 102 " mov d3,(%0) \n" \
|
H A D | irqflags.h | 36 asm volatile("mov epsw,%0" : "=d"(flags)); arch_local_save_flags() 73 " mov epsw,%0 \n" arch_local_irq_enable() 76 " mov %0,epsw \n" arch_local_irq_enable() 85 " mov %0,epsw \n" arch_local_irq_restore() 179 mov epsw,reg 192 mov reg,epsw 195 mov epsw,reg; \
|
/linux-4.1.27/sound/oss/ |
H A D | vidc_fill.S | 20 mov ip, #0xff00 30 mov pc, lr 33 mov ip, #0xff00 44 mov pc, lr 47 mov ip, #0xff00 56 mov pc, lr 59 mov ip, #0xff00 70 mov pc, lr 73 mov ip, #0xff00 88 mov pc, lr 91 mov ip, #0xff00 102 mov pc, lr 105 mov r0, #0 106 mov r1, #0 107 2: mov r4, #0 108 mov r5, #0 112 mov pc, lr 115 mov r0, #0 116 mov r1, #0 144 mov ip, #IOMD_BASE & 0xff000000 153 mov lr, pc 154 mov pc, r4 @ Call fill routine (uses r4, ip) 157 mov r0, #0 164 mov r2, r2, lsl #20 170 mov ip, #IOMD_BASE & 0xff000000 185 mov r0, #0x10 188 mov r0, #1 @ IRQ_HANDLED 193 mov pc, lr
|
/linux-4.1.27/arch/ia64/hp/sim/boot/ |
H A D | boot_head.S | 42 mov r15=in4 49 mov r28=in0 50 mov b7=in1 60 mov r8=-1 61 mov r9=256 66 mov r9=512 74 mov r8=0 /* status = 0 */ 81 mov r8=0 /* status = 0 */ 88 mov r8=0 /* status = 0 */ 89 mov r9=96 /* num phys stacked */ 90 mov r10=0 /* hints */ 91 mov r11=0 95 mov r9=ar.lc 98 mov ar.lc=r8 108 mov ar.lc=r9 109 mov r8=r0 113 mov r8=0 /* status = 0 */ 115 mov r10=0 /* reserved */ 116 mov r11=0 /* reserved */ 117 mov r16=0xffff /* implemented PMC */ 118 mov r17=0x3ffff /* implemented PMD */ 129 mov r16=0xf0 /* cycles count capable PMC */ 133 mov r17=0xf0 /* retired bundles capable PMC */ 149 mov r8=0 /* status = 0 */ 158 mov r8=0 /* status = 0 */ 159 mov r9=0x80|0x01 /* NatPage|WB */
|
/linux-4.1.27/arch/sparc/mm/ |
H A D | ultra.S | 38 mov 0x50, %g3 62 mov SECONDARY_CONTEXT, %o4 90 mov SECONDARY_CONTEXT, %o4 217 mov PRIMARY_CONTEXT, %o2 218 mov 0x40, %g3 239 mov PRIMARY_CONTEXT, %o4 265 mov PRIMARY_CONTEXT, %o4 306 mov %i0, %o0 308 mov %i1, %o1 313 mov %o0, %o2 /* ARG2: mmu context */ 314 mov 0, %o0 /* ARG0: CPU lists unimplemented */ 315 mov 0, %o1 /* ARG1: CPU lists unimplemented */ 316 mov HV_MMU_ALL, %o3 /* ARG3: flags */ 317 mov HV_FAST_MMU_DEMAP_CTX, %o5 320 mov HV_FAST_MMU_DEMAP_CTX, %o1 326 mov %o0, %g2 327 mov %o1, %o0 /* ARG0: vaddr + IMMU-bit */ 328 mov %g2, %o1 /* ARG1: mmu context */ 329 mov HV_MMU_ALL, %o2 /* ARG2: flags */ 334 mov HV_MMU_UNMAP_ADDR_TRAP, %o1 341 mov %o2, %g2 342 mov %o0, %g3 345 mov %g3, %o1 /* ARG1: mmu context */ 346 mov HV_MMU_ALL, %o2 /* ARG2: flags */ 351 mov HV_MMU_UNMAP_ADDR_TRAP, %o1 362 mov %o0, %g1 366 mov 0, %o1 /* ARG1: mmu context */ 367 mov HV_MMU_ALL, %o2 /* ARG2: flags */ 370 mov HV_MMU_UNMAP_ADDR_TRAP, %o1 406 mov 19, %o2 413 mov 22, %o2 420 mov 27, %o2 428 mov 11, %o2 451 mov PRIMARY_CONTEXT, %g2 457 mov 0x40, %g4 476 mov PRIMARY_CONTEXT, %g4 481 mov PRIMARY_CONTEXT, %g4 569 mov %i7, %g7 603 mov 0x08, %g3 606 mov 0x10, %g3 609 mov 0x18, %g3 613 mov %o0, %g2 614 mov %o1, %g3 615 mov %o5, %g7 617 mov HV_FAST_VT_GET_PERFREG, %o5 618 mov 3, %o0 621 mov HV_FAST_VT_GET_PERFREG, %o5 622 mov 2, %o0 625 mov HV_FAST_VT_GET_PERFREG, %o5 626 mov 1, %o0 629 mov HV_FAST_VT_GET_PERFREG, %o5 630 mov 0, %o0 634 mov %g2, %o0 635 mov %g3, %o1 636 mov %g7, %o5 693 mov %g5, %g4 694 mov %g6, %g5 697 mov %l4, %o0 699 mov %l5, %o1 705 mov %o0, %g2 706 mov %o1, %g3 707 mov %o2, %g4 708 mov %o3, %g1 709 mov %o5, %g7 712 mov %g5, %o2 /* ARG2: mmu context */ 713 mov HV_MMU_ALL, %o3 /* ARG3: flags */ 714 mov HV_FAST_MMU_DEMAP_CTX, %o5 716 mov HV_FAST_MMU_DEMAP_CTX, %g6 718 mov %o0, %g5 719 mov %g2, %o0 720 mov %g3, %o1 721 mov %g4, %o2 722 mov %g1, %o3 723 mov %g7, %o5 730 mov %o0, %g2 731 mov %o1, %g3 732 mov %o2, %g4 733 mov %g1, %o0 /* ARG0: virtual address */ 734 mov %g5, %o1 /* ARG1: mmu context */ 735 mov HV_MMU_ALL, %o2 /* ARG2: flags */ 739 mov HV_MMU_UNMAP_ADDR_TRAP, %g6 741 mov %o0, %g5 742 mov %g2, %o0 743 mov %g3, %o1 744 mov %g4, %o2 758 mov %o0, %g2 759 mov %o1, %g4 760 mov %o2, %g7 762 mov 0, %o1 /* ARG1: mmu context */ 763 mov HV_MMU_ALL, %o2 /* ARG2: flags */ 765 mov HV_MMU_UNMAP_ADDR_TRAP, %g6 767 mov %o0, %g5 771 mov %g2, %o0 772 mov %g4, %o1 773 mov %g7, %o2 822 mov 10, %o2 829 mov 11, %o2 836 mov 16, %o2 843 mov 16, %o2 851 mov 2, %o2 860 mov 21, %o2 867 mov 17, %o2 874 mov 25, %o2
|
H A D | hypersparc.S | 126 mov SRMMU_CTX_REG, %g7 135 mov %o0, %o2 153 mov SRMMU_FAULT_STATUS, %g5 155 mov SRMMU_CTX_REG, %g7 176 mov SRMMU_CTX_REG, %o3 207 mov SRMMU_FAULT_STATUS, %g7 208 mov SRMMU_CTX_REG, %g4 252 mov SRMMU_FAULT_STATUS, %g1 266 mov 0x400, %g1 272 mov SRMMU_CTX_REG, %g1 279 mov 0x300, %g2 288 mov SRMMU_CTX_REG, %g1 311 mov SRMMU_CTX_REG, %g1 331 mov 32, %g2 332 mov 64, %g3 333 mov 96, %g4 334 mov 128, %g5 335 mov 160, %g7 336 mov 192, %o2 337 mov 224, %o3 338 mov 16, %o1 358 mov 16, %g1
|
/linux-4.1.27/arch/sparc/kernel/ |
H A D | hvtramp.S | 46 mov %o0, %l0 49 mov SCRATCHPAD_CPUID, %g2 55 mov 0, %l1 62 mov HV_MMU_IMMU | HV_MMU_DMMU, %o3 63 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 75 mov HV_FAST_MMU_FAULT_AREA_CONF, %o5 85 mov 1, %o0 87 mov HV_FAST_MMU_ENABLE, %o5 97 mov PRIMARY_CONTEXT, %g7 101 mov SECONDARY_CONTEXT, %g7 105 mov %l6, %g6 108 mov 1, %g5 122 mov %g6, %o0
|
H A D | misctrap.S | 13 mov TLB_SFSR, %g3 33 mov TLB_SFSR, %g3 34 mov DMMU_SFAR, %g4 45 mov %l4, %o1 46 mov %l5, %o2 56 mov TLB_SFSR, %g4 60 mov DMMU_SFAR, %g4 64 mov %l4, %o1 65 mov %l5, %o2 75 mov TLB_SFSR, %g4 79 mov DMMU_SFAR, %g4 83 mov %l4, %o1 84 mov %l5, %o2
|
H A D | sun4v_tlb_miss.S | 37 mov 512, TMP2; \ 51 mov SCRATCHPAD_UTSBREG1, %g1 62 mov FAULT_CODE_ITLB, %g3 65 mov FAULT_CODE_ITLB, %g3 75 mov %o0, %g1 ! save %o0 76 mov %o1, %g2 ! save %o1 77 mov %o2, %g5 ! save %o2 78 mov %o3, %g7 ! save %o3 79 mov %g4, %o0 ! vaddr 81 mov %g3, %o2 ! PTE 82 mov HV_MMU_IMMU, %o3 ! flags 85 mov %g2, %o1 ! restore %o1 86 mov %g1, %o0 ! restore %o0 87 mov %g5, %o2 ! restore %o2 88 mov %g7, %o3 ! restore %o3 97 mov SCRATCHPAD_UTSBREG1, %g1 108 mov FAULT_CODE_DTLB, %g3 118 mov %o0, %g1 ! save %o0 119 mov %o1, %g2 ! save %o1 120 mov %o2, %g5 ! save %o2 121 mov %o3, %g7 ! save %o3 122 mov %g4, %o0 ! vaddr 124 mov %g3, %o2 ! PTE 125 mov HV_MMU_DMMU, %o3 ! flags 128 mov %g2, %o1 ! restore %o1 129 mov %g1, %o0 ! restore %o0 130 mov %g5, %o2 ! restore %o2 131 mov %g7, %o3 ! restore %o3 145 mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4 155 mov SCRATCHPAD_UTSBREG1, %g1 158 mov FAULT_CODE_ITLB, %g3 167 mov SCRATCHPAD_UTSBREG1, %g1 170 mov FAULT_CODE_DTLB, %g3 180 mov SCRATCHPAD_UTSBREG2, %g5 218 mov %l4, %o1 245 mov %l4, %o1 268 mov %l4, %o1 269 mov %l5, %o2 284 mov %l4, %o1 285 mov %l5, %o2 300 mov %l4, %o1 301 mov %l5, %o2 316 mov %l4, %o1 317 mov %l5, %o2 333 mov HV_FAULT_TYPE_UNALIGNED, %g3 342 mov HV_FAULT_TYPE_UNALIGNED, %g3 350 mov %l4, %o1 351 mov %l5, %o2 374 mov %l4, %o1 375 mov %l5, %o2 390 mov %l4, %o1 391 mov %l5, %o2
|
H A D | spiterrs.S | 16 mov UDBE_UE, %g1 32 mov 1, %g3 61 1: mov 0x18, %g3 69 mov 0x18, %g7 99 mov %l4, %o1 100 mov %l5, %o2 136 mov 1, %g3 154 mov UDBE_CE, %g1 161 mov TLB_SFSR, %g3 162 mov DMMU_SFAR, %g5 178 mov %l4, %o1 179 mov %l5, %o2 190 mov TLB_SFSR, %g3 191 mov DMMU_SFAR, %g5 199 mov %l4, %o1 200 mov %l5, %o2 211 mov TLB_SFSR, %g3 219 mov %l4, %o1 220 mov %l5, %o2 231 mov TLB_SFSR, %g3 239 mov %l4, %o1 240 mov %l5, %o2
|
H A D | syscalls.S | 16 mov %g0, %o2 41 mov %i6, %o2 103 mov SIGCHLD, %o0 107 mov 0, %o3 116 mov %g7, %o0 124 mov 0, %o0 160 mov -ENOSYS, %o0 172 mov -ENOSYS, %o0 173 mov %i0, %o0 174 mov %i1, %o1 175 mov %i2, %o2 176 mov %i3, %o3 178 mov %i4, %o4 199 mov %i0, %l5 ! IEU1 212 mov %i0, %o0 ! IEU0 214 mov %i1, %o1 ! IEU1 216 4: mov %i2, %o2 ! IEU0 Group 219 mov %i3, %o3 ! IEU1 220 mov %i4, %o4 ! IEU0 Group 223 mov %i0, %l5 ! IEU0 225 mov %i5, %o5 ! IEU0 231 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
|
H A D | entry.S | 184 mov 11, %o0 ! floppy irq level (unused anyway) 185 mov %g0, %o1 ! devid is not used in fast interrupts 203 mov %l7, %o1 ! trap number 232 mov %l7, %o0 ! irq level 446 mov %l1, %o1 447 mov %l2, %o2 449 mov %l0, %o3 466 mov %l1, %o1 467 mov %l2, %o2 469 mov %l0, %o3 514 mov %l1, %o1 515 mov %l2, %o2 517 mov %l0, %o3 553 mov %l1, %o1 554 mov %l2, %o2 556 mov %l0, %o3 570 mov %l1, %o1 571 mov %l2, %o2 573 mov %l0, %o3 587 mov %l1, %o1 588 mov %l2, %o2 590 mov %l0, %o3 604 mov %l1, %o1 605 mov %l2, %o2 607 mov %l0, %o3 621 mov %l1, %o1 622 mov %l2, %o2 624 mov %l0, %o3 638 mov %l1, %o1 639 mov %l2, %o2 641 mov %l0, %o3 655 mov %l1, %o1 656 mov %l2, %o2 658 mov %l0, %o3 767 mov 0x400, %l5 768 mov 0x300, %l4 786 mov %l7, %o1 787 mov %l7, %o2 789 mov %l7, %o3 804 mov %o7, %l5 807 mov %l5, %o7 817 mov %o7, %l5 820 mov %l5, %o7 825 mov %o7, %l5 826 mov %fp, %o2 828 mov %l5, %o7 842 mov 1, %o1 863 mov 1, %o1 879 mov %o7, %l5 885 mov SIGCHLD, %o0 ! arg0: clone flags 888 mov %fp, %o1 ! arg1: usp 891 mov 0, %o3 893 mov %l5, %o7 898 mov %o7, %l5 910 mov %fp, %o1 ! yes, use callers usp 915 mov 0, %o3 917 mov %l5, %o7 931 mov %fp, %o1 934 mov 0, %o3 947 mov 0, %o1 950 mov -ENOSYS, %o0 951 mov %i0, %o0 952 mov %i1, %o1 953 mov %i2, %o2 954 mov %i3, %o3 956 mov %i4, %o4 980 mov 0, %o0 999 mov %i0, %o0 1000 mov %i1, %o1 1001 mov %i2, %o2 1004 mov %i3, %o3 1006 mov %i4, %o4 1008 mov %i0, %l5 1011 mov %i5, %o5 1041 mov 1, %l6 1052 mov 1, %o1 1073 mov 0, %g2 1154 mov %i0, %o0 ! round multiplier up so large ns ok 1155 mov 0x1ae, %o1 ! 2**32 / (1 000 000 000 / HZ) 1158 mov %i1, %o1 ! udelay_val 1162 mov %o1, %o0 ! >>32 later for better resolution 1167 mov %i0, %o0 1172 mov %i1, %o1 ! udelay_val 1181 mov HZ, %o0 ! >>32 earlier for wider range 1233 mov 1, %g1 ! signal EFAULT condition 1301 mov PCI_SYS_INT_PENDING_CLEAR_ALL, %o1
|
H A D | head_64.S | 86 mov %o4, %l7 164 mov (1b - prom_peer_name), %l1 166 mov 0, %l2 170 mov 1, %l3 179 mov (1b - prom_root_node), %l1 183 mov (1b - prom_getprop_name), %l1 184 mov (1b - prom_compatible_name), %l2 185 mov (1b - prom_root_compatible), %l5 194 mov 4, %l3 196 mov 1, %l3 201 mov 64, %l3 207 mov (1b - prom_finddev_name), %l1 208 mov (1b - prom_chosen_path), %l2 209 mov (1b - prom_boot_mapped_pc), %l3 218 mov 1, %l3 228 mov (1b - prom_getprop_name), %l1 229 mov (1b - prom_mmu_name), %l2 230 mov (1b - prom_mmu_ihandle_cache), %l5 237 mov 4, %l3 239 mov 1, %l3 244 mov 4, %l3 250 mov (1b - prom_callmethod_name), %l1 251 mov (1b - prom_translate_name), %l2 257 mov 3, %l3 259 mov 5, %l3 276 mov (1b - prom_boot_mapping_mode), %l4 279 mov (1b - prom_boot_mapping_phys_high), %l4 290 mov 7, %l3 292 mov 1, %l3 294 mov (1b - prom_map_name), %l3 298 mov -1, %l3 309 mov (1b - prom_boot_mapping_phys_low), %l3 322 mov 5, %g3 334 mov 1, %g7 338 mov (1b - prom_finddev_name), %l1 339 mov (1b - prom_cpu_path), %l2 345 mov 1, %l3 355 mov (1b - prom_getprop_name), %l1 356 mov (1b - prom_compatible_name), %l2 357 mov (1b - prom_cpu_compatible), %l5 366 mov 4, %l3 368 mov 1, %l3 373 mov 64, %l3 385 mov 17, %g3 401 mov 6, %g3 423 mov SUN4V_CHIP_NIAGARA3, %g4 426 mov SUN4V_CHIP_NIAGARA4, %g4 429 mov SUN4V_CHIP_NIAGARA5, %g4 432 mov SUN4V_CHIP_SPARC_M6, %g4 435 mov SUN4V_CHIP_SPARC_M7, %g4 444 mov SUN4V_CHIP_NIAGARA1, %g4 447 mov SUN4V_CHIP_NIAGARA2, %g4 455 mov 9, %g3 464 mov SUN4V_CHIP_SPARC64X, %g4 469 mov SUN4V_CHIP_UNKNOWN, %g4 487 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 498 mov TSB_EXTENSION_P, %g3 503 mov TSB_EXTENSION_S, %g3 507 mov TSB_EXTENSION_N, %g3 518 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1 543 mov PRIMARY_CONTEXT, %g7 547 mov SECONDARY_CONTEXT, %g7 556 mov PRIMARY_CONTEXT, %g7 560 mov SECONDARY_CONTEXT, %g7 573 mov 3, %g2 /* Set TLB type to hypervisor. */ 646 mov 2, %g2 /* Set TLB type to cheetah+. */ 649 mov 1, %g2 /* Set TLB type to cheetah. */ 667 mov 0, %g2 677 mov 1, %g1 708 mov %l7, %o0 ! OpenPROM cif handler 773 mov 2, %g2 775 mov 0, %g2 791 mov 1, %g2 793 mov 0, %g2 806 mov PRIMARY_CONTEXT, %g1 941 mov -EFAULT, %o0 946 mov 1, %o0 958 mov 1, %o0 963 mov %o1, %o0
|
H A D | trampoline_64.S | 55 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 67 mov TSB_EXTENSION_P, %g3 72 mov TSB_EXTENSION_S, %g3 76 mov TSB_EXTENSION_N, %g3 92 mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1 97 mov %o0, %l0 135 mov 15, %l7 138 mov 63, %l7 146 mov 5, %g2 148 mov 1, %g2 179 mov 5, %g2 181 mov 1, %g2 228 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 233 mov HV_MMU_IMMU, %o3 236 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 241 mov HV_MMU_DMMU, %o3 255 mov PRIMARY_CONTEXT, %g7 264 mov SECONDARY_CONTEXT, %g7 287 mov 0, %fp 315 mov PRIMARY_CONTEXT, %g1 361 mov 2, %g2 363 mov 0, %g2 379 mov 1, %g2 381 mov 0, %g2 396 mov 1, %g5
|
H A D | ivec.S | 15 mov 0x40, %g3 37 mov 0x50, %g1 41 mov 0x60, %g7
|
H A D | sun4v_ivec.S | 17 mov INTRQ_CPU_MONDO_HEAD, %g2 19 mov INTRQ_CPU_MONDO_TAIL, %g4 53 mov INTRQ_CPU_MONDO_HEAD, %g4 65 mov INTRQ_DEVICE_MONDO_HEAD, %g2 67 mov INTRQ_DEVICE_MONDO_TAIL, %g4 95 mov INTRQ_DEVICE_MONDO_HEAD, %g4 123 mov INTRQ_RESUM_MONDO_HEAD, %g2 125 mov INTRQ_RESUM_MONDO_TAIL, %g4 149 mov %g2, %g1 180 mov INTRQ_RESUM_MONDO_HEAD, %g4 190 mov %g1, %g4 200 mov %l4, %o1 214 mov INTRQ_RESUM_MONDO_HEAD, %g2 234 mov INTRQ_NONRESUM_MONDO_HEAD, %g2 236 mov INTRQ_NONRESUM_MONDO_TAIL, %g4 260 mov %g2, %g1 291 mov INTRQ_NONRESUM_MONDO_HEAD, %g4 301 mov %g1, %g4 311 mov %l4, %o1 325 mov INTRQ_NONRESUM_MONDO_HEAD, %g2
|
H A D | tsb.S | 31 mov TLB_TAG_ACCESS, %g4 36 mov TLB_TAG_ACCESS, %g4 58 mov SCRATCHPAD_UTSBREG2, %g5 73 mov %g6, %g2 75 mov 512, %g7 87 mov %g7, %g5 120 mov _PAGE_SZALL_4V, %g7 130 mov _PAGE_SZHUGE_4V, %g7 168 mov %g3, %g4 218 mov %g5, %g3 254 mov %g5, %g3 279 661: mov TLB_TAG_ACCESS, %g4 288 mov FAULT_CODE_DTLB, %g4 295 mov FAULT_CODE_ITLB, %g4 352 mov 1, %o3 388 mov -1, %g3 401 mov SCRATCHPAD_UTSBREG1, %o5 403 mov SCRATCHPAD_UTSBREG2, %o5 406 mov 2, %o0 410 mov HV_FAST_MMU_TSB_CTXNON0, %o5 411 mov %o3, %o1 419 50: mov TSB_REG, %o5 430 mov TLB_TAG_ACCESS, %g3 443 mov TLB_TAG_ACCESS, %g3 520 mov 1, %g1 557 mov 1, %g1
|
/linux-4.1.27/arch/xtensa/include/asm/ |
H A D | traps.h | 37 " mov a12, a12\n" spill_registers() 47 " mov a12, a0\n" spill_registers() 51 " mov a12, a12\n" spill_registers() 53 " mov a4, a4\n" spill_registers() 55 " mov a8, a8\n" spill_registers() 63 " mov a12, a12\n" spill_registers()
|
H A D | ftrace.h | 18 "mov %0, a0\n" \ 19 "mov %1, a1\n" \
|
/linux-4.1.27/arch/arm/lib/ |
H A D | ecard.S | 26 mov r11, r1 27 mov r1, r0 29 mov lr, pc 30 mov pc, r2 39 mov r11, r0 41 mov lr, pc
|
H A D | bitops.h | 10 mov r2, #1 12 mov r0, r0, lsr #5 19 mov r3, r2, lsl r3 35 mov r2, #1 37 mov r0, r0, lsr #5 39 mov r3, r2, lsl r3 @ create mask 66 mov r0, r0, lsr #5 67 mov r3, #1 68 mov r3, r3, lsl r2 93 mov r0, r0, lsr #5 96 mov r0, #1
|
H A D | csumpartialcopygeneric.S | 26 .Lzero: mov r0, sum 143 mov r5, r4, get_byte_0 147 mov r5, r4, get_byte_1 149 mov r5, r4, get_byte_2 175 mov r4, r5, lspull #8 @ C = 0 180 mov r5, r5, lspull #8 182 mov r6, r6, lspull #8 184 mov r7, r7, lspull #8 191 mov r4, r8, lspull #8 201 mov r5, r5, lspull #8 206 mov r4, r6, lspull #8 213 mov r4, r5, lspull #8 216 mov r5, r4, get_byte_0 221 mov r5, r4, get_byte_1 223 mov r5, r4, get_byte_2 226 .Lsrc2_aligned: mov r4, r5, lspull #16 232 mov r5, r5, lspull #16 234 mov r6, r6, lspull #16 236 mov r7, r7, lspull #16 243 mov r4, r8, lspull #16 253 mov r5, r5, lspull #16 258 mov r4, r6, lspull #16 265 mov r4, r5, lspull #16 268 mov r5, r4, get_byte_0 273 mov r5, r4, get_byte_1 280 .Lsrc3_aligned: mov r4, r5, lspull #24 286 mov r5, r5, lspull #24 288 mov r6, r6, lspull #24 290 mov r7, r7, lspull #24 297 mov r4, r8, lspull #24 307 mov r5, r5, lspull #24 312 mov r4, r6, lspull #24 319 mov r4, r5, lspull #24 322 mov r5, r4, get_byte_0 328 mov r5, r4, get_byte_0 331 mov r5, r4, get_byte_1
|
H A D | getuser.S | 38 mov r0, #0 58 mov r0, #0 65 mov r0, #0 78 mov r0, #0 91 mov r0, #0 98 mov r0, #0 114 mov r0, #0 121 mov r0, #0 127 mov r3, #0 129 mov r2, #0 130 mov r0, #-EFAULT
|
H A D | div64.S | 59 mov yh, #0 71 mov ip, #1 72 mov ip, ip, lsl yl 73 mov yl, r4, lsl yl 77 mov yl, r4 78 mov ip, #1 93 mov yl, yl, lsr #1 98 mov yl, #0 106 mov ip, #0x80000000 130 mov xl, xl, lsl xh 131 mov ip, ip, lsr xh 136 mov ip, ip, lsr #1 146 mov xh, #1 160 mov yl, r4 162 mov ip, #0 180 mov yh, xh, lsr ip 181 mov yl, xl, lsr ip 186 mov xh, xl, lsl ip 187 mov xh, xh, lsr ip 206 mov yl, #0 207 mov yh, #0 208 mov xh, #0
|
H A D | backtrace.S | 57 * mov ip, sp 73 subne r0, sv_pc, #4 @ allow for mov 74 subeq r0, sv_pc, #8 @ allow for mov + stmia 77 mov r2, frame 98 mov frame, sv_fp @ above the current frame 102 mov r1, frame 120 mov stack, r0 121 mov instr, r1 122 mov reg, #10 123 mov r7, #0 124 1: mov r3, #1 135 mov r1, reg
|
H A D | putuser.S | 38 mov r0, #0 44 mov ip, r2, lsr #8 62 mov r0, #0 69 mov r0, #0 82 mov r0, #0 87 mov r0, #-EFAULT
|
H A D | io-writesw-armv4.S | 16 mov \rd, \rd, lsr #16 19 mov lr, \rd, lsr #16 87 1: mov ip, r3, lsr #8 89 2: mov ip, r3, pull_hbyte0
|
/linux-4.1.27/arch/x86/include/asm/ |
H A D | debugreg.h | 26 asm("mov %%db0, %0" :"=r" (val)); native_get_debugreg() 29 asm("mov %%db1, %0" :"=r" (val)); native_get_debugreg() 32 asm("mov %%db2, %0" :"=r" (val)); native_get_debugreg() 35 asm("mov %%db3, %0" :"=r" (val)); native_get_debugreg() 38 asm("mov %%db6, %0" :"=r" (val)); native_get_debugreg() 41 asm("mov %%db7, %0" :"=r" (val)); native_get_debugreg() 53 asm("mov %0, %%db0" ::"r" (value)); native_set_debugreg() 56 asm("mov %0, %%db1" ::"r" (value)); native_set_debugreg() 59 asm("mov %0, %%db2" ::"r" (value)); native_set_debugreg() 62 asm("mov %0, %%db3" ::"r" (value)); native_set_debugreg() 65 asm("mov %0, %%db6" ::"r" (value)); native_set_debugreg() 68 asm("mov %0, %%db7" ::"r" (value)); native_set_debugreg()
|
H A D | apm.h | 14 "mov %%dx, %%ds\n\t" \ 15 "mov %%dx, %%es\n\t" \ 16 "mov %%dx, %%fs\n\t" \ 17 "mov %%dx, %%gs\n\t"
|
/linux-4.1.27/arch/avr32/mm/ |
H A D | clear_page.S | 20 mov r10, 0 21 mov r11, 0 25 mov pc, lr
|
/linux-4.1.27/arch/ia64/lib/ |
H A D | copy_page.S | 47 mov saved_lc=ar.lc 48 mov ar.ec=PIPE_DEPTH 50 mov lcount=PAGE_SIZE/64-1 52 mov saved_pr=pr 53 mov pr.rot=1<<16 57 mov src1=in1 59 mov tgt_last = PAGE_SIZE 63 mov ar.lc=lcount 64 mov tgt1=in0 94 mov pr=saved_pr,0xffffffffffff0000 // restore predicates 95 mov ar.pfs=saved_pfs 96 mov ar.lc=saved_lc
|
H A D | memcpy_mck.S | 76 mov f6=f0 77 mov retval=in0 86 mov f6=f1 87 mov saved_in0=in0 // save dest pointer 88 mov saved_in1=in1 // save src pointer 89 mov retval=r0 // initialize return value 97 mov saved_in2=in2 // save len 112 mov saved_pr=pr 119 mov saved_lc=ar.lc 125 (p7) mov ar.lc=cnt // prefetch count 126 (p8) mov ar.lc=r0 147 mov ar.lc=cnt // loop setup 149 mov ar.ec=2 168 mov ar.lc=saved_lc 169 mov ar.pfs=saved_pfs 182 mov pr=saved_pr,-1 191 mov src_pre_mem = src0 192 mov pr.rot = 0x10000 193 mov ar.ec = 1 // special unrolled loop 195 mov dst_pre_mem = dst0 201 mov ar.lc = 2*PREFETCH_DIST - 1 216 mov ar.lc = cnt 217 mov ar.ec = N // # of stages in pipeline 264 mov in2=tmp 280 mov saved_lc=ar.lc 282 mov saved_pr=pr 285 mov saved_in0=dst0 // need to save all input arguments 286 mov saved_in2=in2 287 mov blocksize=BLOCK_SIZE 290 mov saved_in1=src0 292 (p6) mov in2=blocksize 306 (p7) mov ar.lc = cnt 307 (p8) mov ar.lc = r0 334 mov r29=ip // jmp_table thread 335 mov ar.lc=cnt 339 mov ar.ec=2 // loop setup 344 mov b6=r29 // jmp_table thread 394 mov ar.pfs=saved_pfs 396 mov ar.lc=saved_lc 397 mov pr=saved_pr,-1 398 mov in2=curlen // remaining length 399 mov dst0=dst1 // dest pointer 573 mov src1=src_pre_mem 574 mov dst1=dst_pre_mem 579 (p11) mov src0=saved_in1 581 (p13) mov dst0=saved_in0 587 mov src1=src_pre_mem 588 mov dst1=dst_pre_mem 590 mov pr=saved_pr,-1 // first restore pr, lc, and pfs 591 mov ar.lc=saved_lc 592 mov ar.pfs=saved_pfs 599 mov tmp = dst0 601 (p11) mov src1 = src0 // pick the larger of the two 602 (p13) mov dst0 = dst1 // make dst0 the smaller one 603 (p13) mov dst1 = tmp // and dst1 the larger one 610 mov retval=saved_in2 633 (p8) mov A = 0; // A shouldn't be negative, cap it 640 (p6) mov memset_arg2=0 // copy_to_user should not call memset 641 (p7) mov memset_arg2=D // copy_from_user need to have kbuf zeroed 642 mov r8=0 643 mov saved_retval = D 644 mov saved_rtlink = b0 648 mov out2=C 654 mov out0=memset_arg0 // *s 655 mov out1=r0 // c 656 mov out2=memset_arg2 // n 660 mov retval=saved_retval 661 mov ar.pfs=saved_pfs_stack 662 mov b0=saved_rtlink
|
H A D | memcpy.S | 51 mov saved_lc=ar.lc 57 mov saved_pr=pr 62 mov retval=in0 // return dst 66 mov dst=in0 // copy because of rotation 68 mov pr.rot=1<<16 73 mov ar.ec=N 77 mov ar.lc=cnt 81 mov src=in1 // copy because of rotation 106 mov ar.lc=saved_lc 107 mov pr=saved_pr,-1 108 mov ar.pfs=saved_pfs 120 mov ar.ec=MEM_LAT 123 mov ar.lc=cnt 149 mov ar.lc=saved_lc 150 mov pr=saved_pr,-1 151 mov ar.pfs=saved_pfs 200 mov pr=t4,0x38 // (p5,p4,p3)=(dst & 7) 203 mov cnt=r0 223 mov t4=ip 227 mov ar.ec=N 242 mov pr=cnt,0x38 // set (p5,p4,p3) to # of bytes last-word bytes to copy 243 mov ar.lc=t2 253 mov b6=t4 262 mov ar.lc=saved_lc 266 mov ar.pfs=saved_pfs 269 mov pr=saved_pr,-1
|
H A D | clear_page.S | 35 mov r16 = PAGE_SIZE/L3_LINE_SIZE-1 // main loop count, -1=repeat/until 37 mov saved_lc = ar.lc 40 mov ar.lc = (PREFETCH_LINES - 1) 41 mov dst_fetch = in0 50 mov ar.lc = r16 // one L3 line per iteration 74 mov ar.lc = saved_lc // restore lc
|
H A D | copy_user.S | 82 mov ret0=r0 87 mov saved_lc=ar.lc // preserve ar.lc (slow) 93 mov saved_pr=pr // preserve predicates 97 mov dst1=dst // copy because of rotation 98 mov ar.ec=PIPE_DEPTH 99 mov pr.rot=1<<16 // p16=true all others are false 101 mov src1=src // copy because of rotation 102 mov ar.lc=len2 // initialize lc for small count 117 mov ar.lc=saved_lc 118 mov pr=saved_pr,0xffffffffffff0000 119 mov ar.pfs=saved_pfs // restore ar.ec 159 mov t2=src2 190 mov ar.ec=PIPE_DEPTH 191 mov pr.rot=1<<16 // p16=true all others are false 192 mov ar.lc=cnt 216 mov ar.lc=cnt 217 mov ar.ec=PIPE_DEPTH 218 mov pr.rot=1<<16 // p16=true all others are false 242 (p16) mov val1[0]=r0; \ 250 (p16) mov val1[1]=r0; \ 251 (p16) mov val1[0]=r0; \ 301 mov ar.ec=PIPE_DEPTH 302 mov pr.rot=1<<16 // p16=true all others are false 303 mov ar.lc=len1 310 mov ar.lc=saved_lc 311 mov pr=saved_pr,0xffffffffffff0000 312 mov ar.pfs=saved_pfs 323 mov len1=len // copy because of rotation 369 mov ar.lc=tmp 401 mov ar.lc=saved_lc 404 mov pr=saved_pr,0xffffffffffff0000 407 mov ar.pfs=saved_pfs 433 // We simply replace the load with a simple mov and keep the 440 (p16) mov val1[0]=r0 444 mov pr=saved_pr,0xffffffffffff0000 445 mov ar.lc=saved_lc 446 mov ar.pfs=saved_pfs 457 (p16) mov val1[0]=r0 549 mov ar.lc=len // Continue with a stupid byte store. 555 mov pr=saved_pr,0xffffffffffff0000 556 mov ar.lc=saved_lc 557 mov ar.pfs=saved_pfs 574 (p16) mov val1[0]=r0 575 (p16) mov val2[0]=r0 584 mov pr=saved_pr,0xffffffffffff0000 585 mov ar.lc=saved_lc 586 mov ar.pfs=saved_pfs 595 mov pr=saved_pr,0xffffffffffff0000 596 mov ar.lc=saved_lc 597 mov ar.pfs=saved_pfs 605 mov pr=saved_pr,0xffffffffffff0000 606 mov ar.lc=saved_lc 608 mov ar.pfs=saved_pfs
|
/linux-4.1.27/arch/arm/kernel/ |
H A D | debug.S | 47 mov r1, #8 52 mov r1, #4 57 mov r1, #2 60 mov r1, #0 63 mov r0, r0, lsr #4 70 mov r0, r2 98 mov r1, r0 99 mov r0, #0 115 mov r1, r0 116 mov r0, #0x04 @ SYS_WRITE0 125 mov r0, #0x03 @ SYS_WRITEC 132 mov r2, #0
|
H A D | entry-v7m.S | 28 mov r2, lr 31 mov r0, sp 49 mov r1, sp 67 mov r0, #V7M_SCB_ICSR_PENDSVSET 85 mov r0, #V7M_SCB_ICSR_PENDSVCLR 90 mov why, #0 106 mov r5, r0 109 mov r1, #THREAD_NOTIFY_SWITCH 111 mov ip, r4 112 mov r0, r5
|
/linux-4.1.27/arch/arm/boot/compressed/ |
H A D | debug.S | 13 mov pc, lr 24 mov r0, #0x03 @ SYS_WRITEC 27 mov pc, lr
|
H A D | head.S | 59 mov \rb, #0x80000000 @ physical base address 75 mov r0, \val 80 mov r0, \val 81 mov r1, #\len 110 mov r0, r4 129 mov r0, r0 131 ARM( mov r0, r0 ) 148 mov r7, r1 @ save architecture ID 149 mov r8, r2 @ save atags pointer 160 mov r0, #0x17 @ angel_SWIreason_EnterSVC 198 mov r4, pc 212 mov r0, pc 255 mov r10, r6 258 mov r5, #0 @ init dtb size to 0 304 mov r5, r5, ror #8 321 mov r0, r8 322 mov r1, r6 323 mov r2, r5 335 mov r1, r6 336 mov r2, r5 343 mov r8, r6 @ use the appended device tree 363 mov r5, r5, ror #8 452 mov pc, r0 515 not_relocated: mov r0, #0 539 mov r0, r4 540 mov r1, sp @ malloc space above stack 542 mov r3, r7 546 mov r1, r7 @ restore architecture number 547 mov r2, r8 @ restore atags pointer 586 mov pc, lr 609 cache_on: mov r3, #8 @ cache_on function 617 mov r0, #0x3f @ 4G, the whole 621 mov r0, #0x80 @ PR7 626 mov r0, #0xc000 630 mov r0, #0 641 mov r0, #0 644 mov pc, lr 647 mov r0, #0x3f @ 4G, the whole 650 mov r0, #0x80 @ PR7 654 mov r0, #0xc000 657 mov r0, #0 667 mov r0, #0 672 mov pc, lr 687 mov r0, r3 688 mov r9, r0, lsr #18 689 mov r9, r9, lsl #18 @ start of RAM 691 mov r1, #0x12 @ XN|U + section mapping 711 mov r2, pc 712 mov r2, r2, lsr #20 718 mov pc, lr 732 mov r0, #4 @ put dcache in WT mode 737 mov r12, lr 739 mov r6, #CB_BITS | 0x12 @ U 741 mov r0, #0 749 mov r0, #0 752 mov pc, r12 755 mov r12, lr 761 mov r0, #0 787 mov r0, #0 789 mov pc, r12 792 mov r12, lr 793 mov r6, #CB_BITS | 0x12 @ U 795 mov r0, #0 802 mov r0, #0 804 mov pc, r12 811 mov r1, #-1 882 mov pc, lr 884 mov pc, lr 886 mov pc, lr 891 mov pc, lr 893 mov pc, lr 895 mov pc, lr 902 mov pc, lr 925 mov pc, lr 927 mov pc, lr 929 mov pc, lr 1013 mov pc, lr 1015 mov pc, lr 1017 mov pc, lr 1042 cache_off: mov r3, #12 @ cache_off function 1049 mov r0, #0 1053 mov pc, lr 1059 mov r0, #0 1061 mov pc, lr 1068 mov r0, #0 1072 mov pc, lr 1082 mov r12, lr 1084 mov r0, #0 1091 mov pc, r12 1103 mov r3, #16 1109 mov r2, #1 1110 mov r3, #0 1112 mov r1, #7 << 5 @ 8 segments 1123 mov pc, lr 1128 mov r1, #0 1132 mov pc, lr 1135 mov r1, #0 1141 mov pc, lr 1148 mov r10, #0 1157 mov r3, r3, lsr #23 @ left align loc bit field 1159 mov r10, #0 @ start clean at cache level 0 1162 mov r1, r0, lsr r2 @ extract cache type bits from clidr 1177 mov r9, r4 @ create working copy of max way size 1196 mov r10, #0 @ swith back to cache level 0 1203 mov pc, lr 1212 mov pc, lr 1217 mov r2, #64*1024 @ default: 32K dcache size (*2) 1218 mov r11, #32 @ default: 32 byte line size 1222 mov r1, r3, lsr #18 1224 mov r2, #1024 1225 mov r2, r2, lsl r1 @ base dcache size *2 1228 mov r3, r3, lsr #12 1230 mov r11, #8 1231 mov r11, r11, lsl r3 @ cache line size in bytes 1233 mov r1, pc 1246 mov pc, lr 1252 mov r1, #0 1254 mov pc, lr 1268 mov r2, #0 1274 mov r0, r0, lsr #4 1287 mov r1, #0x00020000 1295 mov pc, lr 1298 mov r2, r0 1299 mov r0, #0 1304 memdump: mov r12, r0 1305 mov r10, lr 1306 mov r11, #0 1307 2: mov r0, r11, lsl #2 1309 mov r1, #8 1311 mov r0, #':' 1313 1: mov r0, #' ' 1316 mov r1, #8 1326 mov r0, #'\n' 1330 mov pc, r10 1349 mov r0, #0 @ must be 0 1350 ARM( mov pc, r4 ) @ call kernel
|
H A D | head-sharpsl.S | 28 mov r1, #0x10000000 @ Base address of TC6393 chip 29 mov r6, #0x03 44 mov r6, #0x31 @ Load Magic Init value 46 mov r5, #0x3000 50 mov r6, #0x30 @ Load 2nd Magic Init value 85 mov r6, #0x0140 128 mov r1, #0x0c000000 @ Base address of NAND chip 133 mov r2, #0x90 @ Command "readid" 138 mov r2, #0 @ Address 0x00 148 mov pc, lr
|
/linux-4.1.27/arch/unicore32/kernel/ |
H A D | debug.S | 30 mov r1, #8 35 mov r1, #4 40 mov r1, #2 43 mov r1, #0 46 mov r0, r0 >> #4 54 mov r0, r2 74 3: mov pc, lr 79 mov r1, r0 80 mov r0, #0
|
H A D | entry.S | 40 mov fp, #0 53 mov \rtemp, asr 55 mov.a asr, \rtemp @ switch to the SUSR mode 61 mov.a asr, \rtemp @ switch back to the PRIV mode 65 mov.a bsr, \rpsr 73 mov.a bsr, r1 @ save in bsr_priv 84 mov.a pc, lr @ return 89 mov \rd, sp >> #13 90 mov \rd, \rd << #13 109 mov r0, \reg 111 mov r0, #':' 113 mov r0, pc 147 mov r1, sp 167 mov r4, #-1 @ "" "" "" "" 172 mov r1, lr 198 mov r4, #-1 @ "" "" "" "" 242 mov r7, #-1 @ "" "" "" "" 247 mov r0, sp 248 mov r1, asr 259 mov r17, asr 280 mov.a asr, r17 281 mov r2, sp 302 mov r0, #0 @ epip4d 317 mov r0, sp @ struct pt_regs *regs 318 mov r1, asr 329 mov r17, asr 341 mov r0, r2 @ pass address of aborted instruction 342 mov r1, #5 343 mov.a asr, r17 344 mov r2, sp @ regs 406 mov r7, #1 418 mov r2, sp @ nothing stacked - regdump is at TOS 419 mov lr, r19 @ setup for a return to the user code 444 mov r2, sp 457 mov why, #0 467 mov r0, sp 468 mov r1, asr 476 mov r0, r2 @ pass address of aborted instruction. 477 mov r1, #5 479 mov r2, sp @ regs 487 mov why, #0 547 mov r0, sp @ 'regs' 548 mov r2, why @ 'syscall' 581 mov r0, r5 583 mov pc, r4 598 mov r8, bsr @ called from non-REAL mode 634 2: mov why, #0 @ no longer a real syscall 642 mov r2, scno 644 mov r0, #0 @ trace entry [IP = 0] 648 mov scno, r0 @ syscall number (possibly new) 657 mov r2, scno 658 mov r1, sp 659 mov r0, #1 @ trace exit [IP = 1] 673 mov why, #0 @ prevent syscall restart handling 702 mov lr, bsr 708 mov r0, asr 710 mov.a bsr, r0 717 mov r0, sp 719 mov.a pc, lr @ branch to handler in PRIV mode
|
H A D | debug-macro.S | 58 mov r1, #0x80 61 mov r1, r1, lsr #8 65 mov r1, #0x7 67 mov r1, #0x3 69 mov r1, #0x0
|
/linux-4.1.27/arch/x86/net/ |
H A D | bpf_jit.S | 35 mov %r9d,%eax # hlen 39 mov (SKBDATA,%rsi),%eax 52 mov %r9d,%eax 76 mov %rbx, %rdi; /* arg1 == skb */ \ 80 mov $LEN,%ecx; /* len */ \ 91 mov - MAX_BPF_STACK + 32(%rbp),%eax 98 mov - MAX_BPF_STACK + 32(%rbp),%ax 110 mov %rbx, %rdi; /* arg1 == skb */ \ 114 mov $SIZE,%edx; /* size */ \ 127 mov (%rax), %eax 137 mov (%rax),%ax 154 mov - MAX_BPF_STACK(%rbp),%rbx 155 mov - MAX_BPF_STACK + 8(%rbp),%r13 156 mov - MAX_BPF_STACK + 16(%rbp),%r14 157 mov - MAX_BPF_STACK + 24(%rbp),%r15
|
/linux-4.1.27/arch/sparc/include/asm/ |
H A D | perf_event.h | 13 "mov %%i7, %3\n\t" \ 14 "mov %%i6, %4\n\t" \
|
H A D | futex_64.h | 15 " mov 0, %0\n" \ 21 " mov %5, %0\n" \ 52 __futex_cas_op("mov\t%4, %1", ret, oldval, uaddr, oparg); futex_atomic_op_inuser() 99 " mov %5, %0\n" futex_atomic_cmpxchg_inatomic()
|
/linux-4.1.27/arch/alpha/lib/ |
H A D | strcpy.S | 18 mov $16, $0 # set up return value 19 mov $26, $23 # set up return address
|
H A D | strcat.S | 17 mov $16, $0 # set up return value 49 mov $26, $23
|
H A D | callback_srm.S | 19 mov $20,$21 # Shift arguments right. 20 mov $19,$20 22 mov $18,$19 23 mov $17,$18 24 mov $16,$17
|
/linux-4.1.27/arch/unicore32/mm/ |
H A D | cache-ucv2.S | 33 mov r0, #0 37 mov r0, #0 41 mov pc, lr 72 2: mov ip, #0 76 3: mov ip, #0 80 mov pc, lr 106 mov r9, #PAGE_SZ 122 2: mov ip, #0 126 3: mov ip, #0 130 mov pc, lr 139 mov ip, #0 142 mov pc, lr 160 mov r9, #PAGE_SZ 173 mov pc, lr 175 2: mov ip, #0 179 mov pc, lr 205 mov pc, lr 207 2: mov ip, #0 211 mov pc, lr
|
/linux-4.1.27/arch/ia64/include/asm/native/ |
H A D | pvchk_inst.h | 58 * mov ar.eflag = 59 * mov = ar.eflag 87 * mov = cr.ifa 88 * mov = cr.itir 89 * mov = cr.isr 90 * mov = cr.iha 91 * mov = cr.ipsr 92 * mov = cr.iim 93 * mov = cr.iip 94 * mov = cr.ivr 95 * mov = psr 97 * mov cr.ifa = 98 * mov cr.itir = 99 * mov cr.iha = 100 * mov cr.ipsr = 101 * mov cr.ifs = 102 * mov cr.iip = 103 * mov cr.kr = 109 * mov = psr 110 * mov = ivr 111 * mov = tpr 112 * mov cr.itm = 113 * mov eoi = 114 * mov rr[] = 115 * mov = rr[] 116 * mov = kr 117 * mov kr = 133 mov \reg = r0 140 mov reg = r0 \
|
H A D | inst.h | 52 mov reg = cr.ifa 55 mov reg = cr.itir 58 mov reg = cr.isr 61 mov reg = cr.iha 64 (pred) mov reg = cr.ipsr 67 mov reg = cr.iim 70 mov reg = cr.iip 73 mov reg = cr.ivr \ 77 (pred) mov reg = psr \ 81 (pred) mov reg = ar.itc \ 86 mov cr.ifa = reg \ 90 (pred) mov cr.itir = reg \ 94 (pred) mov cr.iha = reg \ 98 (pred) mov cr.ipsr = reg \ 102 (pred) mov cr.ifs = reg \ 106 mov cr.iip = reg \ 110 mov IA64_KR(kr) = reg \
|
/linux-4.1.27/arch/avr32/lib/ |
H A D | csum_partial_copy_generic.S | 54 6: mov r12, r9 58 7: mov r5, 0 59 mov r4, 32 77 mov r9, -EFAULT 87 mov r9, 0 91 mov r9, -EFAULT 96 1: mov r9, 0
|
H A D | strncpy_from_user.S | 31 mov r9, -EFAULT 41 mov r9, r10 55 3: mov r12, -EFAULT
|
H A D | memcpy.S | 22 mov r9, r11 27 2: mov r9, r12 63 mov r8, r12 71 mov r9, r8
|
/linux-4.1.27/arch/unicore32/lib/ |
H A D | copy_page.S | 28 mov r17, r0 29 mov r18, r1 30 mov r19, #COPY_COUNT
|
H A D | backtrace.S | 24 mov r0, fp 29 mov pc, lr 35 mov.a frame, r0 @ if frame pointer is zero 54 * mov ip, sp 69 sub r0, sv_pc, #4 @ allow for mov 72 sub r0, sv_pc, #8 @ allow for mov + stmia 75 mov r2, frame 97 mov frame, sv_fp @ above the current frame 101 mov r1, frame 120 mov stack, r0 121 mov instr, r1 122 mov reg, #14 123 mov v7, #0 124 1: mov r3, #1 137 mov r2, reg
|
/linux-4.1.27/arch/x86/crypto/sha-mb/ |
H A D | sha1_mb_mgr_submit_avx2.S | 105 mov %rsp, %r10 109 mov %rbx, (%rsp) 110 mov %r10, 8*2(%rsp) #save old rsp 111 mov %rbp, 8*3(%rsp) 112 mov %r12, 8*4(%rsp) 113 mov %r13, 8*5(%rsp) 114 mov %r14, 8*6(%rsp) 115 mov %r15, 8*7(%rsp) 117 mov _unused_lanes(state), unused_lanes 118 mov unused_lanes, lane 124 mov unused_lanes, _unused_lanes(state) 127 mov job, _job_in_lane(lane_data) 135 mov _result_digest+1*16(job), DWORD_tmp 142 mov _buffer(job), p 143 mov p, _args_data_ptr(state, lane, 8) 160 mov idx, len2 186 mov _job_in_lane(lane_data), job_rax 187 mov _unused_lanes(state), unused_lanes 192 mov unused_lanes, _unused_lanes(state) 207 mov (%rsp), %rbx 208 mov 8*2(%rsp), %r10 #save old rsp 209 mov 8*3(%rsp), %rbp 210 mov 8*4(%rsp), %r12 211 mov 8*5(%rsp), %r13 212 mov 8*6(%rsp), %r14 213 mov 8*7(%rsp), %r15 214 mov %r10, %rsp
|
H A D | sha1_mb_mgr_flush_avx2.S | 116 mov %rsp, %r10 119 mov %rbx, _GPR_SAVE(%rsp) 120 mov %r10, _GPR_SAVE+8*1(%rsp) #save rsp 121 mov %rbp, _GPR_SAVE+8*3(%rsp) 122 mov %r12, _GPR_SAVE+8*4(%rsp) 123 mov %r13, _GPR_SAVE+8*5(%rsp) 124 mov %r14, _GPR_SAVE+8*6(%rsp) 125 mov %r15, _GPR_SAVE+8*7(%rsp) 128 mov _unused_lanes(state), unused_lanes 159 mov offset(state,idx,8), tmp 168 mov tmp, offset(state) 187 mov idx, len2 212 mov _job_in_lane(lane_data), job_rax 215 mov _unused_lanes(state), unused_lanes 218 mov unused_lanes, _unused_lanes(state) 230 mov tmp2_w, offset(job_rax) 234 mov _GPR_SAVE(%rsp), %rbx 235 mov _GPR_SAVE+8*1(%rsp), %r10 #saved rsp 236 mov _GPR_SAVE+8*3(%rsp), %rbp 237 mov _GPR_SAVE+8*4(%rsp), %r12 238 mov _GPR_SAVE+8*5(%rsp), %r13 239 mov _GPR_SAVE+8*6(%rsp), %r14 240 mov _GPR_SAVE+8*7(%rsp), %r15 241 mov %r10, %rsp 258 mov _unused_lanes(state), unused_lanes 280 mov _job_in_lane(lane_data), job_rax 283 mov _unused_lanes(state), unused_lanes 286 mov unused_lanes, _unused_lanes(state)
|
/linux-4.1.27/arch/sh/boards/mach-se/7724/ |
H A D | sdram.S | 42 mov.l @(SH_SLEEP_MODE, r5), r0 62 mov.l FRQCRA,r0 63 mov.l @r0,r3 64 mov.l KICK,r1 66 mov.l r3, @r0 68 mov.l LSTATS,r0 69 mov #1,r1 71 mov.l @r0,r3 88 mov #100,r0 105 mov #100,r0 114 mov.l DUMMY,r0 115 mov.l @r0, r1 /* force single dummy read */
|
/linux-4.1.27/arch/nios2/include/asm/ |
H A D | switch_to.h | 21 "mov r4, %1\n" \ 22 "mov r5, %2\n" \ 24 "mov %0,r4\n" \
|
/linux-4.1.27/arch/ia64/include/asm/ |
H A D | mca_asm.h | 51 mov temp = 0x7 ;; \ 55 mov reg = IA64_KR(PER_CPU_DATA);; \ 83 mov old_psr = psr; \ 87 mov ar.rsc = 0 ; \ 90 mov temp2 = ar.bspstore; \ 94 mov temp1 = ar.rnat; \ 96 mov ar.bspstore = temp2; \ 98 mov ar.rnat = temp1; \ 99 mov temp1 = psr; \ 100 mov temp2 = psr; \ 105 mov psr.l = temp2; \ 122 mov cr.ipsr = temp1; \ 126 mov cr.iip = temp2; \ 127 mov cr.ifs = r0; \ 163 mov temp2 = psr; \ 165 mov old_psr = temp2; \ 169 mov psr.l = temp2; \ 170 mov ar.rsc = 0; \ 173 mov r13 = ar.k6; \ 174 mov temp2 = ar.bspstore; \ 178 mov temp1 = ar.rnat; \ 180 mov ar.bspstore = temp2; \ 182 mov ar.rnat = temp1; \ 184 mov temp1 = old_psr; \ 186 mov temp2 = 1; \ 199 mov cr.ipsr = temp1; \ 202 mov cr.iip = temp2; \
|
/linux-4.1.27/arch/arm/mach-gemini/include/mach/ |
H A D | entry-macro.S | 23 mov \tmp, \irqnr 24 mov \irqnr, #0 29 mov \tmp, \tmp, lsr #1
|
/linux-4.1.27/drivers/scsi/arm/ |
H A D | acornscsi-io.S | 27 mov lr, #0xff 70 mov r3, r3, lsr #8 85 mov r3, r4, lsl #16 87 mov r4, r4, lsr #16 89 mov r5, r6, lsl #16 91 mov r6, r6, lsr #16 94 mov r3, ip, lsl #16 96 mov r4, ip, lsr #16 98 mov ip, lr, lsl #16 100 mov lr, lr, lsr #16 109 mov r3, r4, lsl #16 111 mov r4, r4, lsr #16 113 mov r5, r6, lsl #16 115 mov r6, r6, lsr #16 124 mov r3, r4, lsl #16 126 mov r4, r4, lsr #16 135 mov r3, r3, lsr #8
|
/linux-4.1.27/arch/unicore32/include/asm/ |
H A D | irqflags.h | 29 asm volatile("mov %0, asr" : "=r" (temp) : : "memory", "cc"); arch_local_save_flags() 42 "mov %0, asr\n" arch_local_irq_restore() 43 "mov.a asr, %1\n" arch_local_irq_restore() 44 "mov.f asr, %0" arch_local_irq_restore()
|
/linux-4.1.27/arch/arm/mach-rpc/ |
H A D | fiq.S | 10 mov r12, #ioc_base_high
|
/linux-4.1.27/arch/arm/mm/ |
H A D | copypage-feroceon.c | 21 mov ip, %2 \n\ feroceon_copy_user_page() 22 1: mov lr, r1 \n\ feroceon_copy_user_page() 87 mov r1, %2 \n\ feroceon_clear_user_highpage() 88 mov r2, #0 \n\ feroceon_clear_user_highpage() 89 mov r3, #0 \n\ feroceon_clear_user_highpage() 90 mov r4, #0 \n\ feroceon_clear_user_highpage() 91 mov r5, #0 \n\ feroceon_clear_user_highpage() 92 mov r6, #0 \n\ feroceon_clear_user_highpage() 93 mov r7, #0 \n\ feroceon_clear_user_highpage() 94 mov ip, #0 \n\ feroceon_clear_user_highpage() 95 mov lr, #0 \n\ feroceon_clear_user_highpage()
|
H A D | tlb-v6.S | 38 mov ip, #0 41 mov r0, r0, lsr #PAGE_SHIFT @ align address 42 mov r1, r1, lsr #PAGE_SHIFT 45 mov r1, r1, lsl #PAGE_SHIFT 70 mov r2, #0 72 mov r0, r0, lsr #PAGE_SHIFT @ align address 73 mov r1, r1, lsr #PAGE_SHIFT 74 mov r0, r0, lsl #PAGE_SHIFT 75 mov r1, r1, lsl #PAGE_SHIFT
|
H A D | copypage-fa.c | 25 mov r2, %0 @ 1\n\ fa_copy_user_page() 63 mov r1, %2 @ 1\n\ fa_clear_user_highpage() 64 mov r2, #0 @ 1\n\ fa_clear_user_highpage() 65 mov r3, #0 @ 1\n\ fa_clear_user_highpage() 66 mov ip, #0 @ 1\n\ fa_clear_user_highpage() 67 mov lr, #0 @ 1\n\ fa_clear_user_highpage()
|
H A D | copypage-v4wt.c | 28 mov r2, %2 @ 1\n\ v4wt_copy_user_page() 67 mov r1, %2 @ 1\n\ v4wt_clear_user_highpage() 68 mov r2, #0 @ 1\n\ v4wt_clear_user_highpage() 69 mov r3, #0 @ 1\n\ v4wt_clear_user_highpage() 70 mov ip, #0 @ 1\n\ v4wt_clear_user_highpage() 71 mov lr, #0 @ 1\n\ v4wt_clear_user_highpage()
|
H A D | copypage-xsc3.c | 37 mov lr, %2 \n\ xsc3_mc_copy_user_page() 45 mov ip, r0 \n\ xsc3_mc_copy_user_page() 55 mov ip, r0 \n\ xsc3_mc_copy_user_page() 95 mov r1, %2 \n\ xsc3_mc_clear_user_highpage() 96 mov r2, #0 \n\ xsc3_mc_clear_user_highpage() 97 mov r3, #0 \n\ xsc3_mc_clear_user_highpage()
|
H A D | proc-sa110.S | 39 mov r0, #0 47 mov r0, #0 67 mov ip, #0 98 mov r0, r0 @ safety 99 mov r0, r0 @ safety 100 mov r0, r0 @ safety 102 mov r0, r0 @ safety 103 mov r0, r0 @ safety 104 mov r0, r0 @ safety 156 mov r0, r0 164 mov r10, #0
|
H A D | copypage-xscale.c | 48 mov lr, %2 \n\ mc_copy_user_page() 59 mov ip, r1 \n\ mc_copy_user_page() 70 mov ip, r1 \n\ mc_copy_user_page() 114 "mov r1, %2 \n\ xscale_mc_clear_user_highpage() 115 mov r2, #0 \n\ xscale_mc_clear_user_highpage() 116 mov r3, #0 \n\ xscale_mc_clear_user_highpage() 117 1: mov ip, %0 \n\ xscale_mc_clear_user_highpage()
|
/linux-4.1.27/arch/x86/crypto/ |
H A D | twofish-i586-asm_32.S | 83 mov s1(%ebp,%edi,4),d ## D;\ 85 mov s2(%ebp,%edi,4),%esi;\ 121 mov s1(%ebp,%edi,4),d ## D;\ 123 mov s2(%ebp,%edi,4),%esi;\ 158 mov (%ebp,%edi,4), c ## D;\ 160 mov s3(%ebp,%edi,4),%esi;\ 196 mov (%ebp,%edi,4), c ## D;\ 198 mov s3(%ebp,%edi,4),%esi;\ 229 mov ctx + 16(%esp), %ebp /* abuse the base pointer: set new base 231 mov in_blk+16(%esp),%edi /* input address in edi */ 233 mov (%edi), %eax 234 mov b_offset(%edi), %ebx 235 mov c_offset(%edi), %ecx 236 mov d_offset(%edi), %edx 265 mov out_blk+16(%esp),%edi; 266 mov %eax, c_offset(%edi) 267 mov %ebx, d_offset(%edi) 268 mov %ecx, (%edi) 269 mov %edx, b_offset(%edi) 275 mov $1, %eax 286 mov ctx + 16(%esp), %ebp /* abuse the base pointer: set new base 288 mov in_blk+16(%esp),%edi /* input address in edi */ 290 mov (%edi), %eax 291 mov b_offset(%edi), %ebx 292 mov c_offset(%edi), %ecx 293 mov d_offset(%edi), %edx 322 mov out_blk+16(%esp),%edi; 323 mov %eax, c_offset(%edi) 324 mov %ebx, d_offset(%edi) 325 mov %ecx, (%edi) 326 mov %edx, b_offset(%edi) 332 mov $1, %eax
|
H A D | sha256-avx-asm.S | 62 mov \p2, \p1 158 mov e, y0 # y0 = e 160 mov a, y1 # y1 = a 164 mov f, y2 # y2 = f 180 mov a, y0 # y0 = a 182 mov a, y2 # y2 = a 194 mov e, y0 # y0 = e 195 mov a, y1 # y1 = a 198 mov f, y2 # y2 = f 217 mov a, y0 # y0 = a 219 mov a, y2 # y2 = a 232 mov e, y0 # y0 = e 233 mov a, y1 # y1 = a 237 mov f, y2 # y2 = f 255 mov a, y0 # y0 = a 257 mov a, y2 # y2 = a 270 mov e, y0 # y0 = e 272 mov a, y1 # y1 = a 275 mov f, y2 # y2 = f 293 mov a, y0 # y0 = a 295 mov a, y2 # y2 = a 311 mov e, y0 # y0 = e 313 mov a, y1 # y1 = a 316 mov f, y2 # y2 = f 330 mov a, y0 # y0 = a 332 mov a, y2 # y2 = a 359 mov %rsp, %r12 366 mov NUM_BLKS, _INP_END(%rsp) 369 mov 4*0(CTX), a 370 mov 4*1(CTX), b 371 mov 4*2(CTX), c 372 mov 4*3(CTX), d 373 mov 4*4(CTX), e 374 mov 4*5(CTX), f 375 mov 4*6(CTX), g 376 mov 4*7(CTX), h 390 mov INP, _INP(%rsp) 393 mov $3, SRND 416 mov $2, SRND 448 mov _INP(%rsp), INP 455 mov %r12, %rsp
|
H A D | sha256-ssse3-asm.S | 60 mov \p2, \p1 151 mov e, y0 # y0 = e 153 mov a, y1 # y1 = a 157 mov f, y2 # y2 = f 176 mov a, y0 # y0 = a 178 mov a, y2 # y2 = a 192 mov e, y0 # y0 = e 193 mov a, y1 # y1 = a 197 mov f, y2 # y2 = f 216 mov a, y0 # y0 = a 218 mov a, y2 # y2 = a 233 mov e, y0 # y0 = e 234 mov a, y1 # y1 = a 239 mov f, y2 # y2 = f 257 mov a, y0 # y0 = a 259 mov a, y2 # y2 = a 274 mov e, y0 # y0 = e 276 mov a, y1 # y1 = a 280 mov f, y2 # y2 = f 298 mov a, y0 # y0 = a 300 mov a, y2 # y2 = a 317 mov e, y0 # y0 = e 319 mov a, y1 # y1 = a 322 mov f, y2 # y2 = f 336 mov a, y0 # y0 = a 338 mov a, y2 # y2 = a 365 mov %rsp, %r12 372 mov NUM_BLKS, _INP_END(%rsp) # pointer to end of data 375 mov 4*0(CTX), a 376 mov 4*1(CTX), b 377 mov 4*2(CTX), c 378 mov 4*3(CTX), d 379 mov 4*4(CTX), e 380 mov 4*5(CTX), f 381 mov 4*6(CTX), g 382 mov 4*7(CTX), h 397 mov INP, _INP(%rsp) 400 mov $3, SRND 427 mov $2, SRND 458 mov _INP(%rsp), INP 465 mov %r12, %rsp
|
H A D | sha256-avx2-asm.S | 63 mov \p2, \p1 161 mov a, y3 # y3 = a # MAJA 168 mov f, y2 # y2 = f # CH 189 mov a, T1 # T1 = a # MAJB 209 mov a, y3 # y3 = a # MAJA 218 mov f, y2 # y2 = f # CH 240 mov a, T1 # T1 = a # MAJB 261 mov a, y3 # y3 = a # MAJA 269 mov f, y2 # y2 = f # CH 293 mov a, T1 # T1 = a # MAJB 310 mov a, y3 # y3 = a # MAJA 319 mov f, y2 # y2 = f # CH 348 mov a, T1 # T1 = a # MAJB 363 mov f, y2 # y2 = f # CH 376 mov a, y3 # y3 = a # MAJA 384 mov a, T1 # T1 = a # MAJB 400 mov f, y2 # y2 = f # CH 414 mov a, y3 # y3 = a # MAJA 423 mov a, T1 # T1 = a # MAJB 440 mov f, y2 # y2 = f # CH 454 mov a, y3 # y3 = a # MAJA 463 mov a, T1 # T1 = a # MAJB 480 mov f, y2 # y2 = f # CH 494 mov a, y3 # y3 = a # MAJA 503 mov a, T1 # T1 = a # MAJB 540 mov %rsp, %rax 543 mov %rax, _RSP(%rsp) 549 mov NUM_BLKS, _INP_END(%rsp) 555 mov (CTX), a 556 mov 4*1(CTX), b 557 mov 4*2(CTX), c 558 mov 4*3(CTX), d 559 mov 4*4(CTX), e 560 mov 4*5(CTX), f 561 mov 4*6(CTX), g 562 mov 4*7(CTX), h 568 mov CTX, _CTX(%rsp) 593 mov INP, _INP(%rsp) 636 mov _CTX(%rsp), CTX 637 mov _INP(%rsp), INP 661 mov _CTX(%rsp), CTX 662 mov _INP(%rsp), INP 697 mov (4*0)(CTX),a 698 mov (4*1)(CTX),b 699 mov (4*2)(CTX),c 700 mov (4*3)(CTX),d 701 mov (4*4)(CTX),e 702 mov (4*5)(CTX),f 703 mov (4*6)(CTX),g 704 mov (4*7)(CTX),h 710 mov CTX, _CTX(%rsp) 715 mov _RSP(%rsp), %rsp
|
H A D | aes-i586-asm_32.S | 108 mov 0 sched,%a1; \ 110 mov 12 sched,%a2; \ 112 mov 4 sched,%a4; \ 119 mov %a3,%idx; \ 120 mov 8 sched,%a3; \ 127 mov 0 sched,%a1; \ 129 mov 4 sched,%a2; \ 131 mov 12 sched,%a4; \ 138 mov %a3,%idx; \ 139 mov 8 sched,%a3; \ 145 mov %a2,4*a1(%esp) 148 mov 4*a2(%esp),%a1 228 mov ctx(%esp),%ebp 234 mov in_blk+4(%esp),%r2 236 mov klen(%ebp),%r3 // key size 244 mov (%r2),%r0 245 mov 4(%r2),%r1 246 mov 8(%r2),%r4 247 mov 12(%r2),%r5 280 mov out_blk+12(%esp),%ebp 281 mov %r5,12(%ebp) 283 mov %r4,8(%ebp) 285 mov %r1,4(%ebp) 287 mov %r0,(%ebp) 300 mov ctx(%esp),%ebp 306 mov in_blk+4(%esp),%r2 308 mov klen(%ebp),%r3 // key size 316 mov (%r2),%r0 317 mov 4(%r2),%r1 318 mov 8(%r2),%r4 319 mov 12(%r2),%r5 352 mov out_blk+12(%esp),%ebp 353 mov %r5,12(%ebp) 355 mov %r4,8(%ebp) 357 mov %r1,4(%ebp) 359 mov %r0,(%ebp)
|
H A D | sha512-avx-asm.S | 128 mov f_64, T1 # T1 = f 129 mov e_64, tmp0 # tmp = e 139 mov a_64, T2 # T2 = a 143 mov a_64, tmp0 # tmp = a 148 mov a_64, tmp0 # tmp = a 180 mov f_64, T1 182 mov e_64, tmp0 197 mov a_64, T2 203 mov a_64, tmp0 210 mov a_64, tmp0 227 mov f_64, T1 229 mov e_64, tmp0 248 mov a_64, T2 256 mov a_64, tmp0 261 mov a_64, tmp0 285 mov %rsp, %rax 288 mov %rax, frame_RSPSAVE(%rsp) 291 mov %rbx, frame_GPRSAVE(%rsp) 292 mov %r12, frame_GPRSAVE +8*1(%rsp) 293 mov %r13, frame_GPRSAVE +8*2(%rsp) 294 mov %r14, frame_GPRSAVE +8*3(%rsp) 295 mov %r15, frame_GPRSAVE +8*4(%rsp) 300 mov DIGEST(0), a_64 301 mov DIGEST(1), b_64 302 mov DIGEST(2), c_64 303 mov DIGEST(3), d_64 304 mov DIGEST(4), e_64 305 mov DIGEST(5), f_64 306 mov DIGEST(6), g_64 307 mov DIGEST(7), h_64 357 mov frame_GPRSAVE(%rsp), %rbx 358 mov frame_GPRSAVE +8*1(%rsp), %r12 359 mov frame_GPRSAVE +8*2(%rsp), %r13 360 mov frame_GPRSAVE +8*3(%rsp), %r14 361 mov frame_GPRSAVE +8*4(%rsp), %r15 364 mov frame_RSPSAVE(%rsp), %rsp
|
H A D | sha512-ssse3-asm.S | 121 mov f_64, T1 # T1 = f 122 mov e_64, tmp0 # tmp = e 132 mov a_64, T2 # T2 = a 136 mov a_64, tmp0 # tmp = a 141 mov a_64, tmp0 # tmp = a 173 mov f_64, T1 184 mov e_64, tmp0 196 mov a_64, T2 200 mov a_64, tmp0 205 mov a_64, tmp0 220 mov f_64, T1 228 mov e_64, tmp0 240 mov a_64, T2 245 mov a_64, tmp0 251 mov a_64, tmp0 284 mov %rsp, %rax 287 mov %rax, frame_RSPSAVE(%rsp) 290 mov %rbx, frame_GPRSAVE(%rsp) 291 mov %r12, frame_GPRSAVE +8*1(%rsp) 292 mov %r13, frame_GPRSAVE +8*2(%rsp) 293 mov %r14, frame_GPRSAVE +8*3(%rsp) 294 mov %r15, frame_GPRSAVE +8*4(%rsp) 299 mov DIGEST(0), a_64 300 mov DIGEST(1), b_64 301 mov DIGEST(2), c_64 302 mov DIGEST(3), d_64 303 mov DIGEST(4), e_64 304 mov DIGEST(5), f_64 305 mov DIGEST(6), g_64 306 mov DIGEST(7), h_64 356 mov frame_GPRSAVE(%rsp), %rbx 357 mov frame_GPRSAVE +8*1(%rsp), %r12 358 mov frame_GPRSAVE +8*2(%rsp), %r13 359 mov frame_GPRSAVE +8*3(%rsp), %r14 360 mov frame_GPRSAVE +8*4(%rsp), %r15 363 mov frame_RSPSAVE(%rsp), %rsp
|
H A D | sha512-avx2-asm.S | 124 mov \p2, \p1 185 mov a, y3 # y3 = a # MAJA 190 mov f, y2 # y2 = f # CH 208 mov a, T1 # T1 = a # MAJB 247 mov a, y3 # y3 = a # MAJA 254 mov f, y2 # y2 = f # CH 273 mov a, T1 # T1 = a # MAJB 305 mov a, y3 # y3 = a # MAJA 311 mov f, y2 # y2 = f # CH 330 mov a, T1 # T1 = a # MAJB 362 mov a, y3 # y3 = a # MAJA 369 mov f, y2 # y2 = f # CH 392 mov a, T1 # T1 = a # MAJB 409 mov f, y2 # y2 = f # CH 422 mov a, y3 # y3 = a # MAJA 430 mov a, T1 # T1 = a # MAJB 446 mov f, y2 # y2 = f # CH 460 mov a, y3 # y3 = a # MAJA 468 mov a, T1 # T1 = a # MAJB 484 mov f, y2 # y2 = f # CH 498 mov a, y3 # y3 = a # MAJA 506 mov a, T1 # T1 = a # MAJB 522 mov f, y2 # y2 = f # CH 536 mov a, y3 # y3 = a # MAJA 544 mov a, T1 # T1 = a # MAJB 573 mov %rsp, %rax 576 mov %rax, frame_RSPSAVE(%rsp) 579 mov %rbp, frame_GPRSAVE(%rsp) 580 mov %rbx, 8*1+frame_GPRSAVE(%rsp) 581 mov %r12, 8*2+frame_GPRSAVE(%rsp) 582 mov %r13, 8*3+frame_GPRSAVE(%rsp) 583 mov %r14, 8*4+frame_GPRSAVE(%rsp) 584 mov %r15, 8*5+frame_GPRSAVE(%rsp) 589 mov NUM_BLKS, frame_INPEND(%rsp) 592 mov 8*0(CTX),a 593 mov 8*1(CTX),b 594 mov 8*2(CTX),c 595 mov 8*3(CTX),d 596 mov 8*4(CTX),e 597 mov 8*5(CTX),f 598 mov 8*6(CTX),g 599 mov 8*7(CTX),h 612 mov INP, frame_INP(%rsp) 664 mov frame_INP(%rsp), INP 672 mov frame_GPRSAVE(%rsp) ,%rbp 673 mov 8*1+frame_GPRSAVE(%rsp) ,%rbx 674 mov 8*2+frame_GPRSAVE(%rsp) ,%r12 675 mov 8*3+frame_GPRSAVE(%rsp) ,%r13 676 mov 8*4+frame_GPRSAVE(%rsp) ,%r14 677 mov 8*5+frame_GPRSAVE(%rsp) ,%r15 680 mov frame_RSPSAVE(%rsp), %rsp
|
H A D | sha1_ssse3_asm.S | 80 mov %rsp, %r12 84 mov CTX, HASH_PTR 85 mov BUF, BUFFER_PTR 89 mov CNT, BUFFER_END 97 mov $8, %ecx 98 mov %rsp, %rdi 102 mov %r12, %rsp # deallocate workspace 118 mov (HASH_PTR), A 119 mov 4(HASH_PTR), B 120 mov 8(HASH_PTR), C 121 mov 12(HASH_PTR), D 122 mov 16(HASH_PTR), E 207 mov B, REG_B 208 mov D, REG_D define 209 mov A, REG_A 210 mov E, REG_E 220 mov \c, T1 228 mov \d, T1 235 mov \c, T1 237 mov \b, T2 250 mov \val, \hash 279 mov \e, T1
|
/linux-4.1.27/arch/ia64/include/uapi/asm/ |
H A D | gcc_intrin.h | 37 asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \ 40 asm volatile ("mov ar%0=%1" :: \ 45 asm volatile ("mov cr%0=%1" :: \ 50 asm volatile ("mov r12=%0" :: \ 54 asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \ 68 asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \ 71 asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \ 74 asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \ 80 asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \ 84 asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \ 88 asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \ 310 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 319 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 328 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 337 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 347 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 356 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 365 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 374 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \ 425 asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory") 428 asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory") 431 asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory") 434 asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory") 437 asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory") 440 asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory"); 445 asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \ 452 asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ 459 asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ 466 asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ 473 asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ 481 asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ 488 asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \
|
/linux-4.1.27/arch/arm64/kernel/vdso/ |
H A D | gettimeofday.S | 54 mov x2, x30 68 mov x13, #1000 78 mov x0, xzr 82 mov x8, #__NR_gettimeofday 95 mov x2, x30 106 mov x30, x2 124 mov x12, #0 147 mov x15, #NSEC_PER_SEC_LO16 163 mov x0, xzr 166 mov x30, x2 168 mov x8, #__NR_clock_gettime 193 mov w0, wzr 197 mov x8, #__NR_clock_getres 237 mov x11, #NSEC_PER_SEC_LO16
|
/linux-4.1.27/arch/unicore32/boot/compressed/ |
H A D | head.S | 25 mov r0, #0xD3 26 mov.a asr, r0 78 mov r0, #0 86 mov r0, #0 92 mov r0, #0x1c @ en icache and wb dcache 100 mov r1, sp @ malloc space above stack 136 mov r0, r4 142 mov r0, #0 151 mov r0, #0 @ disable i/d cache and MMU 155 mov r0, #0 @ must be zero 157 mov pc, r4 @ call kernel 177 mov pc, lr 188 mov pc, lr
|
/linux-4.1.27/arch/arm/include/debug/ |
H A D | omap2plus.S | 83 mov \rp, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4 87 mov \rp, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4 91 mov \rp, #UART_OFFSET(OMAP2_UART3_BASE) 95 mov \rp, #UART_OFFSET(OMAP3_UART1_BASE) 101 mov \rp, #UART_OFFSET(OMAP4_UART3_BASE) 105 mov \rp, #UART_OFFSET(OMAP3_UART1_BASE) 111 mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) 115 mov \rp, #UART_OFFSET(TI81XX_UART1_BASE) 119 mov \rp, #UART_OFFSET(TI81XX_UART2_BASE) 123 mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) 136 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT) 147 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) 158 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
|
/linux-4.1.27/arch/alpha/boot/ |
H A D | head.S | 113 mov $30, $1 114 mov $16, $2 121 mov $16, $30
|
/linux-4.1.27/arch/arm/crypto/ |
H A D | bsaes-armv7.pl | 992 mov r4,$inp @ pass key 993 mov r12,$out @ pass key schedule 1011 mov r4,$key @ pass the key 1013 mov r5,#10 @ pass rounds 1040 mov r4,$inp @ pass key 1041 mov r12,$out @ pass key schedule 1061 mov r4,$key @ pass the key 1063 mov r5,#10 @ pass rounds 1108 mov ip, sp 1112 mov $len, $len, lsr#4 @ len in 16 byte blocks 1114 mov $fp, sp @ save sp 1123 mov r4, $key @ pass key 1124 mov r5, $rounds @ pass # of rounds 1125 mov sp, r12 @ sp is $keysched 1138 mov r4, $key @ pass key 1139 mov r5, $rounds @ pass # of rounds 1163 mov r4, $keysched @ pass the key 1168 mov r5, $rounds 1207 mov r4, $keysched @ pass the key 1211 mov r5, $rounds 1330 mov $rounds, $out @ save original out pointer 1331 mov $out, $fp @ use the iv scratch space as out buffer 1332 mov r2, $key 1351 mov sp, $fp 1373 mov ip, sp 1378 mov $fp, sp @ save sp 1387 mov r4, $key @ pass key 1388 mov r5, $rounds @ pass # of rounds 1389 mov sp, r12 @ sp is $keysched 1404 mov r4, $key @ pass key 1405 mov r5, $rounds @ pass # of rounds 1450 mov r5, $rounds @ pass rounds 1533 mov sp, $fp 1543 mov r4, $inp @ copy arguments 1544 mov r5, $out 1545 mov r6, $len 1546 mov r7, $key 1558 mov r1, sp @ output on the stack 1559 mov r2, r7 @ key 1601 mov ip, sp 1604 mov r6, sp @ future $fp 1606 mov $inp, r0 1607 mov $out, r1 1608 mov $len, r2 1609 mov $key, r3 1613 mov sp, r0 1620 mov r1, sp 1623 mov r0,sp @ pointer to initial tweak 1627 mov $fp, r6 1635 mov r4, $key @ pass key 1636 mov r5, $rounds @ pass # of rounds 1637 mov sp, r12 1648 mov r4, $key @ pass key 1649 mov r5, $rounds @ pass # of rounds 1670 mov r0, sp 1706 mov r5, $rounds @ pass rounds 1708 mov r0, sp 1740 mov r0, sp 1775 mov r5, $rounds @ pass rounds 1776 mov r0, sp 1809 mov r5, $rounds @ pass rounds 1810 mov r0, sp 1846 mov r5, $rounds @ pass rounds 1847 mov r0, sp 1876 mov r5, $rounds @ pass rounds 1877 mov r0, sp 1903 mov r5, $rounds @ pass rounds 1904 mov r0, sp 1929 mov r5, $rounds @ pass rounds 1930 mov r0, sp 1943 mov r0, sp 1945 mov r1, sp 1947 mov r2, $key 1948 mov r4, $fp @ preserve fp 1955 mov $fp, r4 1975 mov r0, sp 1977 mov r1, sp 1979 mov r2, $key 1980 mov r4, $fp @ preserve fp 1987 mov $fp, r4 2002 mov sp, $fp 2015 mov ip, sp 2018 mov r6, sp @ future $fp 2020 mov $inp, r0 2021 mov $out, r1 2022 mov $len, r2 2023 mov $key, r3 2027 mov sp, r0 2034 mov r1, sp 2037 mov r0, sp @ pointer to initial tweak 2041 mov $fp, r6 2049 mov r4, $key @ pass key 2050 mov r5, $rounds @ pass # of rounds 2051 mov sp, r12 2065 mov r4, $key @ pass key 2066 mov r5, $rounds @ pass # of rounds 2095 mov r0, sp 2131 mov r5, $rounds @ pass rounds 2133 mov r0, sp 2165 mov r0, sp 2200 mov r5, $rounds @ pass rounds 2201 mov r0, sp 2234 mov r5, $rounds @ pass rounds 2235 mov r0, sp 2265 mov r5, $rounds @ pass rounds 2266 mov r0, sp 2295 mov r5, $rounds @ pass rounds 2296 mov r0, sp 2322 mov r5, $rounds @ pass rounds 2323 mov r0, sp 2348 mov r5, $rounds @ pass rounds 2349 mov r0, sp 2362 mov r0, sp 2364 mov r1, sp 2366 mov r2, $key 2367 mov r4, $fp @ preserve fp 2368 mov r5, $magic @ preserve magic 2375 mov $fp, r4 2376 mov $magic, r5 2395 mov r0, sp 2397 mov r1, sp 2399 mov r2, $key 2400 mov r4, $fp @ preserve fp 2408 mov r6, $out 2419 mov r0, sp 2421 mov r1, sp 2423 mov r2, $key 2430 mov $fp, r4 2445 mov sp, $fp
|
/linux-4.1.27/arch/x86/xen/ |
H A D | xen-head.S | 42 mov %esi,xen_start_info 43 mov $init_thread_union+THREAD_SIZE,%esp 45 mov %rsi,xen_start_info 46 mov $init_thread_union+THREAD_SIZE,%rsp 64 mov %rsi, %r11 67 mov $0x80000001, %eax 69 mov %edx, %esi 71 mov $MSR_EFER, %ecx
|
/linux-4.1.27/arch/arm/mach-ebsa110/include/mach/ |
H A D | entry-macro.S | 16 mov \base, #IRQ_STAT 21 mov \irqnr, #0
|
/linux-4.1.27/arch/arm/common/ |
H A D | mcpm_head.S | 35 mov r0, r9 39 mov r0, r10 59 mov r3, #MAX_CPUS_PER_CLUSTER 89 mov r0, #MCPM_SYNC_CLUSTER_SIZE 93 mov r0, #CPU_COMING_UP 94 mov r5, #MCPM_SYNC_CPU_SIZE 101 mov r0, #VLOCK_SIZE 103 mov r0, r11 104 mov r1, r9 @ cpu 115 mov r0, r11 123 mov r0, #INBOUND_COMING_UP 150 mov r0, #1 @ second (cluster) affinity level 154 mov r0, #CLUSTER_UP 161 mov r0, #INBOUND_NOT_COMING_UP 166 mov r0, r11 184 mov r0, #0 @ first (CPU) affinity level 190 mov r0, #CPU_UP
|
/linux-4.1.27/arch/arm64/kernel/ |
H A D | entry.S | 71 mov w0, w0 // zero upper 32 bits of x0 171 mov \rd, sp 192 mov x0, sp 237 mov x0, sp 238 mov x1, #\reason 316 mov x2, sp // struct pt_regs 328 mov x2, sp 335 mov x0, sp 345 mov x2, sp // struct pt_regs 351 mov x0, sp 352 mov x1, #BAD_SYNC 384 mov x24, lr 458 mov sc_nr, #__NR_compat_syscalls 476 mov x1, x25 477 mov x2, sp 488 mov x0, x26 490 mov x2, sp 499 mov x0, x25 500 mov x1, sp 509 mov x0, x25 510 mov x1, sp 521 mov x0, x26 522 mov x1, x25 523 mov x2, sp 533 mov x0, sp 542 mov x1, x25 543 mov x2, sp 551 mov x0, sp 552 mov x1, #BAD_SYNC 586 mov x9, sp 602 mov sp, x9 627 mov x0, sp // 'regs' 655 mov x0, x20 668 mov sc_nr, #__NR_syscalls 683 mov x0, sp 693 mov w0, #-1 // set default errno for 696 mov x0, #-ENOSYS 698 1: mov x0, sp 703 mov x1, sp // pointer to regs 716 mov x0, sp 721 mov x0, sp 729 mov x0, sp
|
/linux-4.1.27/drivers/tty/serial/ |
H A D | earlycon-arm-semihost.c | 38 asm volatile("mov x1, %0\n" smh_putc() 39 "mov x0, #3\n" smh_putc() 43 asm volatile("mov r1, %0\n" smh_putc() 44 "mov r0, #3\n" smh_putc()
|
/linux-4.1.27/arch/avr32/boot/u-boot/ |
H A D | head.S | 28 mov r0, 0 29 mov r1, 0 44 mov lr, 0 45 mov r7, 0
|
/linux-4.1.27/arch/arm64/xen/ |
H A D | hypercall.S | 59 mov x16, #__HYPERVISOR_##hypercall; \ 86 mov x16, x0 87 mov x0, x1 88 mov x1, x2 89 mov x2, x3 90 mov x3, x4 91 mov x4, x5
|
/linux-4.1.27/arch/avr32/kernel/ |
H A D | entry-avr32b.S | 131 mov r3, -1 /* All entries have been accessed, */ 132 mov r2, 0 /* so start at 0 */ 155 mov r11, sp 171 mov r1, lo(swapper_pg_dir) 218 mov r8, r5 /* 5th argument (6th is pushed by stub) */ 248 mov r12, -ENOSYS 254 mov r12, 0 260 mov r12, r0 261 mov lr, r2 /* syscall_return */ 262 mov pc, r1 286 2: mov r2, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME 290 mov r12, sp 291 mov r11, r0 310 mov r12, r8 372 mov sp, 4 392 mov r1, lr 398 mov r11, sp 414 mov r11, 1 421 mov r11, 0 423 mov r10, sp 438 mov r11, sp 465 mov r11, sp 474 mov r11, sp 484 mov r11, sp 503 mov r0, r3 521 mov r12, 26 522 mov r11, sp 593 1: mov r2, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME 597 mov r12, sp 598 mov r11, r0 624 mov r12, sp 626 mov sp, r12 634 mov r2, _TIF_DBGWORK_MASK 661 mov r10, r8 686 mov r1, r2 718 mov r9, 0 750 mov r11, sp 751 mov r12, \level 871 mov r11, sp 872 mov r10, 9 /* SIGKILL */
|
/linux-4.1.27/arch/sh/boards/mach-ecovec24/ |
H A D | sdram.S | 40 mov.l @(SH_SLEEP_MODE, r5), r0 71 mov #100,r0 88 mov #100,r0 97 mov.l DUMMY,r0 98 mov.l @r0, r1 /* force single dummy read */
|