Searched refs:link_bw (Results 1 - 19 of 19) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c70 nv_encoder->dp.link_bw = 27000 * dpcd[1]; nouveau_dp_detect()
74 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); nouveau_dp_detect()
77 nv_encoder->dcb->dpconf.link_bw); nouveau_dp_detect()
81 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) nouveau_dp_detect()
82 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; nouveau_dp_detect()
85 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); nouveau_dp_detect()
H A Dnouveau_encoder.h60 int link_bw; member in struct:nouveau_encoder::__anon4165::__anon4166
H A Dnouveau_bios.c1475 entry->dpconf.link_bw = 162000; parse_dcb20_entry()
1478 entry->dpconf.link_bw = 270000; parse_dcb20_entry()
1481 entry->dpconf.link_bw = 540000; parse_dcb20_entry()
H A Dnouveau_connector.c863 max_clock *= nv_encoder->dp.link_bw; nouveau_connector_mode_valid()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddport.c40 u32 link_bw; member in struct:dp_state
67 DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); dp_set_link_config()
72 while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp)) dp_set_link_config()
76 while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp)) dp_set_link_config()
84 ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000, dp_set_link_config()
96 sink[0] = dp->link_bw / 27000; dp_set_link_config()
343 if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) nvkm_dp_train()
344 outp->dpcd[1] = outp->base.info.dpconf.link_bw; nvkm_dp_train()
366 dp->link_bw = cfg->bw * 27000; nvkm_dp_train()
H A Dgf110.c990 u32 datarate, link_nr, link_bw, bits; gf110_disp_intr_unk2_2_tu() local
994 link_bw = (clksor & 0x007c0000) >> 18; gf110_disp_intr_unk2_2_tu()
995 link_bw *= 27000; gf110_disp_intr_unk2_2_tu()
999 value = value * link_bw; gf110_disp_intr_unk2_2_tu()
1006 value = value * link_bw; gf110_disp_intr_unk2_2_tu()
1019 do_div(ratio, link_nr * link_bw); gf110_disp_intr_unk2_2_tu()
H A Doutpdp.c84 outp->base.info.dpconf.link_bw; nvkm_output_dp_train()
H A Dnv50.c1654 u32 link_nr, link_bw, bits; nv50_disp_intr_unk20_2_dp() local
1657 link_bw = (clksor & 0x000c0000) ? 270000 : 162000; nv50_disp_intr_unk20_2_dp()
1662 value = value * link_bw; nv50_disp_intr_unk20_2_dp()
1669 value = value * link_bw; nv50_disp_intr_unk20_2_dp()
1683 do_div(link_ratio, link_bw); nv50_disp_intr_unk20_2_dp()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Ddcb.h47 int link_bw; member in struct:dcb_output::__anon4113::__anon4117
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Ddcb.c148 outp->dpconf.link_bw = 0x06; dcb_outp_parse()
151 outp->dpconf.link_bw = 0x0a; dcb_outp_parse()
155 outp->dpconf.link_bw = 0x14; dcb_outp_parse()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Danx9805.c33 anx9805_train(struct nvkm_i2c_port *port, int link_nr, int link_bw, bool enh) anx9805_train() argument
39 DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh); anx9805_train()
41 nv_wri2cr(mast, chan->addr, 0xa0, link_bw); anx9805_train()
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c264 uint8_t link_bw; member in struct:cdv_intel_dp
359 cdv_intel_dp_link_clock(uint8_t link_bw) cdv_intel_dp_link_clock() argument
361 if (link_bw == DP_LINK_BW_2_7) cdv_intel_dp_link_clock()
919 intel_dp->link_bw = bws[clock]; cdv_intel_dp_mode_fixup()
921 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); cdv_intel_dp_mode_fixup()
924 intel_dp->link_bw, intel_dp->lane_count, cdv_intel_dp_mode_fixup()
933 intel_dp->link_bw = bws[max_clock]; cdv_intel_dp_mode_fixup()
934 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); cdv_intel_dp_mode_fixup()
937 intel_dp->link_bw, intel_dp->lane_count, cdv_intel_dp_mode_fixup()
1073 intel_dp->link_configuration[0] = intel_dp->link_bw; cdv_intel_dp_mode_set()
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_dp_mst.c59 intel_dp->link_bw = 0; intel_dp_mst_compute_config()
62 intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate); intel_dp_mst_compute_config()
H A Dintel_dp.c45 int link_bw; member in struct:dp_link_dpll
1125 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) hsw_dp_set_ddi_pll_sel() argument
1127 switch (link_bw) { hsw_dp_set_ddi_pll_sel()
1188 struct intel_crtc_state *pipe_config, int link_bw) intel_dp_set_clock()
1210 if (link_bw == divisor[i].link_bw) { intel_dp_set_clock()
1443 intel_dp->link_bw = 0; intel_dp_compute_config()
1447 intel_dp->link_bw = intel_dp_compute_config()
1456 intel_dp->link_bw, intel_dp->lane_count, intel_dp_compute_config()
1478 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); intel_dp_compute_config()
1480 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); intel_dp_compute_config()
3553 link_config[0] = intel_dp->link_bw; intel_dp_start_link_train()
3640 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) intel_dp_complete_link_train()
1187 intel_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, int link_bw) intel_dp_set_clock() argument
H A Dintel_drv.h622 uint8_t link_bw; member in struct:intel_dp
954 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
H A Dintel_display.c5766 int lane, link_bw, fdi_dotclock; ironlake_fdi_compute_config() local
5777 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; ironlake_fdi_compute_config()
5781 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, ironlake_fdi_compute_config()
5787 link_bw, &pipe_config->fdi_m_n); ironlake_fdi_compute_config()
7722 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) ironlake_get_lanes_required() argument
7730 return DIV_ROUND_UP(bps, link_bw * 8); ironlake_get_lanes_required()
H A Dintel_ddi.c1180 switch (intel_dp->link_bw) { skl_ddi_pll_select()
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_dp_helper.c148 int drm_dp_bw_code_to_link_rate(u8 link_bw) drm_dp_bw_code_to_link_rate() argument
150 switch (link_bw) { drm_dp_bw_code_to_link_rate()
/linux-4.1.27/include/drm/
H A Ddrm_dp_helper.h588 int drm_dp_bw_code_to_link_rate(u8 link_bw);

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