Searched refs:imx21 (Results 1 - 37 of 37) sorted by relevance

/linux-4.1.27/drivers/usb/host/
H A Dimx21-dbg.c19 /* this file is part of imx21-hcd.c */
27 static inline void create_debug_files(struct imx21 *imx21) { } remove_debug_files() argument
28 static inline void remove_debug_files(struct imx21 *imx21) { } debug_urb_submitted() argument
29 static inline void debug_urb_submitted(struct imx21 *imx21, struct urb *urb) {} debug_urb_completed() argument
30 static inline void debug_urb_completed(struct imx21 *imx21, struct urb *urb, debug_urb_completed() argument
32 static inline void debug_urb_unlinked(struct imx21 *imx21, struct urb *urb) {} debug_urb_queued_for_etd() argument
33 static inline void debug_urb_queued_for_etd(struct imx21 *imx21, debug_urb_queued_for_etd() argument
35 static inline void debug_urb_queued_for_dmem(struct imx21 *imx21, debug_urb_queued_for_dmem() argument
37 static inline void debug_etd_allocated(struct imx21 *imx21) {} debug_etd_freed() argument
38 static inline void debug_etd_freed(struct imx21 *imx21) {} debug_dmem_allocated() argument
39 static inline void debug_dmem_allocated(struct imx21 *imx21, int size) {} debug_dmem_freed() argument
40 static inline void debug_dmem_freed(struct imx21 *imx21, int size) {} debug_isoc_submitted() argument
41 static inline void debug_isoc_submitted(struct imx21 *imx21, debug_isoc_submitted() argument
43 static inline void debug_isoc_completed(struct imx21 *imx21, debug_isoc_completed() argument
70 static inline struct debug_stats *stats_for_urb(struct imx21 *imx21, stats_for_urb() argument
74 &imx21->isoc_stats : &imx21->nonisoc_stats; stats_for_urb()
77 static void debug_urb_submitted(struct imx21 *imx21, struct urb *urb) debug_urb_submitted() argument
79 stats_for_urb(imx21, urb)->submitted++; debug_urb_submitted()
82 static void debug_urb_completed(struct imx21 *imx21, struct urb *urb, int st) debug_urb_completed() argument
85 stats_for_urb(imx21, urb)->completed_failed++; debug_urb_completed()
87 stats_for_urb(imx21, urb)->completed_ok++; debug_urb_completed()
90 static void debug_urb_unlinked(struct imx21 *imx21, struct urb *urb) debug_urb_unlinked() argument
92 stats_for_urb(imx21, urb)->unlinked++; debug_urb_unlinked()
95 static void debug_urb_queued_for_etd(struct imx21 *imx21, struct urb *urb) debug_urb_queued_for_etd() argument
97 stats_for_urb(imx21, urb)->queue_etd++; debug_urb_queued_for_etd()
100 static void debug_urb_queued_for_dmem(struct imx21 *imx21, struct urb *urb) debug_urb_queued_for_dmem() argument
102 stats_for_urb(imx21, urb)->queue_dmem++; debug_urb_queued_for_dmem()
105 static inline void debug_etd_allocated(struct imx21 *imx21) debug_etd_allocated() argument
107 imx21->etd_usage.maximum = max( debug_etd_allocated()
108 ++(imx21->etd_usage.value), debug_etd_allocated()
109 imx21->etd_usage.maximum); debug_etd_allocated()
112 static inline void debug_etd_freed(struct imx21 *imx21) debug_etd_freed() argument
114 imx21->etd_usage.value--; debug_etd_freed()
117 static inline void debug_dmem_allocated(struct imx21 *imx21, int size) debug_dmem_allocated() argument
119 imx21->dmem_usage.value += size; debug_dmem_allocated()
120 imx21->dmem_usage.maximum = max( debug_dmem_allocated()
121 imx21->dmem_usage.value, debug_dmem_allocated()
122 imx21->dmem_usage.maximum); debug_dmem_allocated()
125 static inline void debug_dmem_freed(struct imx21 *imx21, int size) debug_dmem_freed() argument
127 imx21->dmem_usage.value -= size; debug_dmem_freed()
131 static void debug_isoc_submitted(struct imx21 *imx21, debug_isoc_submitted() argument
134 struct debug_isoc_trace *trace = &imx21->isoc_trace[ debug_isoc_submitted()
135 imx21->isoc_trace_index++]; debug_isoc_submitted()
137 imx21->isoc_trace_index %= ARRAY_SIZE(imx21->isoc_trace); debug_isoc_submitted()
144 static inline void debug_isoc_completed(struct imx21 *imx21, debug_isoc_completed() argument
151 trace = imx21->isoc_trace; debug_isoc_completed()
152 for (i = 0; i < ARRAY_SIZE(imx21->isoc_trace); i++, trace++) { debug_isoc_completed()
164 trace_failed = &imx21->isoc_trace_failed[ debug_isoc_completed()
165 imx21->isoc_trace_index_failed++]; debug_isoc_completed()
167 imx21->isoc_trace_index_failed %= ARRAY_SIZE( debug_isoc_completed()
168 imx21->isoc_trace_failed); debug_isoc_completed()
201 struct imx21 *imx21 = s->private; debug_status_show() local
216 spin_lock_irqsave(&imx21->lock, flags); debug_status_show()
218 etd_enable_mask = readl(imx21->regs + USBH_ETDENSET); debug_status_show()
219 for (i = 0, etd = imx21->etd; i < USB_NUM_ETD; i++, etd++) { debug_status_show()
228 list_for_each_entry(dmem, &imx21->dmem_list, list) { debug_status_show()
233 list_for_each_entry(ep_priv, &imx21->queue_for_etd, queue) debug_status_show()
236 list_for_each_entry(etd, &imx21->queue_for_dmem, queue) debug_status_show()
239 spin_unlock_irqrestore(&imx21->lock, flags); debug_status_show()
250 readl(imx21->regs + USBH_FRMNUB) & 0xFFFF, debug_status_show()
251 etds_allocated, USB_NUM_ETD, imx21->etd_usage.maximum, debug_status_show()
254 dmem_bytes, DMEM_SIZE, imx21->dmem_usage.maximum, debug_status_show()
264 struct imx21 *imx21 = s->private; debug_dmem_show() local
269 spin_lock_irqsave(&imx21->lock, flags); debug_dmem_show()
271 list_for_each_entry(dmem, &imx21->dmem_list, list) debug_dmem_show()
278 spin_unlock_irqrestore(&imx21->lock, flags); debug_dmem_show()
285 struct imx21 *imx21 = s->private; debug_etd_show() local
292 spin_lock_irqsave(&imx21->lock, flags); debug_etd_show()
294 for (i = 0, etd = imx21->etd; i < USB_NUM_ETD; i++, etd++) { debug_etd_show()
318 (readl(imx21->regs + USBH_ETDENSET) & (1 << i)) > 0, debug_etd_show()
323 dword = etd_readl(imx21, i, j); debug_etd_show()
346 spin_unlock_irqrestore(&imx21->lock, flags); debug_etd_show()
372 struct imx21 *imx21 = s->private; debug_statistics_show() local
375 spin_lock_irqsave(&imx21->lock, flags); debug_statistics_show()
377 debug_statistics_show_one(s, "nonisoc", &imx21->nonisoc_stats); debug_statistics_show()
378 debug_statistics_show_one(s, "isoc", &imx21->isoc_stats); debug_statistics_show()
379 seq_printf(s, "unblock kludge triggers: %lu\n", imx21->debug_unblocks); debug_statistics_show()
380 spin_unlock_irqrestore(&imx21->lock, flags); debug_statistics_show()
406 struct imx21 *imx21 = s->private; debug_isoc_show() local
411 spin_lock_irqsave(&imx21->lock, flags); debug_isoc_show()
413 trace = imx21->isoc_trace_failed; debug_isoc_show()
414 for (i = 0; i < ARRAY_SIZE(imx21->isoc_trace_failed); i++, trace++) debug_isoc_show()
417 trace = imx21->isoc_trace; debug_isoc_show()
418 for (i = 0; i < ARRAY_SIZE(imx21->isoc_trace); i++, trace++) debug_isoc_show()
421 spin_unlock_irqrestore(&imx21->lock, flags); debug_isoc_show()
486 static void create_debug_files(struct imx21 *imx21) create_debug_files() argument
488 imx21->debug_root = debugfs_create_dir(dev_name(imx21->dev), NULL); create_debug_files()
489 if (!imx21->debug_root) create_debug_files()
493 imx21->debug_root, imx21, &debug_status_fops)) create_debug_files()
497 imx21->debug_root, imx21, &debug_dmem_fops)) create_debug_files()
501 imx21->debug_root, imx21, &debug_etd_fops)) create_debug_files()
505 imx21->debug_root, imx21, &debug_statistics_fops)) create_debug_files()
509 imx21->debug_root, imx21, &debug_isoc_fops)) create_debug_files()
515 debugfs_remove_recursive(imx21->debug_root); create_debug_files()
518 imx21->debug_root = NULL; create_debug_files()
522 static void remove_debug_files(struct imx21 *imx21) remove_debug_files() argument
524 if (imx21->debug_root) { remove_debug_files()
525 debugfs_remove_recursive(imx21->debug_root); remove_debug_files()
526 imx21->debug_root = NULL; remove_debug_files()
H A Dimx21-hcd.c63 #include "imx21-hcd.h"
70 #define DEBUG_LOG_FRAME(imx21, etd, event) \
71 (etd)->event##_frame = readl((imx21)->regs + USBH_FRMNUB)
73 #define DEBUG_LOG_FRAME(imx21, etd, event) do { } while (0)
76 static const char hcd_name[] = "imx21-hcd";
78 static inline struct imx21 *hcd_to_imx21(struct usb_hcd *hcd) hcd_to_imx21()
80 return (struct imx21 *)hcd->hcd_priv; hcd_to_imx21()
88 static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask) set_register_bits() argument
90 void __iomem *reg = imx21->regs + offset; set_register_bits()
94 static inline void clear_register_bits(struct imx21 *imx21, clear_register_bits() argument
97 void __iomem *reg = imx21->regs + offset; clear_register_bits()
101 static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask) clear_toggle_bit() argument
103 void __iomem *reg = imx21->regs + offset; clear_toggle_bit()
109 static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask) set_toggle_bit() argument
111 void __iomem *reg = imx21->regs + offset; set_toggle_bit()
117 static void etd_writel(struct imx21 *imx21, int etd_num, int dword, u32 value) etd_writel() argument
119 writel(value, imx21->regs + USB_ETD_DWORD(etd_num, dword)); etd_writel()
122 static u32 etd_readl(struct imx21 *imx21, int etd_num, int dword) etd_readl() argument
124 return readl(imx21->regs + USB_ETD_DWORD(etd_num, dword)); etd_readl()
140 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_get_frame() local
142 return wrap_frame(readl(imx21->regs + USBH_FRMNUB)); imx21_hc_get_frame()
150 #include "imx21-dbg.c"
153 struct imx21 *imx21, struct etd_priv *etd, int status);
154 static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb);
155 static void free_dmem(struct imx21 *imx21, struct etd_priv *etd);
161 static int alloc_etd(struct imx21 *imx21) alloc_etd() argument
164 struct etd_priv *etd = imx21->etd; alloc_etd()
168 memset(etd, 0, sizeof(imx21->etd[0])); alloc_etd()
170 debug_etd_allocated(imx21); alloc_etd()
177 static void disactivate_etd(struct imx21 *imx21, int num) disactivate_etd() argument
180 struct etd_priv *etd = &imx21->etd[num]; disactivate_etd()
182 writel(etd_mask, imx21->regs + USBH_ETDENCLR); disactivate_etd()
183 clear_register_bits(imx21, USBH_ETDDONEEN, etd_mask); disactivate_etd()
184 writel(etd_mask, imx21->regs + USB_ETDDMACHANLCLR); disactivate_etd()
185 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask); disactivate_etd()
189 DEBUG_LOG_FRAME(imx21, etd, disactivated); disactivate_etd()
192 static void reset_etd(struct imx21 *imx21, int num) reset_etd() argument
194 struct etd_priv *etd = imx21->etd + num; reset_etd()
197 disactivate_etd(imx21, num); reset_etd()
200 etd_writel(imx21, num, i, 0); reset_etd()
207 static void free_etd(struct imx21 *imx21, int num) free_etd() argument
213 dev_err(imx21->dev, "BAD etd=%d!\n", num); free_etd()
216 if (imx21->etd[num].alloc == 0) { free_etd()
217 dev_err(imx21->dev, "ETD %d already free!\n", num); free_etd()
221 debug_etd_freed(imx21); free_etd()
222 reset_etd(imx21, num); free_etd()
223 memset(&imx21->etd[num], 0, sizeof(imx21->etd[0])); free_etd()
227 static void setup_etd_dword0(struct imx21 *imx21, setup_etd_dword0() argument
230 etd_writel(imx21, etd_num, 0, setup_etd_dword0()
245 struct imx21 *imx21, int dmem_offset, void *src, int count) copy_to_dmem()
247 void __iomem *dmem = imx21->regs + USBOTG_DMEM + dmem_offset; copy_to_dmem()
267 static void activate_etd(struct imx21 *imx21, int etd_num, u8 dir) activate_etd() argument
270 struct etd_priv *etd = &imx21->etd[etd_num]; activate_etd()
277 copy_to_dmem(imx21, activate_etd()
298 dev_err(imx21->dev, "failed bounce alloc\n"); activate_etd()
303 dma_map_single(imx21->dev, activate_etd()
307 if (dma_mapping_error(imx21->dev, etd->dma_handle)) { activate_etd()
308 dev_err(imx21->dev, "failed bounce map\n"); activate_etd()
314 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask); activate_etd()
315 set_register_bits(imx21, USBH_ETDDONEEN, etd_mask); activate_etd()
316 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); activate_etd()
317 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); activate_etd()
320 set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask); activate_etd()
321 clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask); activate_etd()
322 clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask); activate_etd()
323 writel(etd->dma_handle, imx21->regs + USB_ETDSMSA(etd_num)); activate_etd()
324 set_register_bits(imx21, USB_ETDDMAEN, etd_mask); activate_etd()
328 set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); activate_etd()
329 set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); activate_etd()
333 DEBUG_LOG_FRAME(imx21, etd, activated); activate_etd()
338 etd->activated_frame = readl(imx21->regs + USBH_FRMNUB); activate_etd()
344 etd->submitted_dwords[i] = etd_readl(imx21, etd_num, i); activate_etd()
349 writel(etd_mask, imx21->regs + USBH_ETDENSET); activate_etd()
356 free_dmem(imx21, etd); activate_etd()
357 nonisoc_urb_completed_for_etd(imx21, etd, -ENOMEM); activate_etd()
364 static int alloc_dmem(struct imx21 *imx21, unsigned int size, alloc_dmem() argument
374 dev_err(imx21->dev, "size=%d > DMEM_SIZE(%d)\n", alloc_dmem()
379 list_for_each_entry(tmp, &imx21->dmem_list, list) { alloc_dmem()
397 debug_dmem_allocated(imx21, size); alloc_dmem()
405 static void activate_queued_etd(struct imx21 *imx21, activate_queued_etd() argument
409 int etd_num = etd - &imx21->etd[0]; activate_queued_etd()
410 u32 maxpacket = etd_readl(imx21, etd_num, 1) >> DW1_YBUFSRTAD; activate_queued_etd()
411 u8 dir = (etd_readl(imx21, etd_num, 2) >> DW2_DIRPID) & 0x03; activate_queued_etd()
413 dev_dbg(imx21->dev, "activating queued ETD %d now DMEM available\n", activate_queued_etd()
415 etd_writel(imx21, etd_num, 1, activate_queued_etd()
420 activate_etd(imx21, etd_num, dir); activate_queued_etd()
423 static void free_dmem(struct imx21 *imx21, struct etd_priv *etd) free_dmem() argument
435 list_for_each_entry(area, &imx21->dmem_list, list) { free_dmem()
437 debug_dmem_freed(imx21, area->size); free_dmem()
446 dev_err(imx21->dev, free_dmem()
452 list_for_each_entry_safe(etd, tmp, &imx21->queue_for_dmem, queue) { free_dmem()
453 offset = alloc_dmem(imx21, etd->dmem_size, etd->ep); free_dmem()
456 activate_queued_etd(imx21, etd, (u32)offset); free_dmem()
461 static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep) free_epdmem() argument
465 list_for_each_entry_safe(area, tmp, &imx21->dmem_list, list) { free_epdmem()
467 dev_err(imx21->dev, free_epdmem()
482 static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv) ep_idle() argument
492 etd = &imx21->etd[etd_num]; ep_idle()
495 free_dmem(imx21, etd); /* for isoc */ ep_idle()
497 if (list_empty(&imx21->queue_for_etd)) { ep_idle()
498 free_etd(imx21, etd_num); ep_idle()
502 dev_dbg(imx21->dev, ep_idle()
504 ep_priv = list_first_entry(&imx21->queue_for_etd, ep_idle()
507 reset_etd(imx21, etd_num); ep_idle()
512 dev_err(imx21->dev, "No urb for queued ep!\n"); ep_idle()
515 schedule_nonisoc_etd(imx21, list_first_entry( ep_idle()
521 __releases(imx21->lock)
522 __acquires(imx21->lock)
524 struct imx21 *imx21 = hcd_to_imx21(hcd); variable in typeref:struct:imx21
528 debug_urb_completed(imx21, urb, status);
529 dev_vdbg(imx21->dev, "urb %p done %d\n", urb, status);
535 spin_unlock(&imx21->lock);
537 spin_lock(&imx21->lock);
539 ep_idle(imx21, ep_priv);
543 struct imx21 *imx21, struct etd_priv *etd, int status) nonisoc_urb_completed_for_etd()
547 urb_done(imx21->hcd, etd->urb, status); nonisoc_urb_completed_for_etd()
554 dev_vdbg(imx21->dev, "next URB %p\n", urb); nonisoc_urb_completed_for_etd()
555 schedule_nonisoc_etd(imx21, urb); nonisoc_urb_completed_for_etd()
567 struct imx21 *imx21 = hcd_to_imx21(hcd); schedule_isoc_etds() local
586 etd = &imx21->etd[etd_num]; schedule_isoc_etds()
596 dev_dbg(imx21->dev, "isoc too late frame %d > %d\n", schedule_isoc_etds()
615 debug_isoc_submitted(imx21, cur_frame, td); schedule_isoc_etds()
618 setup_etd_dword0(imx21, etd_num, td->urb, dir, etd->dmem_size); schedule_isoc_etds()
619 etd_writel(imx21, etd_num, 1, etd->dmem_offset); schedule_isoc_etds()
620 etd_writel(imx21, etd_num, 2, schedule_isoc_etds()
623 etd_writel(imx21, etd_num, 3, schedule_isoc_etds()
627 activate_etd(imx21, etd_num, dir); schedule_isoc_etds()
633 struct imx21 *imx21 = hcd_to_imx21(hcd); isoc_etd_done() local
635 struct etd_priv *etd = imx21->etd + etd_num; isoc_etd_done()
646 disactivate_etd(imx21, etd_num); isoc_etd_done()
648 cc = (etd_readl(imx21, etd_num, 3) >> DW3_COMPCODE0) & 0xf; isoc_etd_done()
649 bytes_xfrd = etd_readl(imx21, etd_num, 3) & 0x3ff; isoc_etd_done()
660 debug_isoc_completed(imx21, isoc_etd_done()
664 dev_dbg(imx21->dev, isoc_etd_done()
672 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); isoc_etd_done()
675 imx21->regs + USBOTG_DMEM + etd->dmem_offset, isoc_etd_done()
694 struct imx21 *imx21, struct usb_host_endpoint *ep) alloc_isoc_ep()
712 static int alloc_isoc_etds(struct imx21 *imx21, struct ep_priv *ep_priv) alloc_isoc_etds() argument
720 etd_num = alloc_etd(imx21); alloc_isoc_etds()
725 imx21->etd[etd_num].ep = ep_priv->ep; alloc_isoc_etds()
731 dev_err(imx21->dev, "isoc: Couldn't allocate etd\n"); alloc_isoc_etds()
733 free_etd(imx21, ep_priv->etd[j]); alloc_isoc_etds()
743 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_urb_enqueue_isoc() local
764 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_urb_enqueue_isoc()
767 ep_priv = alloc_isoc_ep(imx21, ep); imx21_hc_urb_enqueue_isoc()
776 ret = alloc_isoc_etds(imx21, ep_priv); imx21_hc_urb_enqueue_isoc()
793 struct etd_priv *etd = &imx21->etd[ep_priv->etd[i]]; imx21_hc_urb_enqueue_isoc()
797 dev_err(imx21->dev, "increasing isoc buffer %d->%d\n", imx21_hc_urb_enqueue_isoc()
804 etd->dmem_offset = alloc_dmem(imx21, maxpacket, ep); imx21_hc_urb_enqueue_isoc()
806 dev_dbg(imx21->dev, "failed alloc isoc dmem\n"); imx21_hc_urb_enqueue_isoc()
824 dev_dbg(imx21->dev, imx21_hc_urb_enqueue_isoc()
857 dev_vdbg(imx21->dev, "setup %d packets for iso frame %d->%d\n", imx21_hc_urb_enqueue_isoc()
860 debug_urb_submitted(imx21, urb); imx21_hc_urb_enqueue_isoc()
863 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_urb_enqueue_isoc()
872 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_urb_enqueue_isoc()
880 static void dequeue_isoc_urb(struct imx21 *imx21, dequeue_isoc_urb() argument
890 if (etd_num != -1 && imx21->etd[etd_num].urb == urb) { dequeue_isoc_urb()
891 struct etd_priv *etd = imx21->etd + etd_num; dequeue_isoc_urb()
893 reset_etd(imx21, etd_num); dequeue_isoc_urb()
894 free_dmem(imx21, etd); dequeue_isoc_urb()
901 dev_vdbg(imx21->dev, "removing td %p\n", td); dequeue_isoc_urb()
911 static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb) schedule_nonisoc_etd() argument
929 dev_err(imx21->dev, "No valid ETD\n"); schedule_nonisoc_etd()
932 if (readl(imx21->regs + USBH_ETDENSET) & (1 << etd_num)) schedule_nonisoc_etd()
933 dev_err(imx21->dev, "submitting to active ETD %d\n", etd_num); schedule_nonisoc_etd()
935 etd = &imx21->etd[etd_num]; schedule_nonisoc_etd()
944 usb_hcd_unmap_urb_setup_for_dma(imx21->hcd, schedule_nonisoc_etd()
961 usb_hcd_unmap_urb_for_dma(imx21->hcd, urb); schedule_nonisoc_etd()
989 relpolpos = (readl(imx21->regs + USBH_FRMNUB) + 1) & 0xff; schedule_nonisoc_etd()
993 setup_etd_dword0(imx21, etd_num, urb, dir, maxpacket); schedule_nonisoc_etd()
995 etd_writel(imx21, etd_num, 2, schedule_nonisoc_etd()
1011 etd_writel(imx21, etd_num, 3, schedule_nonisoc_etd()
1019 etd->dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep); schedule_nonisoc_etd()
1022 etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16); schedule_nonisoc_etd()
1024 dev_dbg(imx21->dev, "Queuing etd %d for DMEM\n", etd_num); schedule_nonisoc_etd()
1025 debug_urb_queued_for_dmem(imx21, urb); schedule_nonisoc_etd()
1026 list_add_tail(&etd->queue, &imx21->queue_for_dmem); schedule_nonisoc_etd()
1030 etd_writel(imx21, etd_num, 1, schedule_nonisoc_etd()
1037 dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n", schedule_nonisoc_etd()
1039 activate_etd(imx21, etd_num, dir); schedule_nonisoc_etd()
1045 struct imx21 *imx21 = hcd_to_imx21(hcd); nonisoc_etd_done() local
1046 struct etd_priv *etd = &imx21->etd[etd_num]; nonisoc_etd_done()
1055 disactivate_etd(imx21, etd_num); nonisoc_etd_done()
1057 dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3; nonisoc_etd_done()
1058 cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf; nonisoc_etd_done()
1059 bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff); nonisoc_etd_done()
1064 (etd_readl(imx21, etd_num, 0) >> DW0_TOGCRY) & 0x1); nonisoc_etd_done()
1067 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask); nonisoc_etd_done()
1068 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask); nonisoc_etd_done()
1072 dma_unmap_single(imx21->dev, nonisoc_etd_done()
1076 imx21->regs + USBOTG_DMEM + etd->dmem_offset, nonisoc_etd_done()
1083 free_dmem(imx21, etd); nonisoc_etd_done()
1091 dev_vdbg(imx21->dev, "cc is 0x%x\n", cc); nonisoc_etd_done()
1112 dev_err(imx21->dev, nonisoc_etd_done()
1141 nonisoc_urb_completed_for_etd(imx21, etd, cc_to_error[cc]); nonisoc_etd_done()
1143 dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state); nonisoc_etd_done()
1144 schedule_nonisoc_etd(imx21, urb); nonisoc_etd_done()
1167 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_urb_enqueue() local
1175 dev_vdbg(imx21->dev, imx21_hc_urb_enqueue()
1190 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_urb_enqueue()
1222 debug_urb_submitted(imx21, urb); imx21_hc_urb_enqueue()
1225 dev_dbg(imx21->dev, imx21_hc_urb_enqueue()
1228 debug_urb_queued_for_etd(imx21, urb); imx21_hc_urb_enqueue()
1231 ep_priv->etd[0] = alloc_etd(imx21); imx21_hc_urb_enqueue()
1233 dev_dbg(imx21->dev, imx21_hc_urb_enqueue()
1235 debug_urb_queued_for_etd(imx21, urb); imx21_hc_urb_enqueue()
1236 list_add_tail(&ep_priv->queue, &imx21->queue_for_etd); imx21_hc_urb_enqueue()
1243 etd = &imx21->etd[ep_priv->etd[0]]; imx21_hc_urb_enqueue()
1245 DEBUG_LOG_FRAME(imx21, etd, last_req); imx21_hc_urb_enqueue()
1246 schedule_nonisoc_etd(imx21, urb); imx21_hc_urb_enqueue()
1250 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_urb_enqueue()
1255 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_urb_enqueue()
1263 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_urb_dequeue() local
1270 dev_vdbg(imx21->dev, "dequeue urb=%p iso=%d status=%d\n", imx21_hc_urb_dequeue()
1273 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_urb_dequeue()
1281 debug_urb_unlinked(imx21, urb); imx21_hc_urb_dequeue()
1284 dequeue_isoc_urb(imx21, urb, ep_priv); imx21_hc_urb_dequeue()
1289 struct etd_priv *etd = &imx21->etd[etd_num]; imx21_hc_urb_dequeue()
1291 disactivate_etd(imx21, etd_num); imx21_hc_urb_dequeue()
1292 free_dmem(imx21, etd); imx21_hc_urb_dequeue()
1301 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_urb_dequeue()
1305 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_urb_dequeue()
1313 static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof) process_etds() argument
1319 spin_lock_irqsave(&imx21->lock, flags); process_etds()
1323 u32 enabled = readl(imx21->regs + USBH_ETDENSET) & etd_mask; process_etds()
1324 u32 done = readl(imx21->regs + USBH_ETDDONESTAT) & etd_mask; process_etds()
1325 struct etd_priv *etd = &imx21->etd[etd_num]; process_etds()
1329 DEBUG_LOG_FRAME(imx21, etd, last_int); process_etds()
1356 cc = etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE; process_etds()
1363 dword0 = etd_readl(imx21, etd_num, 0); process_etds()
1364 dev_dbg(imx21->dev, process_etds()
1371 dev_dbg(imx21->dev, process_etds()
1378 readl(imx21->regs + USBH_FRMNUB)); process_etds()
1379 imx21->debug_unblocks++; process_etds()
1386 dev_dbg(imx21->dev, process_etds()
1390 disactivate_etd(imx21, etd_num); process_etds()
1402 set_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT); process_etds()
1404 clear_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT); process_etds()
1407 spin_unlock_irqrestore(&imx21->lock, flags); process_etds()
1412 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_irq() local
1413 u32 ints = readl(imx21->regs + USBH_SYSISR); imx21_irq()
1416 dev_dbg(imx21->dev, "Scheduling error\n"); imx21_irq()
1419 dev_dbg(imx21->dev, "Scheduling overrun\n"); imx21_irq()
1422 process_etds(hcd, imx21, ints & USBH_SYSISR_SOFINT); imx21_irq()
1424 writel(ints, imx21->regs + USBH_SYSISR); imx21_irq()
1431 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_endpoint_disable() local
1439 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_endpoint_disable()
1441 dev_vdbg(imx21->dev, "disable ep=%p, ep->hcpriv=%p\n", ep, ep_priv); imx21_hc_endpoint_disable()
1444 dev_dbg(imx21->dev, "ep's URB list is not empty\n"); imx21_hc_endpoint_disable()
1449 dev_dbg(imx21->dev, "free etd %d for disable\n", imx21_hc_endpoint_disable()
1452 free_etd(imx21, ep_priv->etd[i]); imx21_hc_endpoint_disable()
1459 if (imx21->etd[i].alloc && imx21->etd[i].ep == ep) { imx21_hc_endpoint_disable()
1460 dev_err(imx21->dev, imx21_hc_endpoint_disable()
1462 free_etd(imx21, i); imx21_hc_endpoint_disable()
1465 free_epdmem(imx21, ep); imx21_hc_endpoint_disable()
1466 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_endpoint_disable()
1476 struct imx21 *imx21 = hcd_to_imx21(hcd); get_hub_descriptor() local
1480 desc->bNbrPorts = readl(imx21->regs + USBH_ROOTHUBA) get_hub_descriptor()
1495 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_hub_status_data() local
1501 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_hub_status_data()
1502 ports = readl(imx21->regs + USBH_ROOTHUBA) imx21_hc_hub_status_data()
1506 dev_err(imx21->dev, "ports %d > 7\n", ports); imx21_hc_hub_status_data()
1509 if (readl(imx21->regs + USBH_PORTSTAT(i)) & imx21_hc_hub_status_data()
1520 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_hub_status_data()
1523 dev_info(imx21->dev, "Hub status changed\n"); imx21_hc_hub_status_data()
1531 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_hub_control() local
1537 dev_dbg(imx21->dev, "ClearHubFeature\n"); imx21_hc_hub_control()
1540 dev_dbg(imx21->dev, " OVER_CURRENT\n"); imx21_hc_hub_control()
1543 dev_dbg(imx21->dev, " LOCAL_POWER\n"); imx21_hc_hub_control()
1546 dev_dbg(imx21->dev, " unknown\n"); imx21_hc_hub_control()
1553 dev_dbg(imx21->dev, "ClearPortFeature\n"); imx21_hc_hub_control()
1556 dev_dbg(imx21->dev, " ENABLE\n"); imx21_hc_hub_control()
1560 dev_dbg(imx21->dev, " SUSPEND\n"); imx21_hc_hub_control()
1564 dev_dbg(imx21->dev, " POWER\n"); imx21_hc_hub_control()
1568 dev_dbg(imx21->dev, " C_ENABLE\n"); imx21_hc_hub_control()
1572 dev_dbg(imx21->dev, " C_SUSPEND\n"); imx21_hc_hub_control()
1576 dev_dbg(imx21->dev, " C_CONNECTION\n"); imx21_hc_hub_control()
1580 dev_dbg(imx21->dev, " C_OVER_CURRENT\n"); imx21_hc_hub_control()
1584 dev_dbg(imx21->dev, " C_RESET\n"); imx21_hc_hub_control()
1588 dev_dbg(imx21->dev, " unknown\n"); imx21_hc_hub_control()
1596 dev_dbg(imx21->dev, "GetHubDescriptor\n"); imx21_hc_hub_control()
1601 dev_dbg(imx21->dev, " GetHubStatus\n"); imx21_hc_hub_control()
1606 dev_dbg(imx21->dev, "GetPortStatus: port: %d, 0x%x\n", imx21_hc_hub_control()
1608 *(__le32 *) buf = readl(imx21->regs + imx21_hc_hub_control()
1613 dev_dbg(imx21->dev, "SetHubFeature\n"); imx21_hc_hub_control()
1616 dev_dbg(imx21->dev, " OVER_CURRENT\n"); imx21_hc_hub_control()
1620 dev_dbg(imx21->dev, " LOCAL_POWER\n"); imx21_hc_hub_control()
1623 dev_dbg(imx21->dev, " unknown\n"); imx21_hc_hub_control()
1631 dev_dbg(imx21->dev, "SetPortFeature\n"); imx21_hc_hub_control()
1634 dev_dbg(imx21->dev, " SUSPEND\n"); imx21_hc_hub_control()
1638 dev_dbg(imx21->dev, " POWER\n"); imx21_hc_hub_control()
1642 dev_dbg(imx21->dev, " RESET\n"); imx21_hc_hub_control()
1646 dev_dbg(imx21->dev, " unknown\n"); imx21_hc_hub_control()
1653 dev_dbg(imx21->dev, " unknown\n"); imx21_hc_hub_control()
1659 writel(status_write, imx21->regs + USBH_PORTSTAT(wIndex - 1)); imx21_hc_hub_control()
1669 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_reset() local
1673 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_reset()
1678 imx21->regs + USBOTG_RST_CTRL); imx21_hc_reset()
1682 while (readl(imx21->regs + USBOTG_RST_CTRL) != 0) { imx21_hc_reset()
1684 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_reset()
1685 dev_err(imx21->dev, "timeout waiting for reset\n"); imx21_hc_reset()
1688 spin_unlock_irq(&imx21->lock); imx21_hc_reset()
1690 spin_lock_irq(&imx21->lock); imx21_hc_reset()
1692 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_reset()
1698 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_start() local
1704 hw_mode |= ((imx21->pdata->host_xcvr << USBOTG_HWMODE_HOSTXCVR_SHIFT) & imx21_hc_start()
1706 hw_mode |= ((imx21->pdata->otg_xcvr << USBOTG_HWMODE_OTGXCVR_SHIFT) & imx21_hc_start()
1709 if (imx21->pdata->host1_txenoe) imx21_hc_start()
1712 if (!imx21->pdata->host1_xcverless) imx21_hc_start()
1715 if (imx21->pdata->otg_ext_xcvr) imx21_hc_start()
1719 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_start()
1722 imx21->regs + USBOTG_CLK_CTRL); imx21_hc_start()
1723 writel(hw_mode, imx21->regs + USBOTG_HWMODE); imx21_hc_start()
1724 writel(usb_control, imx21->regs + USBCTRL); imx21_hc_start()
1726 imx21->regs + USB_MISCCONTROL); imx21_hc_start()
1731 etd_writel(imx21, i, j, 0); imx21_hc_start()
1735 imx21->regs + USBH_HOST_CTRL); imx21_hc_start()
1738 if (imx21->pdata->enable_otg_host) imx21_hc_start()
1740 imx21->regs + USBH_PORTSTAT(0)); imx21_hc_start()
1742 if (imx21->pdata->enable_host1) imx21_hc_start()
1744 imx21->regs + USBH_PORTSTAT(1)); imx21_hc_start()
1746 if (imx21->pdata->enable_host2) imx21_hc_start()
1748 imx21->regs + USBH_PORTSTAT(2)); imx21_hc_start()
1754 set_register_bits(imx21, USBH_SYSIEN, imx21_hc_start()
1757 set_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT); imx21_hc_start()
1759 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_start()
1766 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_hc_stop() local
1769 spin_lock_irqsave(&imx21->lock, flags); imx21_hc_stop()
1771 writel(0, imx21->regs + USBH_SYSIEN); imx21_hc_stop()
1772 clear_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT); imx21_hc_stop()
1773 clear_register_bits(imx21, USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN, imx21_hc_stop()
1775 spin_unlock_irqrestore(&imx21->lock, flags); imx21_hc_stop()
1785 .hcd_priv_size = sizeof(struct imx21),
1820 struct imx21 *imx21 = hcd_to_imx21(hcd); imx21_remove() local
1823 remove_debug_files(imx21); imx21_remove()
1827 clk_disable_unprepare(imx21->clk); imx21_remove()
1828 clk_put(imx21->clk); imx21_remove()
1829 iounmap(imx21->regs); imx21_remove()
1841 struct imx21 *imx21; imx21_probe() local
1863 imx21 = hcd_to_imx21(hcd); imx21_probe()
1864 imx21->hcd = hcd; imx21_probe()
1865 imx21->dev = &pdev->dev; imx21_probe()
1866 imx21->pdata = dev_get_platdata(&pdev->dev); imx21_probe()
1867 if (!imx21->pdata) imx21_probe()
1868 imx21->pdata = &default_pdata; imx21_probe()
1870 spin_lock_init(&imx21->lock); imx21_probe()
1871 INIT_LIST_HEAD(&imx21->dmem_list); imx21_probe()
1872 INIT_LIST_HEAD(&imx21->queue_for_etd); imx21_probe()
1873 INIT_LIST_HEAD(&imx21->queue_for_dmem); imx21_probe()
1874 create_debug_files(imx21); imx21_probe()
1882 imx21->regs = ioremap(res->start, resource_size(res)); imx21_probe()
1883 if (imx21->regs == NULL) { imx21_probe()
1884 dev_err(imx21->dev, "Cannot map registers\n"); imx21_probe()
1890 imx21->clk = clk_get(imx21->dev, NULL); imx21_probe()
1891 if (IS_ERR(imx21->clk)) { imx21_probe()
1892 dev_err(imx21->dev, "no clock found\n"); imx21_probe()
1893 ret = PTR_ERR(imx21->clk); imx21_probe()
1897 ret = clk_set_rate(imx21->clk, clk_round_rate(imx21->clk, 48000000)); imx21_probe()
1900 ret = clk_prepare_enable(imx21->clk); imx21_probe()
1904 dev_info(imx21->dev, "Hardware HC revision: 0x%02X\n", imx21_probe()
1905 (readl(imx21->regs + USBOTG_HWMODE) >> 16) & 0xFF); imx21_probe()
1909 dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret); imx21_probe()
1917 clk_disable_unprepare(imx21->clk); imx21_probe()
1920 clk_put(imx21->clk); imx21_probe()
1922 iounmap(imx21->regs); imx21_probe()
1926 remove_debug_files(imx21); imx21_probe()
1946 MODULE_ALIAS("platform:imx21-hcd");
244 copy_to_dmem( struct imx21 *imx21, int dmem_offset, void *src, int count) copy_to_dmem() argument
542 nonisoc_urb_completed_for_etd( struct imx21 *imx21, struct etd_priv *etd, int status) nonisoc_urb_completed_for_etd() argument
693 alloc_isoc_ep( struct imx21 *imx21, struct usb_host_endpoint *ep) alloc_isoc_ep() argument
H A DMakefile70 obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
H A Dimx21-hcd.h419 struct imx21 { struct
/linux-4.1.27/arch/arm/mach-imx/
H A Dmm-imx21.c2 * arch/arm/mach-imx/mm-imx21.c
87 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); imx21_soc_init()
88 mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); imx21_soc_init()
89 mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); imx21_soc_init()
90 mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); imx21_soc_init()
91 mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); imx21_soc_init()
92 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); imx21_soc_init()
95 imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, imx21_soc_init()
97 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, imx21_soc_init()
H A Dclk-imx21.c17 #include <dt-bindings/clock/imx21-clock.h>
128 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0"); mx21_clocks_init()
129 clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx21_clocks_init()
130 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1"); mx21_clocks_init()
131 clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx21_clocks_init()
132 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2"); mx21_clocks_init()
133 clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx21_clocks_init()
134 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3"); mx21_clocks_init()
135 clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx21_clocks_init()
138 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0"); mx21_clocks_init()
139 clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0"); mx21_clocks_init()
140 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1"); mx21_clocks_init()
141 clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1"); mx21_clocks_init()
142 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2"); mx21_clocks_init()
143 clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2"); mx21_clocks_init()
144 clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0"); mx21_clocks_init()
145 clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx21_clocks_init()
146 clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0"); mx21_clocks_init()
147 clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0"); mx21_clocks_init()
148 clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0"); mx21_clocks_init()
149 clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0"); mx21_clocks_init()
150 clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma"); mx21_clocks_init()
151 clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma"); mx21_clocks_init()
153 clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); mx21_clocks_init()
171 CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);
H A Dmm-imx27.c88 mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); imx27_soc_init()
89 mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); imx27_soc_init()
90 mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); imx27_soc_init()
91 mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); imx27_soc_init()
92 mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); imx27_soc_init()
93 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); imx27_soc_init()
98 /* imx27 has the imx21 type audmux */ imx27_soc_init()
99 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, imx27_soc_init()
H A Dclk-imx27.c170 clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx27_clocks_init()
171 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); mx27_clocks_init()
172 clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx27_clocks_init()
173 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); mx27_clocks_init()
174 clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx27_clocks_init()
175 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); mx27_clocks_init()
176 clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx27_clocks_init()
177 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); mx27_clocks_init()
178 clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); mx27_clocks_init()
179 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); mx27_clocks_init()
180 clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); mx27_clocks_init()
181 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); mx27_clocks_init()
184 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); mx27_clocks_init()
185 clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); mx27_clocks_init()
186 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); mx27_clocks_init()
187 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); mx27_clocks_init()
188 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); mx27_clocks_init()
189 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); mx27_clocks_init()
196 clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); mx27_clocks_init()
197 clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx27_clocks_init()
198 clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); mx27_clocks_init()
223 clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); mx27_clocks_init()
224 clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); mx27_clocks_init()
H A Dclk-imx31.c133 clk_register_clkdev(clk[rtc_gate], NULL, "imx21-rtc"); mx31_clocks_init()
154 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); mx31_clocks_init()
155 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx31_clocks_init()
156 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); mx31_clocks_init()
157 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx31_clocks_init()
158 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); mx31_clocks_init()
159 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx31_clocks_init()
160 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); mx31_clocks_init()
161 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); mx31_clocks_init()
162 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); mx31_clocks_init()
163 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); mx31_clocks_init()
164 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); mx31_clocks_init()
165 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); mx31_clocks_init()
166 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); mx31_clocks_init()
H A Dclk-imx35.c226 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); mx35_clocks_init()
227 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); mx35_clocks_init()
228 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); mx35_clocks_init()
237 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); mx35_clocks_init()
238 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx35_clocks_init()
239 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); mx35_clocks_init()
240 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx35_clocks_init()
241 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); mx35_clocks_init()
242 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx35_clocks_init()
H A DMakefile4 obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
H A Dmach-mx21ads.c28 #include "devices-imx21.h"
/linux-4.1.27/arch/arm/mach-imx/devices/
H A Dplatform-imx-i2c.c31 imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
37 imx_imx_i2c_data_entry(MX27, "imx21-i2c", _id, _hwid, SZ_4K)
46 imx_imx_i2c_data_entry(MX31, "imx21-i2c", _id, _hwid, SZ_4K)
56 imx_imx_i2c_data_entry(MX35, "imx21-i2c", _id, _hwid, SZ_4K)
H A Dplatform-imx-fb.c29 imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
34 imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
H A Dplatform-mxc_rtc.c21 imx_mxc_rtc_data_entry_single(MX31, "imx21-rtc");
26 imx_mxc_rtc_data_entry_single(MX35, "imx21-rtc");
H A Dplatform-imx21-hcd.c38 return imx_add_platform_device_dmamask("imx21-hcd", 0, imx_add_imx21_hcd()
H A Dplatform-mxc-mmc.c29 imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K)
38 imx_mxc_mmc_data_entry(MX27, "imx21-mmc", _id, _hwid, SZ_4K)
H A DMakefile8 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
H A Dplatform-mxc_nand.c34 imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
H A Dplatform-spi_imx.c36 imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
H A Dplatform-imx-uart.c130 return imx_add_platform_device("imx21-uart", data->id, imx_add_imx_uart_1irq()
/linux-4.1.27/drivers/pinctrl/freescale/
H A Dpinctrl-imx21.c325 { .compatible = "fsl,imx21-iomuxc", },
332 .name = "imx21-pinctrl",
/linux-4.1.27/sound/soc/fsl/
H A Dimx-audmux.c189 .name = "imx21-audmux",
201 { .compatible = "fsl,imx21-audmux", .data = &imx_audmux_ids[0], },
H A Deukrea-tlv320.c148 of_find_compatible_node(NULL, NULL, "fsl,imx21-audmux")) { eukrea_tlv320_probe()
H A Dfsl_ssi.c245 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
/linux-4.1.27/drivers/w1/masters/
H A Dmxc_w1.c170 { .compatible = "fsl,imx21-owire" },
/linux-4.1.27/drivers/gpio/
H A Dgpio-mxc.c139 .name = "imx21-gpio",
154 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
/linux-4.1.27/drivers/rtc/
H A Drtc-mxc.c92 .name = "imx21-rtc",
/linux-4.1.27/drivers/watchdog/
H A Dimx2_wdt.c398 { .compatible = "fsl,imx21-wdt", },
/linux-4.1.27/drivers/input/keyboard/
H A Dimx_keypad.c419 { .compatible = "fsl,imx21-kpp", },
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-imx.c249 .name = "imx21-i2c",
259 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
/linux-4.1.27/drivers/mmc/host/
H A Dmxcmmc.c167 .name = "imx21-mmc",
183 .compatible = "fsl,imx21-mmc",
/linux-4.1.27/drivers/spi/
H A Dspi-imx.c683 .name = "imx21-cspi",
704 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
/linux-4.1.27/drivers/dma/
H A Dimx-dma.c201 .name = "imx21-dma",
217 .compatible = "fsl,imx21-dma",
/linux-4.1.27/drivers/video/fbdev/
H A Dimxfb.c178 .name = "imx21-fb",
191 .compatible = "fsl,imx21-fb",
/linux-4.1.27/drivers/mtd/nand/
H A Dmxc_nand.c1355 .name = "imx21-nand",
1378 .compatible = "fsl,imx21-nand",
/linux-4.1.27/drivers/tty/serial/
H A Dimx.c247 .name = "imx21-uart",
261 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },

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