1/* 2 * Driver for Motorola/Freescale IMX serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Author: Sascha Hauer <sascha@saschahauer.de> 7 * Copyright (C) 2004 Pengutronix 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21#define SUPPORT_SYSRQ 22#endif 23 24#include <linux/module.h> 25#include <linux/ioport.h> 26#include <linux/init.h> 27#include <linux/console.h> 28#include <linux/sysrq.h> 29#include <linux/platform_device.h> 30#include <linux/tty.h> 31#include <linux/tty_flip.h> 32#include <linux/serial_core.h> 33#include <linux/serial.h> 34#include <linux/clk.h> 35#include <linux/delay.h> 36#include <linux/rational.h> 37#include <linux/slab.h> 38#include <linux/of.h> 39#include <linux/of_device.h> 40#include <linux/io.h> 41#include <linux/dma-mapping.h> 42 43#include <asm/irq.h> 44#include <linux/platform_data/serial-imx.h> 45#include <linux/platform_data/dma-imx.h> 46 47/* Register definitions */ 48#define URXD0 0x0 /* Receiver Register */ 49#define URTX0 0x40 /* Transmitter Register */ 50#define UCR1 0x80 /* Control Register 1 */ 51#define UCR2 0x84 /* Control Register 2 */ 52#define UCR3 0x88 /* Control Register 3 */ 53#define UCR4 0x8c /* Control Register 4 */ 54#define UFCR 0x90 /* FIFO Control Register */ 55#define USR1 0x94 /* Status Register 1 */ 56#define USR2 0x98 /* Status Register 2 */ 57#define UESC 0x9c /* Escape Character Register */ 58#define UTIM 0xa0 /* Escape Timer Register */ 59#define UBIR 0xa4 /* BRM Incremental Register */ 60#define UBMR 0xa8 /* BRM Modulator Register */ 61#define UBRC 0xac /* Baud Rate Count Register */ 62#define IMX21_ONEMS 0xb0 /* One Millisecond register */ 63#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 64#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 65 66/* UART Control Register Bit Fields.*/ 67#define URXD_DUMMY_READ (1<<16) 68#define URXD_CHARRDY (1<<15) 69#define URXD_ERR (1<<14) 70#define URXD_OVRRUN (1<<13) 71#define URXD_FRMERR (1<<12) 72#define URXD_BRK (1<<11) 73#define URXD_PRERR (1<<10) 74#define URXD_RX_DATA (0xFF<<0) 75#define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 76#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 77#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 78#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 79#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 80#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 81#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 82#define UCR1_IREN (1<<7) /* Infrared interface enable */ 83#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 84#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 85#define UCR1_SNDBRK (1<<4) /* Send break */ 86#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 87#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 88#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 89#define UCR1_DOZE (1<<1) /* Doze */ 90#define UCR1_UARTEN (1<<0) /* UART enabled */ 91#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 92#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 93#define UCR2_CTSC (1<<13) /* CTS pin control */ 94#define UCR2_CTS (1<<12) /* Clear to send */ 95#define UCR2_ESCEN (1<<11) /* Escape enable */ 96#define UCR2_PREN (1<<8) /* Parity enable */ 97#define UCR2_PROE (1<<7) /* Parity odd/even */ 98#define UCR2_STPB (1<<6) /* Stop */ 99#define UCR2_WS (1<<5) /* Word size */ 100#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 101#define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 102#define UCR2_TXEN (1<<2) /* Transmitter enabled */ 103#define UCR2_RXEN (1<<1) /* Receiver enabled */ 104#define UCR2_SRST (1<<0) /* SW reset */ 105#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 106#define UCR3_PARERREN (1<<12) /* Parity enable */ 107#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 108#define UCR3_DSR (1<<10) /* Data set ready */ 109#define UCR3_DCD (1<<9) /* Data carrier detect */ 110#define UCR3_RI (1<<8) /* Ring indicator */ 111#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 112#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 113#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 114#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 115#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 116#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 117#define UCR3_BPEN (1<<0) /* Preset registers enable */ 118#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 119#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 120#define UCR4_INVR (1<<9) /* Inverted infrared reception */ 121#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 122#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 123#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 124#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 125#define UCR4_IRSC (1<<5) /* IR special case */ 126#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 127#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 128#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 129#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 130#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 131#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 132#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 133#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 136#define USR1_RTSS (1<<14) /* RTS pin status */ 137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 138#define USR1_RTSD (1<<12) /* RTS delta */ 139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 142#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ 143#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 144#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 145#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 146#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 147#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 148#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 149#define USR2_IDLE (1<<12) /* Idle condition */ 150#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 151#define USR2_WAKE (1<<7) /* Wake */ 152#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 153#define USR2_TXDC (1<<3) /* Transmitter complete */ 154#define USR2_BRCD (1<<2) /* Break condition */ 155#define USR2_ORE (1<<1) /* Overrun error */ 156#define USR2_RDR (1<<0) /* Recv data ready */ 157#define UTS_FRCPERR (1<<13) /* Force parity error */ 158#define UTS_LOOP (1<<12) /* Loop tx and rx */ 159#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 160#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 161#define UTS_TXFULL (1<<4) /* TxFIFO full */ 162#define UTS_RXFULL (1<<3) /* RxFIFO full */ 163#define UTS_SOFTRST (1<<0) /* Software reset */ 164 165/* We've been assigned a range on the "Low-density serial ports" major */ 166#define SERIAL_IMX_MAJOR 207 167#define MINOR_START 16 168#define DEV_NAME "ttymxc" 169 170/* 171 * This determines how often we check the modem status signals 172 * for any change. They generally aren't connected to an IRQ 173 * so we have to poll them. We also check immediately before 174 * filling the TX fifo incase CTS has been dropped. 175 */ 176#define MCTRL_TIMEOUT (250*HZ/1000) 177 178#define DRIVER_NAME "IMX-uart" 179 180#define UART_NR 8 181 182/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 183enum imx_uart_type { 184 IMX1_UART, 185 IMX21_UART, 186 IMX6Q_UART, 187}; 188 189/* device type dependent stuff */ 190struct imx_uart_data { 191 unsigned uts_reg; 192 enum imx_uart_type devtype; 193}; 194 195struct imx_port { 196 struct uart_port port; 197 struct timer_list timer; 198 unsigned int old_status; 199 unsigned int have_rtscts:1; 200 unsigned int dte_mode:1; 201 unsigned int irda_inv_rx:1; 202 unsigned int irda_inv_tx:1; 203 unsigned short trcv_delay; /* transceiver delay */ 204 struct clk *clk_ipg; 205 struct clk *clk_per; 206 const struct imx_uart_data *devdata; 207 208 /* DMA fields */ 209 unsigned int dma_is_inited:1; 210 unsigned int dma_is_enabled:1; 211 unsigned int dma_is_rxing:1; 212 unsigned int dma_is_txing:1; 213 struct dma_chan *dma_chan_rx, *dma_chan_tx; 214 struct scatterlist rx_sgl, tx_sgl[2]; 215 void *rx_buf; 216 unsigned int tx_bytes; 217 unsigned int dma_tx_nents; 218 wait_queue_head_t dma_wait; 219}; 220 221struct imx_port_ucrs { 222 unsigned int ucr1; 223 unsigned int ucr2; 224 unsigned int ucr3; 225}; 226 227static struct imx_uart_data imx_uart_devdata[] = { 228 [IMX1_UART] = { 229 .uts_reg = IMX1_UTS, 230 .devtype = IMX1_UART, 231 }, 232 [IMX21_UART] = { 233 .uts_reg = IMX21_UTS, 234 .devtype = IMX21_UART, 235 }, 236 [IMX6Q_UART] = { 237 .uts_reg = IMX21_UTS, 238 .devtype = IMX6Q_UART, 239 }, 240}; 241 242static struct platform_device_id imx_uart_devtype[] = { 243 { 244 .name = "imx1-uart", 245 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 246 }, { 247 .name = "imx21-uart", 248 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 249 }, { 250 .name = "imx6q-uart", 251 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 252 }, { 253 /* sentinel */ 254 } 255}; 256MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 257 258static const struct of_device_id imx_uart_dt_ids[] = { 259 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 260 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 261 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 262 { /* sentinel */ } 263}; 264MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 265 266static inline unsigned uts_reg(struct imx_port *sport) 267{ 268 return sport->devdata->uts_reg; 269} 270 271static inline int is_imx1_uart(struct imx_port *sport) 272{ 273 return sport->devdata->devtype == IMX1_UART; 274} 275 276static inline int is_imx21_uart(struct imx_port *sport) 277{ 278 return sport->devdata->devtype == IMX21_UART; 279} 280 281static inline int is_imx6q_uart(struct imx_port *sport) 282{ 283 return sport->devdata->devtype == IMX6Q_UART; 284} 285/* 286 * Save and restore functions for UCR1, UCR2 and UCR3 registers 287 */ 288#if defined(CONFIG_SERIAL_IMX_CONSOLE) 289static void imx_port_ucrs_save(struct uart_port *port, 290 struct imx_port_ucrs *ucr) 291{ 292 /* save control registers */ 293 ucr->ucr1 = readl(port->membase + UCR1); 294 ucr->ucr2 = readl(port->membase + UCR2); 295 ucr->ucr3 = readl(port->membase + UCR3); 296} 297 298static void imx_port_ucrs_restore(struct uart_port *port, 299 struct imx_port_ucrs *ucr) 300{ 301 /* restore control registers */ 302 writel(ucr->ucr1, port->membase + UCR1); 303 writel(ucr->ucr2, port->membase + UCR2); 304 writel(ucr->ucr3, port->membase + UCR3); 305} 306#endif 307 308/* 309 * Handle any change of modem status signal since we were last called. 310 */ 311static void imx_mctrl_check(struct imx_port *sport) 312{ 313 unsigned int status, changed; 314 315 status = sport->port.ops->get_mctrl(&sport->port); 316 changed = status ^ sport->old_status; 317 318 if (changed == 0) 319 return; 320 321 sport->old_status = status; 322 323 if (changed & TIOCM_RI) 324 sport->port.icount.rng++; 325 if (changed & TIOCM_DSR) 326 sport->port.icount.dsr++; 327 if (changed & TIOCM_CAR) 328 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 329 if (changed & TIOCM_CTS) 330 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 331 332 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 333} 334 335/* 336 * This is our per-port timeout handler, for checking the 337 * modem status signals. 338 */ 339static void imx_timeout(unsigned long data) 340{ 341 struct imx_port *sport = (struct imx_port *)data; 342 unsigned long flags; 343 344 if (sport->port.state) { 345 spin_lock_irqsave(&sport->port.lock, flags); 346 imx_mctrl_check(sport); 347 spin_unlock_irqrestore(&sport->port.lock, flags); 348 349 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 350 } 351} 352 353/* 354 * interrupts disabled on entry 355 */ 356static void imx_stop_tx(struct uart_port *port) 357{ 358 struct imx_port *sport = (struct imx_port *)port; 359 unsigned long temp; 360 361 /* 362 * We are maybe in the SMP context, so if the DMA TX thread is running 363 * on other cpu, we have to wait for it to finish. 364 */ 365 if (sport->dma_is_enabled && sport->dma_is_txing) 366 return; 367 368 temp = readl(port->membase + UCR1); 369 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); 370 371 /* in rs485 mode disable transmitter if shifter is empty */ 372 if (port->rs485.flags & SER_RS485_ENABLED && 373 readl(port->membase + USR2) & USR2_TXDC) { 374 temp = readl(port->membase + UCR2); 375 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 376 temp &= ~UCR2_CTS; 377 else 378 temp |= UCR2_CTS; 379 writel(temp, port->membase + UCR2); 380 381 temp = readl(port->membase + UCR4); 382 temp &= ~UCR4_TCEN; 383 writel(temp, port->membase + UCR4); 384 } 385} 386 387/* 388 * interrupts disabled on entry 389 */ 390static void imx_stop_rx(struct uart_port *port) 391{ 392 struct imx_port *sport = (struct imx_port *)port; 393 unsigned long temp; 394 395 if (sport->dma_is_enabled && sport->dma_is_rxing) { 396 if (sport->port.suspended) { 397 dmaengine_terminate_all(sport->dma_chan_rx); 398 sport->dma_is_rxing = 0; 399 } else { 400 return; 401 } 402 } 403 404 temp = readl(sport->port.membase + UCR2); 405 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); 406 407 /* disable the `Receiver Ready Interrrupt` */ 408 temp = readl(sport->port.membase + UCR1); 409 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); 410} 411 412/* 413 * Set the modem control timer to fire immediately. 414 */ 415static void imx_enable_ms(struct uart_port *port) 416{ 417 struct imx_port *sport = (struct imx_port *)port; 418 419 mod_timer(&sport->timer, jiffies); 420} 421 422static void imx_dma_tx(struct imx_port *sport); 423static inline void imx_transmit_buffer(struct imx_port *sport) 424{ 425 struct circ_buf *xmit = &sport->port.state->xmit; 426 unsigned long temp; 427 428 if (sport->port.x_char) { 429 /* Send next char */ 430 writel(sport->port.x_char, sport->port.membase + URTX0); 431 sport->port.icount.tx++; 432 sport->port.x_char = 0; 433 return; 434 } 435 436 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 437 imx_stop_tx(&sport->port); 438 return; 439 } 440 441 if (sport->dma_is_enabled) { 442 /* 443 * We've just sent a X-char Ensure the TX DMA is enabled 444 * and the TX IRQ is disabled. 445 **/ 446 temp = readl(sport->port.membase + UCR1); 447 temp &= ~UCR1_TXMPTYEN; 448 if (sport->dma_is_txing) { 449 temp |= UCR1_TDMAEN; 450 writel(temp, sport->port.membase + UCR1); 451 } else { 452 writel(temp, sport->port.membase + UCR1); 453 imx_dma_tx(sport); 454 } 455 } 456 457 while (!uart_circ_empty(xmit) && 458 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { 459 /* send xmit->buf[xmit->tail] 460 * out the port here */ 461 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); 462 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 463 sport->port.icount.tx++; 464 } 465 466 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 467 uart_write_wakeup(&sport->port); 468 469 if (uart_circ_empty(xmit)) 470 imx_stop_tx(&sport->port); 471} 472 473static void dma_tx_callback(void *data) 474{ 475 struct imx_port *sport = data; 476 struct scatterlist *sgl = &sport->tx_sgl[0]; 477 struct circ_buf *xmit = &sport->port.state->xmit; 478 unsigned long flags; 479 unsigned long temp; 480 481 spin_lock_irqsave(&sport->port.lock, flags); 482 483 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 484 485 temp = readl(sport->port.membase + UCR1); 486 temp &= ~UCR1_TDMAEN; 487 writel(temp, sport->port.membase + UCR1); 488 489 /* update the stat */ 490 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 491 sport->port.icount.tx += sport->tx_bytes; 492 493 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 494 495 sport->dma_is_txing = 0; 496 497 spin_unlock_irqrestore(&sport->port.lock, flags); 498 499 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 500 uart_write_wakeup(&sport->port); 501 502 if (waitqueue_active(&sport->dma_wait)) { 503 wake_up(&sport->dma_wait); 504 dev_dbg(sport->port.dev, "exit in %s.\n", __func__); 505 return; 506 } 507 508 spin_lock_irqsave(&sport->port.lock, flags); 509 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 510 imx_dma_tx(sport); 511 spin_unlock_irqrestore(&sport->port.lock, flags); 512} 513 514static void imx_dma_tx(struct imx_port *sport) 515{ 516 struct circ_buf *xmit = &sport->port.state->xmit; 517 struct scatterlist *sgl = sport->tx_sgl; 518 struct dma_async_tx_descriptor *desc; 519 struct dma_chan *chan = sport->dma_chan_tx; 520 struct device *dev = sport->port.dev; 521 unsigned long temp; 522 int ret; 523 524 if (sport->dma_is_txing) 525 return; 526 527 sport->tx_bytes = uart_circ_chars_pending(xmit); 528 529 if (xmit->tail < xmit->head) { 530 sport->dma_tx_nents = 1; 531 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 532 } else { 533 sport->dma_tx_nents = 2; 534 sg_init_table(sgl, 2); 535 sg_set_buf(sgl, xmit->buf + xmit->tail, 536 UART_XMIT_SIZE - xmit->tail); 537 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 538 } 539 540 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 541 if (ret == 0) { 542 dev_err(dev, "DMA mapping error for TX.\n"); 543 return; 544 } 545 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 546 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 547 if (!desc) { 548 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 549 DMA_TO_DEVICE); 550 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 551 return; 552 } 553 desc->callback = dma_tx_callback; 554 desc->callback_param = sport; 555 556 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 557 uart_circ_chars_pending(xmit)); 558 559 temp = readl(sport->port.membase + UCR1); 560 temp |= UCR1_TDMAEN; 561 writel(temp, sport->port.membase + UCR1); 562 563 /* fire it */ 564 sport->dma_is_txing = 1; 565 dmaengine_submit(desc); 566 dma_async_issue_pending(chan); 567 return; 568} 569 570/* 571 * interrupts disabled on entry 572 */ 573static void imx_start_tx(struct uart_port *port) 574{ 575 struct imx_port *sport = (struct imx_port *)port; 576 unsigned long temp; 577 578 if (port->rs485.flags & SER_RS485_ENABLED) { 579 /* enable transmitter and shifter empty irq */ 580 temp = readl(port->membase + UCR2); 581 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 582 temp &= ~UCR2_CTS; 583 else 584 temp |= UCR2_CTS; 585 writel(temp, port->membase + UCR2); 586 587 temp = readl(port->membase + UCR4); 588 temp |= UCR4_TCEN; 589 writel(temp, port->membase + UCR4); 590 } 591 592 if (!sport->dma_is_enabled) { 593 temp = readl(sport->port.membase + UCR1); 594 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); 595 } 596 597 if (sport->dma_is_enabled) { 598 if (sport->port.x_char) { 599 /* We have X-char to send, so enable TX IRQ and 600 * disable TX DMA to let TX interrupt to send X-char */ 601 temp = readl(sport->port.membase + UCR1); 602 temp &= ~UCR1_TDMAEN; 603 temp |= UCR1_TXMPTYEN; 604 writel(temp, sport->port.membase + UCR1); 605 return; 606 } 607 608 if (!uart_circ_empty(&port->state->xmit) && 609 !uart_tx_stopped(port)) 610 imx_dma_tx(sport); 611 return; 612 } 613} 614 615static irqreturn_t imx_rtsint(int irq, void *dev_id) 616{ 617 struct imx_port *sport = dev_id; 618 unsigned int val; 619 unsigned long flags; 620 621 spin_lock_irqsave(&sport->port.lock, flags); 622 623 writel(USR1_RTSD, sport->port.membase + USR1); 624 val = readl(sport->port.membase + USR1) & USR1_RTSS; 625 uart_handle_cts_change(&sport->port, !!val); 626 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 627 628 spin_unlock_irqrestore(&sport->port.lock, flags); 629 return IRQ_HANDLED; 630} 631 632static irqreturn_t imx_txint(int irq, void *dev_id) 633{ 634 struct imx_port *sport = dev_id; 635 unsigned long flags; 636 637 spin_lock_irqsave(&sport->port.lock, flags); 638 imx_transmit_buffer(sport); 639 spin_unlock_irqrestore(&sport->port.lock, flags); 640 return IRQ_HANDLED; 641} 642 643static irqreturn_t imx_rxint(int irq, void *dev_id) 644{ 645 struct imx_port *sport = dev_id; 646 unsigned int rx, flg, ignored = 0; 647 struct tty_port *port = &sport->port.state->port; 648 unsigned long flags, temp; 649 650 spin_lock_irqsave(&sport->port.lock, flags); 651 652 while (readl(sport->port.membase + USR2) & USR2_RDR) { 653 flg = TTY_NORMAL; 654 sport->port.icount.rx++; 655 656 rx = readl(sport->port.membase + URXD0); 657 658 temp = readl(sport->port.membase + USR2); 659 if (temp & USR2_BRCD) { 660 writel(USR2_BRCD, sport->port.membase + USR2); 661 if (uart_handle_break(&sport->port)) 662 continue; 663 } 664 665 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 666 continue; 667 668 if (unlikely(rx & URXD_ERR)) { 669 if (rx & URXD_BRK) 670 sport->port.icount.brk++; 671 else if (rx & URXD_PRERR) 672 sport->port.icount.parity++; 673 else if (rx & URXD_FRMERR) 674 sport->port.icount.frame++; 675 if (rx & URXD_OVRRUN) 676 sport->port.icount.overrun++; 677 678 if (rx & sport->port.ignore_status_mask) { 679 if (++ignored > 100) 680 goto out; 681 continue; 682 } 683 684 rx &= (sport->port.read_status_mask | 0xFF); 685 686 if (rx & URXD_BRK) 687 flg = TTY_BREAK; 688 else if (rx & URXD_PRERR) 689 flg = TTY_PARITY; 690 else if (rx & URXD_FRMERR) 691 flg = TTY_FRAME; 692 if (rx & URXD_OVRRUN) 693 flg = TTY_OVERRUN; 694 695#ifdef SUPPORT_SYSRQ 696 sport->port.sysrq = 0; 697#endif 698 } 699 700 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 701 goto out; 702 703 tty_insert_flip_char(port, rx, flg); 704 } 705 706out: 707 spin_unlock_irqrestore(&sport->port.lock, flags); 708 tty_flip_buffer_push(port); 709 return IRQ_HANDLED; 710} 711 712static int start_rx_dma(struct imx_port *sport); 713/* 714 * If the RXFIFO is filled with some data, and then we 715 * arise a DMA operation to receive them. 716 */ 717static void imx_dma_rxint(struct imx_port *sport) 718{ 719 unsigned long temp; 720 unsigned long flags; 721 722 spin_lock_irqsave(&sport->port.lock, flags); 723 724 temp = readl(sport->port.membase + USR2); 725 if ((temp & USR2_RDR) && !sport->dma_is_rxing) { 726 sport->dma_is_rxing = 1; 727 728 /* disable the `Recerver Ready Interrrupt` */ 729 temp = readl(sport->port.membase + UCR1); 730 temp &= ~(UCR1_RRDYEN); 731 writel(temp, sport->port.membase + UCR1); 732 733 /* tell the DMA to receive the data. */ 734 start_rx_dma(sport); 735 } 736 737 spin_unlock_irqrestore(&sport->port.lock, flags); 738} 739 740static irqreturn_t imx_int(int irq, void *dev_id) 741{ 742 struct imx_port *sport = dev_id; 743 unsigned int sts; 744 unsigned int sts2; 745 746 sts = readl(sport->port.membase + USR1); 747 sts2 = readl(sport->port.membase + USR2); 748 749 if (sts & USR1_RRDY) { 750 if (sport->dma_is_enabled) 751 imx_dma_rxint(sport); 752 else 753 imx_rxint(irq, dev_id); 754 } 755 756 if ((sts & USR1_TRDY && 757 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || 758 (sts2 & USR2_TXDC && 759 readl(sport->port.membase + UCR4) & UCR4_TCEN)) 760 imx_txint(irq, dev_id); 761 762 if (sts & USR1_RTSD) 763 imx_rtsint(irq, dev_id); 764 765 if (sts & USR1_AWAKE) 766 writel(USR1_AWAKE, sport->port.membase + USR1); 767 768 if (sts2 & USR2_ORE) { 769 dev_err(sport->port.dev, "Rx FIFO overrun\n"); 770 sport->port.icount.overrun++; 771 writel(USR2_ORE, sport->port.membase + USR2); 772 } 773 774 return IRQ_HANDLED; 775} 776 777/* 778 * Return TIOCSER_TEMT when transmitter is not busy. 779 */ 780static unsigned int imx_tx_empty(struct uart_port *port) 781{ 782 struct imx_port *sport = (struct imx_port *)port; 783 unsigned int ret; 784 785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 786 787 /* If the TX DMA is working, return 0. */ 788 if (sport->dma_is_enabled && sport->dma_is_txing) 789 ret = 0; 790 791 return ret; 792} 793 794/* 795 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 796 */ 797static unsigned int imx_get_mctrl(struct uart_port *port) 798{ 799 struct imx_port *sport = (struct imx_port *)port; 800 unsigned int tmp = TIOCM_DSR | TIOCM_CAR; 801 802 if (readl(sport->port.membase + USR1) & USR1_RTSS) 803 tmp |= TIOCM_CTS; 804 805 if (readl(sport->port.membase + UCR2) & UCR2_CTS) 806 tmp |= TIOCM_RTS; 807 808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) 809 tmp |= TIOCM_LOOP; 810 811 return tmp; 812} 813 814static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 815{ 816 struct imx_port *sport = (struct imx_port *)port; 817 unsigned long temp; 818 819 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 820 temp = readl(sport->port.membase + UCR2); 821 temp &= ~(UCR2_CTS | UCR2_CTSC); 822 if (mctrl & TIOCM_RTS) 823 temp |= UCR2_CTS | UCR2_CTSC; 824 writel(temp, sport->port.membase + UCR2); 825 } 826 827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; 828 if (mctrl & TIOCM_LOOP) 829 temp |= UTS_LOOP; 830 writel(temp, sport->port.membase + uts_reg(sport)); 831} 832 833/* 834 * Interrupts always disabled. 835 */ 836static void imx_break_ctl(struct uart_port *port, int break_state) 837{ 838 struct imx_port *sport = (struct imx_port *)port; 839 unsigned long flags, temp; 840 841 spin_lock_irqsave(&sport->port.lock, flags); 842 843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; 844 845 if (break_state != 0) 846 temp |= UCR1_SNDBRK; 847 848 writel(temp, sport->port.membase + UCR1); 849 850 spin_unlock_irqrestore(&sport->port.lock, flags); 851} 852 853#define TXTL 2 /* reset default */ 854#define RXTL 1 /* reset default */ 855 856static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) 857{ 858 unsigned int val; 859 860 /* set receiver / transmitter trigger level */ 861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 862 val |= TXTL << UFCR_TXTL_SHF | RXTL; 863 writel(val, sport->port.membase + UFCR); 864 return 0; 865} 866 867#define RX_BUF_SIZE (PAGE_SIZE) 868static void imx_rx_dma_done(struct imx_port *sport) 869{ 870 unsigned long temp; 871 unsigned long flags; 872 873 spin_lock_irqsave(&sport->port.lock, flags); 874 875 /* Enable this interrupt when the RXFIFO is empty. */ 876 temp = readl(sport->port.membase + UCR1); 877 temp |= UCR1_RRDYEN; 878 writel(temp, sport->port.membase + UCR1); 879 880 sport->dma_is_rxing = 0; 881 882 /* Is the shutdown waiting for us? */ 883 if (waitqueue_active(&sport->dma_wait)) 884 wake_up(&sport->dma_wait); 885 886 spin_unlock_irqrestore(&sport->port.lock, flags); 887} 888 889/* 890 * There are three kinds of RX DMA interrupts(such as in the MX6Q): 891 * [1] the RX DMA buffer is full. 892 * [2] the Aging timer expires(wait for 8 bytes long) 893 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). 894 * 895 * The [2] is trigger when a character was been sitting in the FIFO 896 * meanwhile [3] can wait for 32 bytes long when the RX line is 897 * on IDLE state and RxFIFO is empty. 898 */ 899static void dma_rx_callback(void *data) 900{ 901 struct imx_port *sport = data; 902 struct dma_chan *chan = sport->dma_chan_rx; 903 struct scatterlist *sgl = &sport->rx_sgl; 904 struct tty_port *port = &sport->port.state->port; 905 struct dma_tx_state state; 906 enum dma_status status; 907 unsigned int count; 908 909 /* unmap it first */ 910 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); 911 912 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); 913 count = RX_BUF_SIZE - state.residue; 914 915 if (readl(sport->port.membase + USR2) & USR2_IDLE) { 916 /* In condition [3] the SDMA counted up too early */ 917 count--; 918 919 writel(USR2_IDLE, sport->port.membase + USR2); 920 } 921 922 dev_dbg(sport->port.dev, "We get %d bytes.\n", count); 923 924 if (count) { 925 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) 926 tty_insert_flip_string(port, sport->rx_buf, count); 927 tty_flip_buffer_push(port); 928 929 start_rx_dma(sport); 930 } else if (readl(sport->port.membase + USR2) & USR2_RDR) { 931 /* 932 * start rx_dma directly once data in RXFIFO, more efficient 933 * than before: 934 * 1. call imx_rx_dma_done to stop dma if no data received 935 * 2. wait next RDR interrupt to start dma transfer. 936 */ 937 start_rx_dma(sport); 938 } else { 939 /* 940 * stop dma to prevent too many IDLE event trigged if no data 941 * in RXFIFO 942 */ 943 imx_rx_dma_done(sport); 944 } 945} 946 947static int start_rx_dma(struct imx_port *sport) 948{ 949 struct scatterlist *sgl = &sport->rx_sgl; 950 struct dma_chan *chan = sport->dma_chan_rx; 951 struct device *dev = sport->port.dev; 952 struct dma_async_tx_descriptor *desc; 953 int ret; 954 955 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 956 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 957 if (ret == 0) { 958 dev_err(dev, "DMA mapping error for RX.\n"); 959 return -EINVAL; 960 } 961 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, 962 DMA_PREP_INTERRUPT); 963 if (!desc) { 964 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 965 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 966 return -EINVAL; 967 } 968 desc->callback = dma_rx_callback; 969 desc->callback_param = sport; 970 971 dev_dbg(dev, "RX: prepare for the DMA.\n"); 972 dmaengine_submit(desc); 973 dma_async_issue_pending(chan); 974 return 0; 975} 976 977static void imx_uart_dma_exit(struct imx_port *sport) 978{ 979 if (sport->dma_chan_rx) { 980 dma_release_channel(sport->dma_chan_rx); 981 sport->dma_chan_rx = NULL; 982 983 kfree(sport->rx_buf); 984 sport->rx_buf = NULL; 985 } 986 987 if (sport->dma_chan_tx) { 988 dma_release_channel(sport->dma_chan_tx); 989 sport->dma_chan_tx = NULL; 990 } 991 992 sport->dma_is_inited = 0; 993} 994 995static int imx_uart_dma_init(struct imx_port *sport) 996{ 997 struct dma_slave_config slave_config = {}; 998 struct device *dev = sport->port.dev; 999 int ret; 1000 1001 /* Prepare for RX : */ 1002 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1003 if (!sport->dma_chan_rx) { 1004 dev_dbg(dev, "cannot get the DMA channel.\n"); 1005 ret = -EINVAL; 1006 goto err; 1007 } 1008 1009 slave_config.direction = DMA_DEV_TO_MEM; 1010 slave_config.src_addr = sport->port.mapbase + URXD0; 1011 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1012 slave_config.src_maxburst = RXTL; 1013 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1014 if (ret) { 1015 dev_err(dev, "error in RX dma configuration.\n"); 1016 goto err; 1017 } 1018 1019 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 1020 if (!sport->rx_buf) { 1021 ret = -ENOMEM; 1022 goto err; 1023 } 1024 1025 /* Prepare for TX : */ 1026 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1027 if (!sport->dma_chan_tx) { 1028 dev_err(dev, "cannot get the TX DMA channel!\n"); 1029 ret = -EINVAL; 1030 goto err; 1031 } 1032 1033 slave_config.direction = DMA_MEM_TO_DEV; 1034 slave_config.dst_addr = sport->port.mapbase + URTX0; 1035 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1036 slave_config.dst_maxburst = TXTL; 1037 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1038 if (ret) { 1039 dev_err(dev, "error in TX dma configuration."); 1040 goto err; 1041 } 1042 1043 sport->dma_is_inited = 1; 1044 1045 return 0; 1046err: 1047 imx_uart_dma_exit(sport); 1048 return ret; 1049} 1050 1051static void imx_enable_dma(struct imx_port *sport) 1052{ 1053 unsigned long temp; 1054 1055 init_waitqueue_head(&sport->dma_wait); 1056 1057 /* set UCR1 */ 1058 temp = readl(sport->port.membase + UCR1); 1059 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | 1060 /* wait for 32 idle frames for IDDMA interrupt */ 1061 UCR1_ICD_REG(3); 1062 writel(temp, sport->port.membase + UCR1); 1063 1064 /* set UCR4 */ 1065 temp = readl(sport->port.membase + UCR4); 1066 temp |= UCR4_IDDMAEN; 1067 writel(temp, sport->port.membase + UCR4); 1068 1069 sport->dma_is_enabled = 1; 1070} 1071 1072static void imx_disable_dma(struct imx_port *sport) 1073{ 1074 unsigned long temp; 1075 1076 /* clear UCR1 */ 1077 temp = readl(sport->port.membase + UCR1); 1078 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); 1079 writel(temp, sport->port.membase + UCR1); 1080 1081 /* clear UCR2 */ 1082 temp = readl(sport->port.membase + UCR2); 1083 temp &= ~(UCR2_CTSC | UCR2_CTS); 1084 writel(temp, sport->port.membase + UCR2); 1085 1086 /* clear UCR4 */ 1087 temp = readl(sport->port.membase + UCR4); 1088 temp &= ~UCR4_IDDMAEN; 1089 writel(temp, sport->port.membase + UCR4); 1090 1091 sport->dma_is_enabled = 0; 1092} 1093 1094/* half the RX buffer size */ 1095#define CTSTL 16 1096 1097static int imx_startup(struct uart_port *port) 1098{ 1099 struct imx_port *sport = (struct imx_port *)port; 1100 int retval, i; 1101 unsigned long flags, temp; 1102 1103 retval = clk_prepare_enable(sport->clk_per); 1104 if (retval) 1105 return retval; 1106 retval = clk_prepare_enable(sport->clk_ipg); 1107 if (retval) { 1108 clk_disable_unprepare(sport->clk_per); 1109 return retval; 1110 } 1111 1112 imx_setup_ufcr(sport, 0); 1113 1114 /* disable the DREN bit (Data Ready interrupt enable) before 1115 * requesting IRQs 1116 */ 1117 temp = readl(sport->port.membase + UCR4); 1118 1119 /* set the trigger level for CTS */ 1120 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1121 temp |= CTSTL << UCR4_CTSTL_SHF; 1122 1123 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); 1124 1125 /* Reset fifo's and state machines */ 1126 i = 100; 1127 1128 temp = readl(sport->port.membase + UCR2); 1129 temp &= ~UCR2_SRST; 1130 writel(temp, sport->port.membase + UCR2); 1131 1132 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1133 udelay(1); 1134 1135 spin_lock_irqsave(&sport->port.lock, flags); 1136 1137 /* 1138 * Finally, clear and enable interrupts 1139 */ 1140 writel(USR1_RTSD, sport->port.membase + USR1); 1141 writel(USR2_ORE, sport->port.membase + USR2); 1142 1143 temp = readl(sport->port.membase + UCR1); 1144 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; 1145 1146 writel(temp, sport->port.membase + UCR1); 1147 1148 temp = readl(sport->port.membase + UCR4); 1149 temp |= UCR4_OREN; 1150 writel(temp, sport->port.membase + UCR4); 1151 1152 temp = readl(sport->port.membase + UCR2); 1153 temp |= (UCR2_RXEN | UCR2_TXEN); 1154 if (!sport->have_rtscts) 1155 temp |= UCR2_IRTS; 1156 writel(temp, sport->port.membase + UCR2); 1157 1158 if (!is_imx1_uart(sport)) { 1159 temp = readl(sport->port.membase + UCR3); 1160 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 1161 writel(temp, sport->port.membase + UCR3); 1162 } 1163 1164 /* 1165 * Enable modem status interrupts 1166 */ 1167 imx_enable_ms(&sport->port); 1168 spin_unlock_irqrestore(&sport->port.lock, flags); 1169 1170 return 0; 1171} 1172 1173static void imx_shutdown(struct uart_port *port) 1174{ 1175 struct imx_port *sport = (struct imx_port *)port; 1176 unsigned long temp; 1177 unsigned long flags; 1178 1179 if (sport->dma_is_enabled) { 1180 int ret; 1181 1182 /* We have to wait for the DMA to finish. */ 1183 ret = wait_event_interruptible(sport->dma_wait, 1184 !sport->dma_is_rxing && !sport->dma_is_txing); 1185 if (ret != 0) { 1186 sport->dma_is_rxing = 0; 1187 sport->dma_is_txing = 0; 1188 dmaengine_terminate_all(sport->dma_chan_tx); 1189 dmaengine_terminate_all(sport->dma_chan_rx); 1190 } 1191 spin_lock_irqsave(&sport->port.lock, flags); 1192 imx_stop_tx(port); 1193 imx_stop_rx(port); 1194 imx_disable_dma(sport); 1195 spin_unlock_irqrestore(&sport->port.lock, flags); 1196 imx_uart_dma_exit(sport); 1197 } 1198 1199 spin_lock_irqsave(&sport->port.lock, flags); 1200 temp = readl(sport->port.membase + UCR2); 1201 temp &= ~(UCR2_TXEN); 1202 writel(temp, sport->port.membase + UCR2); 1203 spin_unlock_irqrestore(&sport->port.lock, flags); 1204 1205 /* 1206 * Stop our timer. 1207 */ 1208 del_timer_sync(&sport->timer); 1209 1210 /* 1211 * Disable all interrupts, port and break condition. 1212 */ 1213 1214 spin_lock_irqsave(&sport->port.lock, flags); 1215 temp = readl(sport->port.membase + UCR1); 1216 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1217 1218 writel(temp, sport->port.membase + UCR1); 1219 spin_unlock_irqrestore(&sport->port.lock, flags); 1220 1221 clk_disable_unprepare(sport->clk_per); 1222 clk_disable_unprepare(sport->clk_ipg); 1223} 1224 1225static void imx_flush_buffer(struct uart_port *port) 1226{ 1227 struct imx_port *sport = (struct imx_port *)port; 1228 struct scatterlist *sgl = &sport->tx_sgl[0]; 1229 unsigned long temp; 1230 int i = 100, ubir, ubmr, uts; 1231 1232 if (!sport->dma_chan_tx) 1233 return; 1234 1235 sport->tx_bytes = 0; 1236 dmaengine_terminate_all(sport->dma_chan_tx); 1237 if (sport->dma_is_txing) { 1238 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1239 DMA_TO_DEVICE); 1240 temp = readl(sport->port.membase + UCR1); 1241 temp &= ~UCR1_TDMAEN; 1242 writel(temp, sport->port.membase + UCR1); 1243 sport->dma_is_txing = false; 1244 } 1245 1246 /* 1247 * According to the Reference Manual description of the UART SRST bit: 1248 * "Reset the transmit and receive state machines, 1249 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1250 * and UTS[6-3]". As we don't need to restore the old values from 1251 * USR1, USR2, URXD, UTXD, only save/restore the other four registers 1252 */ 1253 ubir = readl(sport->port.membase + UBIR); 1254 ubmr = readl(sport->port.membase + UBMR); 1255 uts = readl(sport->port.membase + IMX21_UTS); 1256 1257 temp = readl(sport->port.membase + UCR2); 1258 temp &= ~UCR2_SRST; 1259 writel(temp, sport->port.membase + UCR2); 1260 1261 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) 1262 udelay(1); 1263 1264 /* Restore the registers */ 1265 writel(ubir, sport->port.membase + UBIR); 1266 writel(ubmr, sport->port.membase + UBMR); 1267 writel(uts, sport->port.membase + IMX21_UTS); 1268} 1269 1270static void 1271imx_set_termios(struct uart_port *port, struct ktermios *termios, 1272 struct ktermios *old) 1273{ 1274 struct imx_port *sport = (struct imx_port *)port; 1275 unsigned long flags; 1276 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; 1277 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1278 unsigned int div, ufcr; 1279 unsigned long num, denom; 1280 uint64_t tdiv64; 1281 1282 /* 1283 * We only support CS7 and CS8. 1284 */ 1285 while ((termios->c_cflag & CSIZE) != CS7 && 1286 (termios->c_cflag & CSIZE) != CS8) { 1287 termios->c_cflag &= ~CSIZE; 1288 termios->c_cflag |= old_csize; 1289 old_csize = CS8; 1290 } 1291 1292 if ((termios->c_cflag & CSIZE) == CS8) 1293 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; 1294 else 1295 ucr2 = UCR2_SRST | UCR2_IRTS; 1296 1297 if (termios->c_cflag & CRTSCTS) { 1298 if (sport->have_rtscts) { 1299 ucr2 &= ~UCR2_IRTS; 1300 1301 if (port->rs485.flags & SER_RS485_ENABLED) { 1302 /* 1303 * RTS is mandatory for rs485 operation, so keep 1304 * it under manual control and keep transmitter 1305 * disabled. 1306 */ 1307 if (!(port->rs485.flags & 1308 SER_RS485_RTS_AFTER_SEND)) 1309 ucr2 |= UCR2_CTS; 1310 } else { 1311 ucr2 |= UCR2_CTSC; 1312 } 1313 1314 /* Can we enable the DMA support? */ 1315 if (is_imx6q_uart(sport) && !uart_console(port) 1316 && !sport->dma_is_inited) 1317 imx_uart_dma_init(sport); 1318 } else { 1319 termios->c_cflag &= ~CRTSCTS; 1320 } 1321 } else if (port->rs485.flags & SER_RS485_ENABLED) 1322 /* disable transmitter */ 1323 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND)) 1324 ucr2 |= UCR2_CTS; 1325 1326 if (termios->c_cflag & CSTOPB) 1327 ucr2 |= UCR2_STPB; 1328 if (termios->c_cflag & PARENB) { 1329 ucr2 |= UCR2_PREN; 1330 if (termios->c_cflag & PARODD) 1331 ucr2 |= UCR2_PROE; 1332 } 1333 1334 del_timer_sync(&sport->timer); 1335 1336 /* 1337 * Ask the core to calculate the divisor for us. 1338 */ 1339 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1340 quot = uart_get_divisor(port, baud); 1341 1342 spin_lock_irqsave(&sport->port.lock, flags); 1343 1344 sport->port.read_status_mask = 0; 1345 if (termios->c_iflag & INPCK) 1346 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1347 if (termios->c_iflag & (BRKINT | PARMRK)) 1348 sport->port.read_status_mask |= URXD_BRK; 1349 1350 /* 1351 * Characters to ignore 1352 */ 1353 sport->port.ignore_status_mask = 0; 1354 if (termios->c_iflag & IGNPAR) 1355 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1356 if (termios->c_iflag & IGNBRK) { 1357 sport->port.ignore_status_mask |= URXD_BRK; 1358 /* 1359 * If we're ignoring parity and break indicators, 1360 * ignore overruns too (for real raw support). 1361 */ 1362 if (termios->c_iflag & IGNPAR) 1363 sport->port.ignore_status_mask |= URXD_OVRRUN; 1364 } 1365 1366 if ((termios->c_cflag & CREAD) == 0) 1367 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1368 1369 /* 1370 * Update the per-port timeout. 1371 */ 1372 uart_update_timeout(port, termios->c_cflag, baud); 1373 1374 /* 1375 * disable interrupts and drain transmitter 1376 */ 1377 old_ucr1 = readl(sport->port.membase + UCR1); 1378 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), 1379 sport->port.membase + UCR1); 1380 1381 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) 1382 barrier(); 1383 1384 /* then, disable everything */ 1385 old_txrxen = readl(sport->port.membase + UCR2); 1386 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), 1387 sport->port.membase + UCR2); 1388 old_txrxen &= (UCR2_TXEN | UCR2_RXEN); 1389 1390 /* custom-baudrate handling */ 1391 div = sport->port.uartclk / (baud * 16); 1392 if (baud == 38400 && quot != div) 1393 baud = sport->port.uartclk / (quot * 16); 1394 1395 div = sport->port.uartclk / (baud * 16); 1396 if (div > 7) 1397 div = 7; 1398 if (!div) 1399 div = 1; 1400 1401 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1402 1 << 16, 1 << 16, &num, &denom); 1403 1404 tdiv64 = sport->port.uartclk; 1405 tdiv64 *= num; 1406 do_div(tdiv64, denom * 16 * div); 1407 tty_termios_encode_baud_rate(termios, 1408 (speed_t)tdiv64, (speed_t)tdiv64); 1409 1410 num -= 1; 1411 denom -= 1; 1412 1413 ufcr = readl(sport->port.membase + UFCR); 1414 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1415 if (sport->dte_mode) 1416 ufcr |= UFCR_DCEDTE; 1417 writel(ufcr, sport->port.membase + UFCR); 1418 1419 writel(num, sport->port.membase + UBIR); 1420 writel(denom, sport->port.membase + UBMR); 1421 1422 if (!is_imx1_uart(sport)) 1423 writel(sport->port.uartclk / div / 1000, 1424 sport->port.membase + IMX21_ONEMS); 1425 1426 writel(old_ucr1, sport->port.membase + UCR1); 1427 1428 /* set the parity, stop bits and data size */ 1429 writel(ucr2 | old_txrxen, sport->port.membase + UCR2); 1430 1431 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1432 imx_enable_ms(&sport->port); 1433 1434 if (sport->dma_is_inited && !sport->dma_is_enabled) 1435 imx_enable_dma(sport); 1436 spin_unlock_irqrestore(&sport->port.lock, flags); 1437} 1438 1439static const char *imx_type(struct uart_port *port) 1440{ 1441 struct imx_port *sport = (struct imx_port *)port; 1442 1443 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1444} 1445 1446/* 1447 * Configure/autoconfigure the port. 1448 */ 1449static void imx_config_port(struct uart_port *port, int flags) 1450{ 1451 struct imx_port *sport = (struct imx_port *)port; 1452 1453 if (flags & UART_CONFIG_TYPE) 1454 sport->port.type = PORT_IMX; 1455} 1456 1457/* 1458 * Verify the new serial_struct (for TIOCSSERIAL). 1459 * The only change we allow are to the flags and type, and 1460 * even then only between PORT_IMX and PORT_UNKNOWN 1461 */ 1462static int 1463imx_verify_port(struct uart_port *port, struct serial_struct *ser) 1464{ 1465 struct imx_port *sport = (struct imx_port *)port; 1466 int ret = 0; 1467 1468 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1469 ret = -EINVAL; 1470 if (sport->port.irq != ser->irq) 1471 ret = -EINVAL; 1472 if (ser->io_type != UPIO_MEM) 1473 ret = -EINVAL; 1474 if (sport->port.uartclk / 16 != ser->baud_base) 1475 ret = -EINVAL; 1476 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1477 ret = -EINVAL; 1478 if (sport->port.iobase != ser->port) 1479 ret = -EINVAL; 1480 if (ser->hub6 != 0) 1481 ret = -EINVAL; 1482 return ret; 1483} 1484 1485#if defined(CONFIG_CONSOLE_POLL) 1486 1487static int imx_poll_init(struct uart_port *port) 1488{ 1489 struct imx_port *sport = (struct imx_port *)port; 1490 unsigned long flags; 1491 unsigned long temp; 1492 int retval; 1493 1494 retval = clk_prepare_enable(sport->clk_ipg); 1495 if (retval) 1496 return retval; 1497 retval = clk_prepare_enable(sport->clk_per); 1498 if (retval) 1499 clk_disable_unprepare(sport->clk_ipg); 1500 1501 imx_setup_ufcr(sport, 0); 1502 1503 spin_lock_irqsave(&sport->port.lock, flags); 1504 1505 temp = readl(sport->port.membase + UCR1); 1506 if (is_imx1_uart(sport)) 1507 temp |= IMX1_UCR1_UARTCLKEN; 1508 temp |= UCR1_UARTEN | UCR1_RRDYEN; 1509 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 1510 writel(temp, sport->port.membase + UCR1); 1511 1512 temp = readl(sport->port.membase + UCR2); 1513 temp |= UCR2_RXEN; 1514 writel(temp, sport->port.membase + UCR2); 1515 1516 spin_unlock_irqrestore(&sport->port.lock, flags); 1517 1518 return 0; 1519} 1520 1521static int imx_poll_get_char(struct uart_port *port) 1522{ 1523 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) 1524 return NO_POLL_CHAR; 1525 1526 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; 1527} 1528 1529static void imx_poll_put_char(struct uart_port *port, unsigned char c) 1530{ 1531 unsigned int status; 1532 1533 /* drain */ 1534 do { 1535 status = readl_relaxed(port->membase + USR1); 1536 } while (~status & USR1_TRDY); 1537 1538 /* write */ 1539 writel_relaxed(c, port->membase + URTX0); 1540 1541 /* flush */ 1542 do { 1543 status = readl_relaxed(port->membase + USR2); 1544 } while (~status & USR2_TXDC); 1545} 1546#endif 1547 1548static int imx_rs485_config(struct uart_port *port, 1549 struct serial_rs485 *rs485conf) 1550{ 1551 struct imx_port *sport = (struct imx_port *)port; 1552 1553 /* unimplemented */ 1554 rs485conf->delay_rts_before_send = 0; 1555 rs485conf->delay_rts_after_send = 0; 1556 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1557 1558 /* RTS is required to control the transmitter */ 1559 if (!sport->have_rtscts) 1560 rs485conf->flags &= ~SER_RS485_ENABLED; 1561 1562 if (rs485conf->flags & SER_RS485_ENABLED) { 1563 unsigned long temp; 1564 1565 /* disable transmitter */ 1566 temp = readl(sport->port.membase + UCR2); 1567 temp &= ~UCR2_CTSC; 1568 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1569 temp &= ~UCR2_CTS; 1570 else 1571 temp |= UCR2_CTS; 1572 writel(temp, sport->port.membase + UCR2); 1573 } 1574 1575 port->rs485 = *rs485conf; 1576 1577 return 0; 1578} 1579 1580static struct uart_ops imx_pops = { 1581 .tx_empty = imx_tx_empty, 1582 .set_mctrl = imx_set_mctrl, 1583 .get_mctrl = imx_get_mctrl, 1584 .stop_tx = imx_stop_tx, 1585 .start_tx = imx_start_tx, 1586 .stop_rx = imx_stop_rx, 1587 .enable_ms = imx_enable_ms, 1588 .break_ctl = imx_break_ctl, 1589 .startup = imx_startup, 1590 .shutdown = imx_shutdown, 1591 .flush_buffer = imx_flush_buffer, 1592 .set_termios = imx_set_termios, 1593 .type = imx_type, 1594 .config_port = imx_config_port, 1595 .verify_port = imx_verify_port, 1596#if defined(CONFIG_CONSOLE_POLL) 1597 .poll_init = imx_poll_init, 1598 .poll_get_char = imx_poll_get_char, 1599 .poll_put_char = imx_poll_put_char, 1600#endif 1601}; 1602 1603static struct imx_port *imx_ports[UART_NR]; 1604 1605#ifdef CONFIG_SERIAL_IMX_CONSOLE 1606static void imx_console_putchar(struct uart_port *port, int ch) 1607{ 1608 struct imx_port *sport = (struct imx_port *)port; 1609 1610 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) 1611 barrier(); 1612 1613 writel(ch, sport->port.membase + URTX0); 1614} 1615 1616/* 1617 * Interrupts are disabled on entering 1618 */ 1619static void 1620imx_console_write(struct console *co, const char *s, unsigned int count) 1621{ 1622 struct imx_port *sport = imx_ports[co->index]; 1623 struct imx_port_ucrs old_ucr; 1624 unsigned int ucr1; 1625 unsigned long flags = 0; 1626 int locked = 1; 1627 int retval; 1628 1629 retval = clk_enable(sport->clk_per); 1630 if (retval) 1631 return; 1632 retval = clk_enable(sport->clk_ipg); 1633 if (retval) { 1634 clk_disable(sport->clk_per); 1635 return; 1636 } 1637 1638 if (sport->port.sysrq) 1639 locked = 0; 1640 else if (oops_in_progress) 1641 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1642 else 1643 spin_lock_irqsave(&sport->port.lock, flags); 1644 1645 /* 1646 * First, save UCR1/2/3 and then disable interrupts 1647 */ 1648 imx_port_ucrs_save(&sport->port, &old_ucr); 1649 ucr1 = old_ucr.ucr1; 1650 1651 if (is_imx1_uart(sport)) 1652 ucr1 |= IMX1_UCR1_UARTCLKEN; 1653 ucr1 |= UCR1_UARTEN; 1654 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1655 1656 writel(ucr1, sport->port.membase + UCR1); 1657 1658 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); 1659 1660 uart_console_write(&sport->port, s, count, imx_console_putchar); 1661 1662 /* 1663 * Finally, wait for transmitter to become empty 1664 * and restore UCR1/2/3 1665 */ 1666 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); 1667 1668 imx_port_ucrs_restore(&sport->port, &old_ucr); 1669 1670 if (locked) 1671 spin_unlock_irqrestore(&sport->port.lock, flags); 1672 1673 clk_disable(sport->clk_ipg); 1674 clk_disable(sport->clk_per); 1675} 1676 1677/* 1678 * If the port was already initialised (eg, by a boot loader), 1679 * try to determine the current setup. 1680 */ 1681static void __init 1682imx_console_get_options(struct imx_port *sport, int *baud, 1683 int *parity, int *bits) 1684{ 1685 1686 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { 1687 /* ok, the port was enabled */ 1688 unsigned int ucr2, ubir, ubmr, uartclk; 1689 unsigned int baud_raw; 1690 unsigned int ucfr_rfdiv; 1691 1692 ucr2 = readl(sport->port.membase + UCR2); 1693 1694 *parity = 'n'; 1695 if (ucr2 & UCR2_PREN) { 1696 if (ucr2 & UCR2_PROE) 1697 *parity = 'o'; 1698 else 1699 *parity = 'e'; 1700 } 1701 1702 if (ucr2 & UCR2_WS) 1703 *bits = 8; 1704 else 1705 *bits = 7; 1706 1707 ubir = readl(sport->port.membase + UBIR) & 0xffff; 1708 ubmr = readl(sport->port.membase + UBMR) & 0xffff; 1709 1710 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; 1711 if (ucfr_rfdiv == 6) 1712 ucfr_rfdiv = 7; 1713 else 1714 ucfr_rfdiv = 6 - ucfr_rfdiv; 1715 1716 uartclk = clk_get_rate(sport->clk_per); 1717 uartclk /= ucfr_rfdiv; 1718 1719 { /* 1720 * The next code provides exact computation of 1721 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 1722 * without need of float support or long long division, 1723 * which would be required to prevent 32bit arithmetic overflow 1724 */ 1725 unsigned int mul = ubir + 1; 1726 unsigned int div = 16 * (ubmr + 1); 1727 unsigned int rem = uartclk % div; 1728 1729 baud_raw = (uartclk / div) * mul; 1730 baud_raw += (rem * mul + div / 2) / div; 1731 *baud = (baud_raw + 50) / 100 * 100; 1732 } 1733 1734 if (*baud != baud_raw) 1735 pr_info("Console IMX rounded baud rate from %d to %d\n", 1736 baud_raw, *baud); 1737 } 1738} 1739 1740static int __init 1741imx_console_setup(struct console *co, char *options) 1742{ 1743 struct imx_port *sport; 1744 int baud = 9600; 1745 int bits = 8; 1746 int parity = 'n'; 1747 int flow = 'n'; 1748 int retval; 1749 1750 /* 1751 * Check whether an invalid uart number has been specified, and 1752 * if so, search for the first available port that does have 1753 * console support. 1754 */ 1755 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) 1756 co->index = 0; 1757 sport = imx_ports[co->index]; 1758 if (sport == NULL) 1759 return -ENODEV; 1760 1761 /* For setting the registers, we only need to enable the ipg clock. */ 1762 retval = clk_prepare_enable(sport->clk_ipg); 1763 if (retval) 1764 goto error_console; 1765 1766 if (options) 1767 uart_parse_options(options, &baud, &parity, &bits, &flow); 1768 else 1769 imx_console_get_options(sport, &baud, &parity, &bits); 1770 1771 imx_setup_ufcr(sport, 0); 1772 1773 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 1774 1775 clk_disable(sport->clk_ipg); 1776 if (retval) { 1777 clk_unprepare(sport->clk_ipg); 1778 goto error_console; 1779 } 1780 1781 retval = clk_prepare(sport->clk_per); 1782 if (retval) 1783 clk_disable_unprepare(sport->clk_ipg); 1784 1785error_console: 1786 return retval; 1787} 1788 1789static struct uart_driver imx_reg; 1790static struct console imx_console = { 1791 .name = DEV_NAME, 1792 .write = imx_console_write, 1793 .device = uart_console_device, 1794 .setup = imx_console_setup, 1795 .flags = CON_PRINTBUFFER, 1796 .index = -1, 1797 .data = &imx_reg, 1798}; 1799 1800#define IMX_CONSOLE &imx_console 1801#else 1802#define IMX_CONSOLE NULL 1803#endif 1804 1805static struct uart_driver imx_reg = { 1806 .owner = THIS_MODULE, 1807 .driver_name = DRIVER_NAME, 1808 .dev_name = DEV_NAME, 1809 .major = SERIAL_IMX_MAJOR, 1810 .minor = MINOR_START, 1811 .nr = ARRAY_SIZE(imx_ports), 1812 .cons = IMX_CONSOLE, 1813}; 1814 1815static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) 1816{ 1817 struct imx_port *sport = platform_get_drvdata(dev); 1818 unsigned int val; 1819 1820 /* enable wakeup from i.MX UART */ 1821 val = readl(sport->port.membase + UCR3); 1822 val |= UCR3_AWAKEN; 1823 writel(val, sport->port.membase + UCR3); 1824 1825 uart_suspend_port(&imx_reg, &sport->port); 1826 1827 return 0; 1828} 1829 1830static int serial_imx_resume(struct platform_device *dev) 1831{ 1832 struct imx_port *sport = platform_get_drvdata(dev); 1833 unsigned int val; 1834 1835 /* disable wakeup from i.MX UART */ 1836 val = readl(sport->port.membase + UCR3); 1837 val &= ~UCR3_AWAKEN; 1838 writel(val, sport->port.membase + UCR3); 1839 1840 uart_resume_port(&imx_reg, &sport->port); 1841 1842 return 0; 1843} 1844 1845#ifdef CONFIG_OF 1846/* 1847 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 1848 * could successfully get all information from dt or a negative errno. 1849 */ 1850static int serial_imx_probe_dt(struct imx_port *sport, 1851 struct platform_device *pdev) 1852{ 1853 struct device_node *np = pdev->dev.of_node; 1854 const struct of_device_id *of_id = 1855 of_match_device(imx_uart_dt_ids, &pdev->dev); 1856 int ret; 1857 1858 if (!np) 1859 /* no device tree device */ 1860 return 1; 1861 1862 ret = of_alias_get_id(np, "serial"); 1863 if (ret < 0) { 1864 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1865 return ret; 1866 } 1867 sport->port.line = ret; 1868 1869 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1870 sport->have_rtscts = 1; 1871 1872 if (of_get_property(np, "fsl,dte-mode", NULL)) 1873 sport->dte_mode = 1; 1874 1875 sport->devdata = of_id->data; 1876 1877 return 0; 1878} 1879#else 1880static inline int serial_imx_probe_dt(struct imx_port *sport, 1881 struct platform_device *pdev) 1882{ 1883 return 1; 1884} 1885#endif 1886 1887static void serial_imx_probe_pdata(struct imx_port *sport, 1888 struct platform_device *pdev) 1889{ 1890 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 1891 1892 sport->port.line = pdev->id; 1893 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 1894 1895 if (!pdata) 1896 return; 1897 1898 if (pdata->flags & IMXUART_HAVE_RTSCTS) 1899 sport->have_rtscts = 1; 1900} 1901 1902static int serial_imx_probe(struct platform_device *pdev) 1903{ 1904 struct imx_port *sport; 1905 void __iomem *base; 1906 int ret = 0; 1907 struct resource *res; 1908 int txirq, rxirq, rtsirq; 1909 1910 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1911 if (!sport) 1912 return -ENOMEM; 1913 1914 ret = serial_imx_probe_dt(sport, pdev); 1915 if (ret > 0) 1916 serial_imx_probe_pdata(sport, pdev); 1917 else if (ret < 0) 1918 return ret; 1919 1920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1921 base = devm_ioremap_resource(&pdev->dev, res); 1922 if (IS_ERR(base)) 1923 return PTR_ERR(base); 1924 1925 rxirq = platform_get_irq(pdev, 0); 1926 txirq = platform_get_irq(pdev, 1); 1927 rtsirq = platform_get_irq(pdev, 2); 1928 1929 sport->port.dev = &pdev->dev; 1930 sport->port.mapbase = res->start; 1931 sport->port.membase = base; 1932 sport->port.type = PORT_IMX, 1933 sport->port.iotype = UPIO_MEM; 1934 sport->port.irq = rxirq; 1935 sport->port.fifosize = 32; 1936 sport->port.ops = &imx_pops; 1937 sport->port.rs485_config = imx_rs485_config; 1938 sport->port.rs485.flags = 1939 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; 1940 sport->port.flags = UPF_BOOT_AUTOCONF; 1941 init_timer(&sport->timer); 1942 sport->timer.function = imx_timeout; 1943 sport->timer.data = (unsigned long)sport; 1944 1945 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1946 if (IS_ERR(sport->clk_ipg)) { 1947 ret = PTR_ERR(sport->clk_ipg); 1948 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 1949 return ret; 1950 } 1951 1952 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 1953 if (IS_ERR(sport->clk_per)) { 1954 ret = PTR_ERR(sport->clk_per); 1955 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 1956 return ret; 1957 } 1958 1959 sport->port.uartclk = clk_get_rate(sport->clk_per); 1960 1961 /* 1962 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 1963 * chips only have one interrupt. 1964 */ 1965 if (txirq > 0) { 1966 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0, 1967 dev_name(&pdev->dev), sport); 1968 if (ret) 1969 return ret; 1970 1971 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0, 1972 dev_name(&pdev->dev), sport); 1973 if (ret) 1974 return ret; 1975 } else { 1976 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0, 1977 dev_name(&pdev->dev), sport); 1978 if (ret) 1979 return ret; 1980 } 1981 1982 imx_ports[sport->port.line] = sport; 1983 1984 platform_set_drvdata(pdev, sport); 1985 1986 return uart_add_one_port(&imx_reg, &sport->port); 1987} 1988 1989static int serial_imx_remove(struct platform_device *pdev) 1990{ 1991 struct imx_port *sport = platform_get_drvdata(pdev); 1992 1993 return uart_remove_one_port(&imx_reg, &sport->port); 1994} 1995 1996static struct platform_driver serial_imx_driver = { 1997 .probe = serial_imx_probe, 1998 .remove = serial_imx_remove, 1999 2000 .suspend = serial_imx_suspend, 2001 .resume = serial_imx_resume, 2002 .id_table = imx_uart_devtype, 2003 .driver = { 2004 .name = "imx-uart", 2005 .of_match_table = imx_uart_dt_ids, 2006 }, 2007}; 2008 2009static int __init imx_serial_init(void) 2010{ 2011 int ret = uart_register_driver(&imx_reg); 2012 2013 if (ret) 2014 return ret; 2015 2016 ret = platform_driver_register(&serial_imx_driver); 2017 if (ret != 0) 2018 uart_unregister_driver(&imx_reg); 2019 2020 return ret; 2021} 2022 2023static void __exit imx_serial_exit(void) 2024{ 2025 platform_driver_unregister(&serial_imx_driver); 2026 uart_unregister_driver(&imx_reg); 2027} 2028 2029module_init(imx_serial_init); 2030module_exit(imx_serial_exit); 2031 2032MODULE_AUTHOR("Sascha Hauer"); 2033MODULE_DESCRIPTION("IMX generic serial port driver"); 2034MODULE_LICENSE("GPL"); 2035MODULE_ALIAS("platform:imx-uart"); 2036