| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| H A D | evergreen.c | 1301 * Wait for vblank on the requested crtc (evergreen+).
1338 * Does the actual pageflip (evergreen+).
1566 * (voltage, etc.) (evergreen+).
1613 * Prepare for a power state change (evergreen+).
1638 * Clean up after a power state change (evergreen+).
1664 * Checks if a digital monitor is connected (evergreen+).
1709 * Set the polarity of the hpd pin (evergreen+).
1776 * Setup the hpd pins used by the card (evergreen+).
1832 * Tear down the hpd pins used by the card (evergreen+).
2368 * (evergreen+).
2402 * (evergreen+).
3052 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); evergreen_cp_start()
3198 rdev->config.evergreen.num_ses = 2; evergreen_gpu_init()
3199 rdev->config.evergreen.max_pipes = 4; evergreen_gpu_init()
3200 rdev->config.evergreen.max_tile_pipes = 8; evergreen_gpu_init()
3201 rdev->config.evergreen.max_simds = 10; evergreen_gpu_init()
3202 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3203 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3204 rdev->config.evergreen.max_threads = 248; evergreen_gpu_init()
3205 rdev->config.evergreen.max_gs_threads = 32; evergreen_gpu_init()
3206 rdev->config.evergreen.max_stack_entries = 512; evergreen_gpu_init()
3207 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3208 rdev->config.evergreen.sx_max_export_size = 256; evergreen_gpu_init()
3209 rdev->config.evergreen.sx_max_export_pos_size = 64; evergreen_gpu_init()
3210 rdev->config.evergreen.sx_max_export_smx_size = 192; evergreen_gpu_init()
3211 rdev->config.evergreen.max_hw_contexts = 8; evergreen_gpu_init()
3212 rdev->config.evergreen.sq_num_cf_insts = 2; evergreen_gpu_init()
3214 rdev->config.evergreen.sc_prim_fifo_size = 0x100; evergreen_gpu_init()
3215 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3216 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3220 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3221 rdev->config.evergreen.max_pipes = 4; evergreen_gpu_init()
3222 rdev->config.evergreen.max_tile_pipes = 4; evergreen_gpu_init()
3223 rdev->config.evergreen.max_simds = 10; evergreen_gpu_init()
3224 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3225 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3226 rdev->config.evergreen.max_threads = 248; evergreen_gpu_init()
3227 rdev->config.evergreen.max_gs_threads = 32; evergreen_gpu_init()
3228 rdev->config.evergreen.max_stack_entries = 512; evergreen_gpu_init()
3229 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3230 rdev->config.evergreen.sx_max_export_size = 256; evergreen_gpu_init()
3231 rdev->config.evergreen.sx_max_export_pos_size = 64; evergreen_gpu_init()
3232 rdev->config.evergreen.sx_max_export_smx_size = 192; evergreen_gpu_init()
3233 rdev->config.evergreen.max_hw_contexts = 8; evergreen_gpu_init()
3234 rdev->config.evergreen.sq_num_cf_insts = 2; evergreen_gpu_init()
3236 rdev->config.evergreen.sc_prim_fifo_size = 0x100; evergreen_gpu_init()
3237 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3238 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3242 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3243 rdev->config.evergreen.max_pipes = 4; evergreen_gpu_init()
3244 rdev->config.evergreen.max_tile_pipes = 4; evergreen_gpu_init()
3245 rdev->config.evergreen.max_simds = 5; evergreen_gpu_init()
3246 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3247 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3248 rdev->config.evergreen.max_threads = 248; evergreen_gpu_init()
3249 rdev->config.evergreen.max_gs_threads = 32; evergreen_gpu_init()
3250 rdev->config.evergreen.max_stack_entries = 256; evergreen_gpu_init()
3251 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3252 rdev->config.evergreen.sx_max_export_size = 256; evergreen_gpu_init()
3253 rdev->config.evergreen.sx_max_export_pos_size = 64; evergreen_gpu_init()
3254 rdev->config.evergreen.sx_max_export_smx_size = 192; evergreen_gpu_init()
3255 rdev->config.evergreen.max_hw_contexts = 8; evergreen_gpu_init()
3256 rdev->config.evergreen.sq_num_cf_insts = 2; evergreen_gpu_init()
3258 rdev->config.evergreen.sc_prim_fifo_size = 0x100; evergreen_gpu_init()
3259 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3260 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3265 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3266 rdev->config.evergreen.max_pipes = 2; evergreen_gpu_init()
3267 rdev->config.evergreen.max_tile_pipes = 2; evergreen_gpu_init()
3268 rdev->config.evergreen.max_simds = 2; evergreen_gpu_init()
3269 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3270 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3271 rdev->config.evergreen.max_threads = 192; evergreen_gpu_init()
3272 rdev->config.evergreen.max_gs_threads = 16; evergreen_gpu_init()
3273 rdev->config.evergreen.max_stack_entries = 256; evergreen_gpu_init()
3274 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3275 rdev->config.evergreen.sx_max_export_size = 128; evergreen_gpu_init()
3276 rdev->config.evergreen.sx_max_export_pos_size = 32; evergreen_gpu_init()
3277 rdev->config.evergreen.sx_max_export_smx_size = 96; evergreen_gpu_init()
3278 rdev->config.evergreen.max_hw_contexts = 4; evergreen_gpu_init()
3279 rdev->config.evergreen.sq_num_cf_insts = 1; evergreen_gpu_init()
3281 rdev->config.evergreen.sc_prim_fifo_size = 0x40; evergreen_gpu_init()
3282 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3283 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3287 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3288 rdev->config.evergreen.max_pipes = 2; evergreen_gpu_init()
3289 rdev->config.evergreen.max_tile_pipes = 2; evergreen_gpu_init()
3290 rdev->config.evergreen.max_simds = 2; evergreen_gpu_init()
3291 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3292 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3293 rdev->config.evergreen.max_threads = 192; evergreen_gpu_init()
3294 rdev->config.evergreen.max_gs_threads = 16; evergreen_gpu_init()
3295 rdev->config.evergreen.max_stack_entries = 256; evergreen_gpu_init()
3296 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3297 rdev->config.evergreen.sx_max_export_size = 128; evergreen_gpu_init()
3298 rdev->config.evergreen.sx_max_export_pos_size = 32; evergreen_gpu_init()
3299 rdev->config.evergreen.sx_max_export_smx_size = 96; evergreen_gpu_init()
3300 rdev->config.evergreen.max_hw_contexts = 4; evergreen_gpu_init()
3301 rdev->config.evergreen.sq_num_cf_insts = 1; evergreen_gpu_init()
3303 rdev->config.evergreen.sc_prim_fifo_size = 0x40; evergreen_gpu_init()
3304 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3305 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3309 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3310 rdev->config.evergreen.max_pipes = 4; evergreen_gpu_init()
3311 rdev->config.evergreen.max_tile_pipes = 4; evergreen_gpu_init()
3313 rdev->config.evergreen.max_simds = 3; evergreen_gpu_init()
3316 rdev->config.evergreen.max_simds = 4; evergreen_gpu_init()
3318 rdev->config.evergreen.max_simds = 5; evergreen_gpu_init()
3319 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3320 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3321 rdev->config.evergreen.max_threads = 248; evergreen_gpu_init()
3322 rdev->config.evergreen.max_gs_threads = 32; evergreen_gpu_init()
3323 rdev->config.evergreen.max_stack_entries = 256; evergreen_gpu_init()
3324 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3325 rdev->config.evergreen.sx_max_export_size = 256; evergreen_gpu_init()
3326 rdev->config.evergreen.sx_max_export_pos_size = 64; evergreen_gpu_init()
3327 rdev->config.evergreen.sx_max_export_smx_size = 192; evergreen_gpu_init()
3328 rdev->config.evergreen.max_hw_contexts = 8; evergreen_gpu_init()
3329 rdev->config.evergreen.sq_num_cf_insts = 2; evergreen_gpu_init()
3331 rdev->config.evergreen.sc_prim_fifo_size = 0x40; evergreen_gpu_init()
3332 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3333 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3337 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3338 rdev->config.evergreen.max_pipes = 4; evergreen_gpu_init()
3339 rdev->config.evergreen.max_tile_pipes = 4; evergreen_gpu_init()
3340 rdev->config.evergreen.max_simds = 2; evergreen_gpu_init()
3341 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3342 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3343 rdev->config.evergreen.max_threads = 248; evergreen_gpu_init()
3344 rdev->config.evergreen.max_gs_threads = 32; evergreen_gpu_init()
3345 rdev->config.evergreen.max_stack_entries = 512; evergreen_gpu_init()
3346 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3347 rdev->config.evergreen.sx_max_export_size = 256; evergreen_gpu_init()
3348 rdev->config.evergreen.sx_max_export_pos_size = 64; evergreen_gpu_init()
3349 rdev->config.evergreen.sx_max_export_smx_size = 192; evergreen_gpu_init()
3350 rdev->config.evergreen.max_hw_contexts = 4; evergreen_gpu_init()
3351 rdev->config.evergreen.sq_num_cf_insts = 2; evergreen_gpu_init()
3353 rdev->config.evergreen.sc_prim_fifo_size = 0x40; evergreen_gpu_init()
3354 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3355 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3359 rdev->config.evergreen.num_ses = 2; evergreen_gpu_init()
3360 rdev->config.evergreen.max_pipes = 4; evergreen_gpu_init()
3361 rdev->config.evergreen.max_tile_pipes = 8; evergreen_gpu_init()
3362 rdev->config.evergreen.max_simds = 7; evergreen_gpu_init()
3363 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3364 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3365 rdev->config.evergreen.max_threads = 248; evergreen_gpu_init()
3366 rdev->config.evergreen.max_gs_threads = 32; evergreen_gpu_init()
3367 rdev->config.evergreen.max_stack_entries = 512; evergreen_gpu_init()
3368 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3369 rdev->config.evergreen.sx_max_export_size = 256; evergreen_gpu_init()
3370 rdev->config.evergreen.sx_max_export_pos_size = 64; evergreen_gpu_init()
3371 rdev->config.evergreen.sx_max_export_smx_size = 192; evergreen_gpu_init()
3372 rdev->config.evergreen.max_hw_contexts = 8; evergreen_gpu_init()
3373 rdev->config.evergreen.sq_num_cf_insts = 2; evergreen_gpu_init()
3375 rdev->config.evergreen.sc_prim_fifo_size = 0x100; evergreen_gpu_init()
3376 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3377 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3381 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3382 rdev->config.evergreen.max_pipes = 4; evergreen_gpu_init()
3383 rdev->config.evergreen.max_tile_pipes = 4; evergreen_gpu_init()
3384 rdev->config.evergreen.max_simds = 6; evergreen_gpu_init()
3385 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3386 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3387 rdev->config.evergreen.max_threads = 248; evergreen_gpu_init()
3388 rdev->config.evergreen.max_gs_threads = 32; evergreen_gpu_init()
3389 rdev->config.evergreen.max_stack_entries = 256; evergreen_gpu_init()
3390 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3391 rdev->config.evergreen.sx_max_export_size = 256; evergreen_gpu_init()
3392 rdev->config.evergreen.sx_max_export_pos_size = 64; evergreen_gpu_init()
3393 rdev->config.evergreen.sx_max_export_smx_size = 192; evergreen_gpu_init()
3394 rdev->config.evergreen.max_hw_contexts = 8; evergreen_gpu_init()
3395 rdev->config.evergreen.sq_num_cf_insts = 2; evergreen_gpu_init()
3397 rdev->config.evergreen.sc_prim_fifo_size = 0x100; evergreen_gpu_init()
3398 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3399 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3403 rdev->config.evergreen.num_ses = 1; evergreen_gpu_init()
3404 rdev->config.evergreen.max_pipes = 2; evergreen_gpu_init()
3405 rdev->config.evergreen.max_tile_pipes = 2; evergreen_gpu_init()
3406 rdev->config.evergreen.max_simds = 2; evergreen_gpu_init()
3407 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; evergreen_gpu_init()
3408 rdev->config.evergreen.max_gprs = 256; evergreen_gpu_init()
3409 rdev->config.evergreen.max_threads = 192; evergreen_gpu_init()
3410 rdev->config.evergreen.max_gs_threads = 16; evergreen_gpu_init()
3411 rdev->config.evergreen.max_stack_entries = 256; evergreen_gpu_init()
3412 rdev->config.evergreen.sx_num_of_sets = 4; evergreen_gpu_init()
3413 rdev->config.evergreen.sx_max_export_size = 128; evergreen_gpu_init()
3414 rdev->config.evergreen.sx_max_export_pos_size = 32; evergreen_gpu_init()
3415 rdev->config.evergreen.sx_max_export_smx_size = 96; evergreen_gpu_init()
3416 rdev->config.evergreen.max_hw_contexts = 4; evergreen_gpu_init()
3417 rdev->config.evergreen.sq_num_cf_insts = 1; evergreen_gpu_init()
3419 rdev->config.evergreen.sc_prim_fifo_size = 0x40; evergreen_gpu_init()
3420 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; evergreen_gpu_init()
3421 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; evergreen_gpu_init()
3456 rdev->config.evergreen.tile_config = 0; evergreen_gpu_init()
3457 switch (rdev->config.evergreen.max_tile_pipes) { evergreen_gpu_init()
3460 rdev->config.evergreen.tile_config |= (0 << 0); evergreen_gpu_init()
3463 rdev->config.evergreen.tile_config |= (1 << 0); evergreen_gpu_init()
3466 rdev->config.evergreen.tile_config |= (2 << 0); evergreen_gpu_init()
3469 rdev->config.evergreen.tile_config |= (3 << 0); evergreen_gpu_init()
3474 rdev->config.evergreen.tile_config |= 1 << 4; evergreen_gpu_init()
3478 rdev->config.evergreen.tile_config |= 0 << 4; evergreen_gpu_init()
3481 rdev->config.evergreen.tile_config |= 1 << 4; evergreen_gpu_init()
3485 rdev->config.evergreen.tile_config |= 2 << 4; evergreen_gpu_init()
3489 rdev->config.evergreen.tile_config |= 0 << 8; evergreen_gpu_init()
3490 rdev->config.evergreen.tile_config |= evergreen_gpu_init()
3503 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { evergreen_gpu_init()
3516 for (i = 0; i < rdev->config.evergreen.max_backends; i++) evergreen_gpu_init()
3520 for (i = 0; i < rdev->config.evergreen.max_backends; i++) evergreen_gpu_init()
3524 for (i = 0; i < rdev->config.evergreen.num_ses; i++) { evergreen_gpu_init()
3530 simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds; evergreen_gpu_init()
3534 rdev->config.evergreen.active_simds = hweight32(~tmp); evergreen_gpu_init()
3547 if ((rdev->config.evergreen.max_backends == 1) && evergreen_gpu_init()
3558 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, evergreen_gpu_init()
3586 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); evergreen_gpu_init()
3592 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | evergreen_gpu_init()
3593 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | evergreen_gpu_init()
3594 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); evergreen_gpu_init()
3596 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | evergreen_gpu_init()
3597 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | evergreen_gpu_init()
3598 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); evergreen_gpu_init()
3605 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | evergreen_gpu_init()
3637 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); evergreen_gpu_init()
3638 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); evergreen_gpu_init()
3640 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); evergreen_gpu_init()
3641 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); evergreen_gpu_init()
3642 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); evergreen_gpu_init()
3643 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); evergreen_gpu_init()
3658 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); evergreen_gpu_init()
3659 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); evergreen_gpu_init()
3660 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); evergreen_gpu_init()
3661 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); evergreen_gpu_init()
3662 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); evergreen_gpu_init()
3664 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); evergreen_gpu_init()
3665 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); evergreen_gpu_init()
3666 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); evergreen_gpu_init()
3667 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); evergreen_gpu_init()
3668 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); evergreen_gpu_init()
3669 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); evergreen_gpu_init()
3798 /* size in MB on evergreen/cayman/tn */ evergreen_mc_init()
4786 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); evergreen_irq_ack()
4787 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); evergreen_irq_ack()
4788 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); evergreen_irq_ack()
4789 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); evergreen_irq_ack()
4790 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); evergreen_irq_ack()
4791 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); evergreen_irq_ack()
4792 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); evergreen_irq_ack()
4793 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); evergreen_irq_ack()
4795 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); evergreen_irq_ack()
4796 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); evergreen_irq_ack()
4799 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); evergreen_irq_ack()
4800 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); evergreen_irq_ack()
4803 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); evergreen_irq_ack()
4804 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); evergreen_irq_ack()
4805 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); evergreen_irq_ack()
4806 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); evergreen_irq_ack()
4807 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); evergreen_irq_ack()
4808 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); evergreen_irq_ack()
4810 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) evergreen_irq_ack()
4812 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) evergreen_irq_ack()
4814 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) evergreen_irq_ack()
4816 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) evergreen_irq_ack()
4818 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) evergreen_irq_ack()
4820 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) evergreen_irq_ack()
4824 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) evergreen_irq_ack()
4826 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) evergreen_irq_ack()
4828 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) evergreen_irq_ack()
4830 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) evergreen_irq_ack()
4832 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) evergreen_irq_ack()
4834 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) evergreen_irq_ack()
4839 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) evergreen_irq_ack()
4841 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) evergreen_irq_ack()
4843 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) evergreen_irq_ack()
4845 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) evergreen_irq_ack()
4847 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) evergreen_irq_ack()
4849 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) evergreen_irq_ack()
4853 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { evergreen_irq_ack()
4858 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { evergreen_irq_ack()
4863 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { evergreen_irq_ack()
4868 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { evergreen_irq_ack()
4873 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { evergreen_irq_ack()
4878 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { evergreen_irq_ack()
4884 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { evergreen_irq_ack()
4889 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { evergreen_irq_ack()
4894 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { evergreen_irq_ack()
4899 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { evergreen_irq_ack()
4904 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { evergreen_irq_ack()
4909 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { evergreen_irq_ack()
4915 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { evergreen_irq_ack()
4920 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { evergreen_irq_ack()
4925 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { evergreen_irq_ack()
4930 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { evergreen_irq_ack()
4935 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { evergreen_irq_ack()
4940 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { evergreen_irq_ack()
5028 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) evergreen_irq_process()
5038 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; evergreen_irq_process()
5043 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) evergreen_irq_process()
5046 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; evergreen_irq_process()
5058 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) evergreen_irq_process()
5068 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; evergreen_irq_process()
5073 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) evergreen_irq_process()
5076 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; evergreen_irq_process()
5088 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) evergreen_irq_process()
5098 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; evergreen_irq_process()
5103 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) evergreen_irq_process()
5106 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; evergreen_irq_process()
5118 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) evergreen_irq_process()
5128 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; evergreen_irq_process()
5133 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) evergreen_irq_process()
5136 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; evergreen_irq_process()
5148 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) evergreen_irq_process()
5158 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; evergreen_irq_process()
5163 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) evergreen_irq_process()
5166 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; evergreen_irq_process()
5178 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) evergreen_irq_process()
5188 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; evergreen_irq_process()
5193 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) evergreen_irq_process()
5196 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; evergreen_irq_process()
5218 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) evergreen_irq_process()
5221 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; evergreen_irq_process()
5226 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) evergreen_irq_process()
5229 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; evergreen_irq_process()
5234 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) evergreen_irq_process()
5237 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; evergreen_irq_process()
5242 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) evergreen_irq_process()
5245 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; evergreen_irq_process()
5250 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) evergreen_irq_process()
5253 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; evergreen_irq_process()
5258 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) evergreen_irq_process()
5261 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; evergreen_irq_process()
5266 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) evergreen_irq_process()
5269 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; evergreen_irq_process()
5274 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) evergreen_irq_process()
5277 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; evergreen_irq_process()
5282 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) evergreen_irq_process()
5285 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; evergreen_irq_process()
5290 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) evergreen_irq_process()
5293 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; evergreen_irq_process()
5298 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) evergreen_irq_process()
5301 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; evergreen_irq_process()
5306 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) evergreen_irq_process()
5309 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; evergreen_irq_process()
5321 if (!(rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG)) evergreen_irq_process()
5324 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; evergreen_irq_process()
5329 if (!(rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG)) evergreen_irq_process()
5332 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; evergreen_irq_process()
5337 if (!(rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG)) evergreen_irq_process()
5340 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; evergreen_irq_process()
5345 if (!(rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG)) evergreen_irq_process()
5348 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; evergreen_irq_process()
5353 if (!(rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG)) evergreen_irq_process()
5356 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; evergreen_irq_process()
5361 if (!(rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG)) evergreen_irq_process()
5364 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; evergreen_irq_process()
5633 DRM_ERROR("evergreen startup failed on resume\n"); evergreen_resume()
5674 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); evergreen_init()
6022 /* evergreen parts only */ evergreen_program_aspm()
|
| H A D | evergreen_dma.c | 39 * an interrupt if needed (evergreen-SI).
65 * Schedule an IB in the DMA ring (evergreen).
103 * Copy GPU paging using the DMA engine (evergreen-cayman).
|
| H A D | Makefile | 37 $(obj)/evergreen_reg_safe.h: $(src)/reg_srcs/evergreen $(obj)/mkregtable
76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o \
|
| H A D | si.c | 6249 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); si_irq_ack()
6250 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); si_irq_ack()
6251 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); si_irq_ack()
6252 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); si_irq_ack()
6253 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); si_irq_ack()
6254 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); si_irq_ack()
6255 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); si_irq_ack()
6256 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); si_irq_ack()
6258 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); si_irq_ack()
6259 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); si_irq_ack()
6262 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); si_irq_ack()
6263 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); si_irq_ack()
6266 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) si_irq_ack()
6268 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) si_irq_ack()
6270 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) si_irq_ack()
6272 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) si_irq_ack()
6274 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) si_irq_ack()
6276 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) si_irq_ack()
6280 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) si_irq_ack()
6282 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) si_irq_ack()
6284 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) si_irq_ack()
6286 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) si_irq_ack()
6288 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) si_irq_ack()
6290 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) si_irq_ack()
6295 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) si_irq_ack()
6297 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) si_irq_ack()
6299 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) si_irq_ack()
6301 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) si_irq_ack()
6303 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) si_irq_ack()
6305 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) si_irq_ack()
6309 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { si_irq_ack()
6314 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { si_irq_ack()
6319 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { si_irq_ack()
6324 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { si_irq_ack()
6329 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { si_irq_ack()
6334 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { si_irq_ack()
6340 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { si_irq_ack()
6345 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { si_irq_ack()
6350 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { si_irq_ack()
6355 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { si_irq_ack()
6360 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { si_irq_ack()
6365 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { si_irq_ack()
6469 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) si_irq_process()
6479 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; si_irq_process()
6484 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) si_irq_process()
6487 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; si_irq_process()
6499 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) si_irq_process()
6509 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; si_irq_process()
6514 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) si_irq_process()
6517 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; si_irq_process()
6529 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) si_irq_process()
6539 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; si_irq_process()
6544 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) si_irq_process()
6547 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; si_irq_process()
6559 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) si_irq_process()
6569 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; si_irq_process()
6574 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) si_irq_process()
6577 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; si_irq_process()
6589 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) si_irq_process()
6599 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; si_irq_process()
6604 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) si_irq_process()
6607 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; si_irq_process()
6619 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) si_irq_process()
6629 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; si_irq_process()
6634 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) si_irq_process()
6637 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; si_irq_process()
6659 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) si_irq_process()
6662 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; si_irq_process()
6668 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) si_irq_process()
6671 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; si_irq_process()
6677 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) si_irq_process()
6680 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; si_irq_process()
6686 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) si_irq_process()
6689 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; si_irq_process()
6695 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) si_irq_process()
6698 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; si_irq_process()
6704 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) si_irq_process()
6707 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; si_irq_process()
6713 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) si_irq_process()
6716 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; si_irq_process()
6722 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) si_irq_process()
6725 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; si_irq_process()
6731 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) si_irq_process()
6734 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; si_irq_process()
6740 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) si_irq_process()
6743 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; si_irq_process()
6749 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) si_irq_process()
6752 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; si_irq_process()
6758 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) si_irq_process()
6761 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; si_irq_process()
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| H A D | radeon_kms.c | 238 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ radeon_info_ioctl()
285 *value = rdev->config.evergreen.tile_config; radeon_info_ioctl()
342 *value = rdev->config.evergreen.max_backends; radeon_info_ioctl()
359 *value = rdev->config.evergreen.max_tile_pipes; radeon_info_ioctl()
379 *value = rdev->config.evergreen.backend_map; radeon_info_ioctl()
408 *value = rdev->config.evergreen.max_pipes; radeon_info_ioctl()
434 *value = rdev->config.evergreen.num_ses; radeon_info_ioctl()
542 *value = rdev->config.evergreen.active_simds; radeon_info_ioctl()
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| H A D | r600_dma.c | 97 * Stop the async dma engine (r6xx-evergreen).
117 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
191 * Stop the async dma engine and free the ring (r6xx-evergreen).
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| H A D | cayman_blit_shaders.c | 32 * evergreen cards need to use the 3D engine to blit data which requires
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| H A D | evergreen_blit_shaders.c | 32 * evergreen cards need to use the 3D engine to blit data which requires
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| H A D | radeon_drv.c | 53 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
62 * 2.14.0 - add evergreen tiling informations
64 * 2.16.0 - fix evergreen 2D tiled surface calculation
91 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
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| H A D | rv770_dpm.c | 2135 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
2198 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); rv7xx_parse_pplib_clock_info()
2199 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; rv7xx_parse_pplib_clock_info()
2200 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); rv7xx_parse_pplib_clock_info()
2201 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; rv7xx_parse_pplib_clock_info()
2203 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC); rv7xx_parse_pplib_clock_info()
2204 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI); rv7xx_parse_pplib_clock_info()
2205 pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags); rv7xx_parse_pplib_clock_info()
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| H A D | evergreen_reg.h | 31 /* evergreen */
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| H A D | radeon_atombios.c | 64 /* some evergreen boards have bad data for this entry */ radeon_lookup_i2c_gpio_quirks()
2038 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
2510 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); radeon_atombios_parse_pplib_clock_info()
2511 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; radeon_atombios_parse_pplib_clock_info()
2512 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); radeon_atombios_parse_pplib_clock_info()
2513 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; radeon_atombios_parse_pplib_clock_info()
2519 le16_to_cpu(clock_info->evergreen.usVDDC); radeon_atombios_parse_pplib_clock_info()
2521 le16_to_cpu(clock_info->evergreen.usVDDCI); radeon_atombios_parse_pplib_clock_info()
2855 /* r6xx, r7xx, evergreen, ni, si */ radeon_atom_get_clock_dividers()
3845 /* r7xx, evergreen */ radeon_atom_get_memory_info()
3923 /* r7xx, evergreen */ radeon_atom_get_mclk_range_table()
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| H A D | ni_dpm.c | 3885 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
3931 pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); ni_parse_pplib_clock_info()
3932 pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16; ni_parse_pplib_clock_info()
3933 pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); ni_parse_pplib_clock_info()
3934 pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; ni_parse_pplib_clock_info()
3936 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC); ni_parse_pplib_clock_info()
3937 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI); ni_parse_pplib_clock_info()
3938 pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags); ni_parse_pplib_clock_info()
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| H A D | radeon.h | 803 struct evergreen_irq_stat_regs evergreen; member in union:radeon_irq_stat_regs
1282 /* evergreen+ vddci */
2201 struct evergreen_asic evergreen; member in union:radeon_asic_config
3095 * evergreen functions used by radeon_encoder.c
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| H A D | evergreend.h | 876 /* evergreen */
2572 /* DMA regs common on r6xx/r7xx/evergreen/ni */
|
| H A D | rs780_dpm.c | 708 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
|
| H A D | cypress_dpm.c | 1426 /* evergreen only */ cypress_populate_smc_acpi_state()
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| H A D | radeon_asic.h | 501 * evergreen
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| H A D | rv6xx_dpm.c | 1786 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
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| H A D | rv770.c | 52 /* RV740 uses evergreen uvd clk programming */ rv770_set_uvd_clocks()
|
| H A D | sumo_dpm.c | 1384 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
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| H A D | trinity_dpm.c | 1605 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
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| H A D | atombios_crtc.c | 1309 tmp = rdev->config.evergreen.tile_config; dce4_crtc_do_set_base()
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| H A D | kv_dpm.c | 2564 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
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| H A D | radeon_drv.h | 113 * 1.34- fix evergreen/cayman GS register
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| H A D | evergreen_cs.c | 2650 tmp = p->rdev->config.evergreen.tile_config; evergreen_cs_parse()
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| H A D | ci_dpm.c | 5405 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
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| H A D | si_dpm.c | 6616 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; member in union:pplib_clock_info
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