| H A D | denali.c | 28 #include "denali.h"
43 #define DENALI_NAND_NAME "denali-nand"
76 * device context (denali) structure.
104 static void clear_interrupts(struct denali_nand_info *denali);
105 static uint32_t wait_for_irq(struct denali_nand_info *denali,
107 static void denali_irq_enable(struct denali_nand_info *denali,
109 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
112 * Certain operations for the denali NAND controller use an indexed mode to
117 static void index_addr(struct denali_nand_info *denali, index_addr() argument
120 iowrite32(address, denali->flash_mem); index_addr()
121 iowrite32(data, denali->flash_mem + 0x10); index_addr()
125 static void index_addr_read_data(struct denali_nand_info *denali, index_addr_read_data() argument
128 iowrite32(address, denali->flash_mem); index_addr_read_data()
129 *pdata = ioread32(denali->flash_mem + 0x10); index_addr_read_data()
136 static void reset_buf(struct denali_nand_info *denali) reset_buf() argument
138 denali->buf.head = denali->buf.tail = 0; reset_buf()
141 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) write_byte_to_buf() argument
143 denali->buf.buf[denali->buf.tail++] = byte; write_byte_to_buf()
147 static void read_status(struct denali_nand_info *denali) read_status() argument
152 reset_buf(denali); read_status()
154 cmd = ioread32(denali->flash_reg + WRITE_PROTECT); read_status()
156 write_byte_to_buf(denali, NAND_STATUS_WP); read_status()
158 write_byte_to_buf(denali, 0); read_status()
162 static void reset_bank(struct denali_nand_info *denali) reset_bank() argument
167 clear_interrupts(denali); reset_bank()
169 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); reset_bank()
171 irq_status = wait_for_irq(denali, irq_mask); reset_bank()
174 dev_err(denali->dev, "reset bank failed.\n"); reset_bank()
178 static uint16_t denali_nand_reset(struct denali_nand_info *denali) denali_nand_reset() argument
182 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", denali_nand_reset()
185 for (i = 0; i < denali->max_banks; i++) denali_nand_reset()
187 denali->flash_reg + INTR_STATUS(i)); denali_nand_reset()
189 for (i = 0; i < denali->max_banks; i++) { denali_nand_reset()
190 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); denali_nand_reset()
191 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & denali_nand_reset()
194 if (ioread32(denali->flash_reg + INTR_STATUS(i)) & denali_nand_reset()
196 dev_dbg(denali->dev, denali_nand_reset()
200 for (i = 0; i < denali->max_banks; i++) denali_nand_reset()
202 denali->flash_reg + INTR_STATUS(i)); denali_nand_reset()
212 static void nand_onfi_timing_set(struct denali_nand_info *denali, nand_onfi_timing_set() argument
234 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", nand_onfi_timing_set()
270 dev_warn(denali->dev, "%s, Line %d: Warning!\n", nand_onfi_timing_set()
292 if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && nand_onfi_timing_set()
293 ioread32(denali->flash_reg + DEVICE_ID) == 0x88) nand_onfi_timing_set()
296 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); nand_onfi_timing_set()
297 iowrite32(re_2_we, denali->flash_reg + RE_2_WE); nand_onfi_timing_set()
298 iowrite32(re_2_re, denali->flash_reg + RE_2_RE); nand_onfi_timing_set()
299 iowrite32(we_2_re, denali->flash_reg + WE_2_RE); nand_onfi_timing_set()
300 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); nand_onfi_timing_set()
301 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); nand_onfi_timing_set()
302 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); nand_onfi_timing_set()
303 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); nand_onfi_timing_set()
307 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) get_onfi_nand_para() argument
315 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & get_onfi_nand_para()
320 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & get_onfi_nand_para()
325 nand_onfi_timing_set(denali, i); get_onfi_nand_para()
331 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ get_onfi_nand_para()
332 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ get_onfi_nand_para()
337 static void get_samsung_nand_para(struct denali_nand_info *denali, get_samsung_nand_para() argument
342 iowrite32(5, denali->flash_reg + ACC_CLKS); get_samsung_nand_para()
343 iowrite32(20, denali->flash_reg + RE_2_WE); get_samsung_nand_para()
344 iowrite32(12, denali->flash_reg + WE_2_RE); get_samsung_nand_para()
345 iowrite32(14, denali->flash_reg + ADDR_2_DATA); get_samsung_nand_para()
346 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); get_samsung_nand_para()
347 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); get_samsung_nand_para()
348 iowrite32(2, denali->flash_reg + CS_SETUP_CNT); get_samsung_nand_para()
352 static void get_toshiba_nand_para(struct denali_nand_info *denali) get_toshiba_nand_para() argument
360 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && get_toshiba_nand_para()
361 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { get_toshiba_nand_para()
362 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); get_toshiba_nand_para()
363 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * get_toshiba_nand_para()
364 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); get_toshiba_nand_para()
366 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); get_toshiba_nand_para()
368 iowrite32(15, denali->flash_reg + ECC_CORRECTION); get_toshiba_nand_para()
370 iowrite32(8, denali->flash_reg + ECC_CORRECTION); get_toshiba_nand_para()
375 static void get_hynix_nand_para(struct denali_nand_info *denali, get_hynix_nand_para() argument
383 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); get_hynix_nand_para()
384 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); get_hynix_nand_para()
385 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); get_hynix_nand_para()
387 ioread32(denali->flash_reg + DEVICES_CONNECTED); get_hynix_nand_para()
389 ioread32(denali->flash_reg + DEVICES_CONNECTED); get_hynix_nand_para()
391 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); get_hynix_nand_para()
393 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); get_hynix_nand_para()
394 iowrite32(0, denali->flash_reg + DEVICE_WIDTH); get_hynix_nand_para()
396 iowrite32(15, denali->flash_reg + ECC_CORRECTION); get_hynix_nand_para()
398 iowrite32(8, denali->flash_reg + ECC_CORRECTION); get_hynix_nand_para()
402 dev_warn(denali->dev, get_hynix_nand_para()
413 static void find_valid_banks(struct denali_nand_info *denali) find_valid_banks() argument
415 uint32_t id[denali->max_banks]; find_valid_banks()
418 denali->total_used_banks = 1; find_valid_banks()
419 for (i = 0; i < denali->max_banks; i++) { find_valid_banks()
420 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); find_valid_banks()
421 index_addr(denali, MODE_11 | (i << 24) | 1, 0); find_valid_banks()
422 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); find_valid_banks()
424 dev_dbg(denali->dev, find_valid_banks()
432 denali->total_used_banks++; find_valid_banks()
438 if (denali->platform == INTEL_CE4100) { find_valid_banks()
444 if (denali->total_used_banks != 1) { find_valid_banks()
445 dev_err(denali->dev, find_valid_banks()
450 dev_dbg(denali->dev, find_valid_banks()
451 "denali->total_used_banks: %d\n", denali->total_used_banks); find_valid_banks()
458 static void detect_max_banks(struct denali_nand_info *denali) detect_max_banks() argument
460 uint32_t features = ioread32(denali->flash_reg + FEATURES); detect_max_banks()
462 denali->max_banks = 2 << (features & FEATURES__N_BANKS); detect_max_banks()
465 static void detect_partition_feature(struct denali_nand_info *denali) detect_partition_feature() argument
468 * For MRST platform, denali->fwblks represent the detect_partition_feature()
474 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { detect_partition_feature()
475 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & detect_partition_feature()
477 denali->fwblks = detect_partition_feature()
478 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) & detect_partition_feature()
480 denali->blksperchip) detect_partition_feature()
482 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & detect_partition_feature()
485 denali->fwblks = SPECTRA_START_BLOCK; detect_partition_feature()
488 denali->fwblks = SPECTRA_START_BLOCK; detect_partition_feature()
492 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) denali_nand_timing_set() argument
499 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", denali_nand_timing_set()
507 addr = MODE_11 | BANK(denali->flash_bank); denali_nand_timing_set()
508 index_addr(denali, addr | 0, 0x90); denali_nand_timing_set()
509 index_addr(denali, addr | 1, 0); denali_nand_timing_set()
511 index_addr_read_data(denali, addr | 2, &id_bytes[i]); denali_nand_timing_set()
515 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & denali_nand_timing_set()
517 if (FAIL == get_onfi_nand_para(denali)) denali_nand_timing_set()
520 get_samsung_nand_para(denali, device_id); denali_nand_timing_set()
522 get_toshiba_nand_para(denali); denali_nand_timing_set()
524 get_hynix_nand_para(denali, device_id); denali_nand_timing_set()
527 dev_info(denali->dev, denali_nand_timing_set()
532 ioread32(denali->flash_reg + ACC_CLKS), denali_nand_timing_set()
533 ioread32(denali->flash_reg + RE_2_WE), denali_nand_timing_set()
534 ioread32(denali->flash_reg + RE_2_RE), denali_nand_timing_set()
535 ioread32(denali->flash_reg + WE_2_RE), denali_nand_timing_set()
536 ioread32(denali->flash_reg + ADDR_2_DATA), denali_nand_timing_set()
537 ioread32(denali->flash_reg + RDWR_EN_LO_CNT), denali_nand_timing_set()
538 ioread32(denali->flash_reg + RDWR_EN_HI_CNT), denali_nand_timing_set()
539 ioread32(denali->flash_reg + CS_SETUP_CNT)); denali_nand_timing_set()
541 find_valid_banks(denali); denali_nand_timing_set()
543 detect_partition_feature(denali); denali_nand_timing_set()
550 nand_onfi_timing_set(denali, onfi_timing_mode); denali_nand_timing_set()
555 static void denali_set_intr_modes(struct denali_nand_info *denali, denali_set_intr_modes() argument
558 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", denali_set_intr_modes()
562 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); denali_set_intr_modes()
564 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); denali_set_intr_modes()
576 static void denali_irq_init(struct denali_nand_info *denali) denali_irq_init() argument
582 denali_set_intr_modes(denali, false); denali_irq_init()
587 for (i = 0; i < denali->max_banks; ++i) denali_irq_init()
588 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); denali_irq_init()
590 denali_irq_enable(denali, int_mask); denali_irq_init()
593 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) denali_irq_cleanup() argument
595 denali_set_intr_modes(denali, false); denali_irq_cleanup()
596 free_irq(irqnum, denali); denali_irq_cleanup()
599 static void denali_irq_enable(struct denali_nand_info *denali, denali_irq_enable() argument
604 for (i = 0; i < denali->max_banks; ++i) denali_irq_enable()
605 iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); denali_irq_enable()
612 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) denali_irq_detected() argument
614 return read_interrupt_status(denali) & DENALI_IRQ_ALL; denali_irq_detected()
618 static inline void clear_interrupt(struct denali_nand_info *denali, clear_interrupt() argument
623 intr_status_reg = INTR_STATUS(denali->flash_bank); clear_interrupt()
625 iowrite32(irq_mask, denali->flash_reg + intr_status_reg); clear_interrupt()
628 static void clear_interrupts(struct denali_nand_info *denali) clear_interrupts() argument
632 spin_lock_irq(&denali->irq_lock); clear_interrupts()
634 status = read_interrupt_status(denali); clear_interrupts()
635 clear_interrupt(denali, status); clear_interrupts()
637 denali->irq_status = 0x0; clear_interrupts()
638 spin_unlock_irq(&denali->irq_lock); clear_interrupts()
641 static uint32_t read_interrupt_status(struct denali_nand_info *denali) read_interrupt_status() argument
645 intr_status_reg = INTR_STATUS(denali->flash_bank); read_interrupt_status()
647 return ioread32(denali->flash_reg + intr_status_reg); read_interrupt_status()
656 struct denali_nand_info *denali = dev_id; denali_isr() local
660 spin_lock(&denali->irq_lock); denali_isr()
663 if (is_flash_bank_valid(denali->flash_bank)) { denali_isr()
668 irq_status = denali_irq_detected(denali); denali_isr()
672 clear_interrupt(denali, irq_status); denali_isr()
677 denali->irq_status |= irq_status; denali_isr()
679 complete(&denali->complete); denali_isr()
684 spin_unlock(&denali->irq_lock); denali_isr()
689 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) wait_for_irq() argument
697 wait_for_completion_timeout(&denali->complete, timeout); wait_for_irq()
698 spin_lock_irq(&denali->irq_lock); wait_for_irq()
699 intr_status = denali->irq_status; wait_for_irq()
702 denali->irq_status &= ~irq_mask; wait_for_irq()
703 spin_unlock_irq(&denali->irq_lock); wait_for_irq()
712 spin_unlock_irq(&denali->irq_lock); wait_for_irq()
729 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, setup_ecc_for_xfer() argument
739 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); setup_ecc_for_xfer()
740 iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); setup_ecc_for_xfer()
747 static int denali_send_pipeline_cmd(struct denali_nand_info *denali, denali_send_pipeline_cmd() argument
762 setup_ecc_for_xfer(denali, ecc_en, transfer_spare); denali_send_pipeline_cmd()
764 clear_interrupts(denali); denali_send_pipeline_cmd()
766 addr = BANK(denali->flash_bank) | denali->page; denali_send_pipeline_cmd()
770 iowrite32(cmd, denali->flash_mem); denali_send_pipeline_cmd()
774 index_addr(denali, cmd, access_type); denali_send_pipeline_cmd()
777 iowrite32(cmd, denali->flash_mem); denali_send_pipeline_cmd()
781 index_addr(denali, cmd, access_type); denali_send_pipeline_cmd()
790 iowrite32(cmd, denali->flash_mem); denali_send_pipeline_cmd()
792 index_addr(denali, cmd, denali_send_pipeline_cmd()
800 irq_status = wait_for_irq(denali, irq_mask); denali_send_pipeline_cmd()
803 dev_err(denali->dev, denali_send_pipeline_cmd()
805 cmd, denali->page, addr); denali_send_pipeline_cmd()
809 iowrite32(cmd, denali->flash_mem); denali_send_pipeline_cmd()
817 static int write_data_to_flash_mem(struct denali_nand_info *denali, write_data_to_flash_mem() argument
832 iowrite32(*buf32++, denali->flash_mem + 0x10); write_data_to_flash_mem()
837 static int read_data_from_flash_mem(struct denali_nand_info *denali, read_data_from_flash_mem() argument
854 *buf32++ = ioread32(denali->flash_mem + 0x10); read_data_from_flash_mem()
861 struct denali_nand_info *denali = mtd_to_denali(mtd); write_oob_data() local
867 denali->page = page; write_oob_data()
869 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, write_oob_data()
871 write_data_to_flash_mem(denali, buf, mtd->oobsize); write_oob_data()
874 irq_status = wait_for_irq(denali, irq_mask); write_oob_data()
877 dev_err(denali->dev, "OOB write failed\n"); write_oob_data()
881 dev_err(denali->dev, "unable to send pipeline command\n"); write_oob_data()
890 struct denali_nand_info *denali = mtd_to_denali(mtd); read_oob_data() local
894 denali->page = page; read_oob_data()
896 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, read_oob_data()
898 read_data_from_flash_mem(denali, buf, mtd->oobsize); read_oob_data()
905 irq_status = wait_for_irq(denali, irq_mask); read_oob_data()
908 dev_err(denali->dev, "page on OOB timeout %d\n", read_oob_data()
909 denali->page); read_oob_data()
918 addr = BANK(denali->flash_bank) | denali->page; read_oob_data()
920 index_addr(denali, cmd, MAIN_ACCESS); read_oob_data()
946 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, handle_ecc() argument
956 denali_set_intr_modes(denali, false); handle_ecc()
959 err_address = ioread32(denali->flash_reg + handle_ecc()
964 err_correction_info = ioread32(denali->flash_reg + handle_ecc()
985 denali->devnum + handle_ecc()
989 denali->mtd.ecc_stats.corrected++; handle_ecc()
1006 while (!(read_interrupt_status(denali) & handle_ecc()
1009 clear_interrupts(denali); handle_ecc()
1010 denali_set_intr_modes(denali, true); handle_ecc()
1017 static void denali_enable_dma(struct denali_nand_info *denali, bool en) denali_enable_dma() argument
1019 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); denali_enable_dma()
1020 ioread32(denali->flash_reg + DMA_ENABLE); denali_enable_dma()
1024 static void denali_setup_dma(struct denali_nand_info *denali, int op) denali_setup_dma() argument
1028 uint32_t addr = denali->buf.dma_buf; denali_setup_dma()
1030 mode = MODE_10 | BANK(denali->flash_bank); denali_setup_dma()
1035 index_addr(denali, mode | denali->page, 0x2000 | op | page_count); denali_setup_dma()
1038 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); denali_setup_dma()
1041 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); denali_setup_dma()
1044 index_addr(denali, mode | 0x14000, 0x2400); denali_setup_dma()
1054 struct denali_nand_info *denali = mtd_to_denali(mtd); write_page() local
1055 dma_addr_t addr = denali->buf.dma_buf; write_page()
1056 size_t size = denali->mtd.writesize + denali->mtd.oobsize; write_page()
1066 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); write_page()
1069 memcpy(denali->buf.buf, buf, mtd->writesize); write_page()
1073 memcpy(denali->buf.buf + mtd->writesize, write_page()
1078 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); write_page()
1080 clear_interrupts(denali); write_page()
1081 denali_enable_dma(denali, true); write_page()
1083 denali_setup_dma(denali, DENALI_WRITE); write_page()
1086 irq_status = wait_for_irq(denali, irq_mask); write_page()
1089 dev_err(denali->dev, "timeout on write_page (type = %d)\n", write_page()
1091 denali->status = NAND_STATUS_FAIL; write_page()
1094 denali_enable_dma(denali, false); write_page()
1095 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); write_page()
1150 struct denali_nand_info *denali = mtd_to_denali(mtd); denali_read_page() local
1152 dma_addr_t addr = denali->buf.dma_buf; denali_read_page()
1153 size_t size = denali->mtd.writesize + denali->mtd.oobsize; denali_read_page()
1160 if (page != denali->page) { denali_read_page()
1161 dev_err(denali->dev, denali_read_page()
1162 "IN %s: page %d is not equal to denali->page %d", denali_read_page()
1163 __func__, page, denali->page); denali_read_page()
1167 setup_ecc_for_xfer(denali, true, false); denali_read_page()
1169 denali_enable_dma(denali, true); denali_read_page()
1170 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); denali_read_page()
1172 clear_interrupts(denali); denali_read_page()
1173 denali_setup_dma(denali, DENALI_READ); denali_read_page()
1176 irq_status = wait_for_irq(denali, irq_mask); denali_read_page()
1178 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); denali_read_page()
1180 memcpy(buf, denali->buf.buf, mtd->writesize); denali_read_page()
1182 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); denali_read_page()
1183 denali_enable_dma(denali, false); denali_read_page()
1186 read_oob_data(&denali->mtd, chip->oob_poi, denali->page); denali_read_page()
1190 if (!is_erased(buf, denali->mtd.writesize)) denali_read_page()
1191 denali->mtd.ecc_stats.failed++; denali_read_page()
1192 if (!is_erased(buf, denali->mtd.oobsize)) denali_read_page()
1193 denali->mtd.ecc_stats.failed++; denali_read_page()
1202 struct denali_nand_info *denali = mtd_to_denali(mtd); denali_read_page_raw() local
1203 dma_addr_t addr = denali->buf.dma_buf; denali_read_page_raw()
1204 size_t size = denali->mtd.writesize + denali->mtd.oobsize; denali_read_page_raw()
1207 if (page != denali->page) { denali_read_page_raw()
1208 dev_err(denali->dev, denali_read_page_raw()
1209 "IN %s: page %d is not equal to denali->page %d", denali_read_page_raw()
1210 __func__, page, denali->page); denali_read_page_raw()
1214 setup_ecc_for_xfer(denali, false, true); denali_read_page_raw()
1215 denali_enable_dma(denali, true); denali_read_page_raw()
1217 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); denali_read_page_raw()
1219 clear_interrupts(denali); denali_read_page_raw()
1220 denali_setup_dma(denali, DENALI_READ); denali_read_page_raw()
1223 wait_for_irq(denali, irq_mask); denali_read_page_raw()
1225 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); denali_read_page_raw()
1227 denali_enable_dma(denali, false); denali_read_page_raw()
1229 memcpy(buf, denali->buf.buf, mtd->writesize); denali_read_page_raw()
1230 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); denali_read_page_raw()
1237 struct denali_nand_info *denali = mtd_to_denali(mtd); denali_read_byte() local
1240 if (denali->buf.head < denali->buf.tail) denali_read_byte()
1241 result = denali->buf.buf[denali->buf.head++]; denali_read_byte()
1248 struct denali_nand_info *denali = mtd_to_denali(mtd); denali_select_chip() local
1250 spin_lock_irq(&denali->irq_lock); denali_select_chip()
1251 denali->flash_bank = chip; denali_select_chip()
1252 spin_unlock_irq(&denali->irq_lock); denali_select_chip()
1257 struct denali_nand_info *denali = mtd_to_denali(mtd); denali_waitfunc() local
1258 int status = denali->status; denali_waitfunc()
1260 denali->status = 0; denali_waitfunc()
1267 struct denali_nand_info *denali = mtd_to_denali(mtd); denali_erase() local
1271 clear_interrupts(denali); denali_erase()
1274 cmd = MODE_10 | BANK(denali->flash_bank) | page; denali_erase()
1275 index_addr(denali, cmd, 0x1); denali_erase()
1278 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | denali_erase()
1287 struct denali_nand_info *denali = mtd_to_denali(mtd); denali_cmdfunc() local
1295 read_status(denali); denali_cmdfunc()
1299 reset_buf(denali); denali_cmdfunc()
1305 addr = MODE_11 | BANK(denali->flash_bank); denali_cmdfunc()
1306 index_addr(denali, addr | 0, 0x90); denali_cmdfunc()
1307 index_addr(denali, addr | 1, 0); denali_cmdfunc()
1309 index_addr_read_data(denali, addr | 2, &id); denali_cmdfunc()
1310 write_byte_to_buf(denali, id); denali_cmdfunc()
1315 denali->page = page; denali_cmdfunc()
1318 reset_bank(denali); denali_cmdfunc()
1331 static void denali_hw_init(struct denali_nand_info *denali) denali_hw_init() argument
1339 denali->bbtskipbytes = ioread32(denali->flash_reg + denali_hw_init()
1341 detect_max_banks(denali); denali_hw_init()
1342 denali_nand_reset(denali); denali_hw_init()
1343 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); denali_hw_init()
1345 denali->flash_reg + CHIP_ENABLE_DONT_CARE); denali_hw_init()
1347 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); denali_hw_init()
1350 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); denali_hw_init()
1351 iowrite32(1, denali->flash_reg + ECC_ENABLE); denali_hw_init()
1352 denali_nand_timing_set(denali); denali_hw_init()
1353 denali_irq_init(denali); denali_hw_init()
1358 * but denali controller in MRST only support 15bit and 8bit ECC
1395 static void denali_drv_init(struct denali_nand_info *denali) denali_drv_init() argument
1397 denali->idx = 0; denali_drv_init()
1404 init_completion(&denali->complete); denali_drv_init()
1410 spin_lock_init(&denali->irq_lock); denali_drv_init()
1413 denali->flash_bank = CHIP_SELECT_INVALID; denali_drv_init()
1416 denali->irq_status = 0; denali_drv_init()
1419 int denali_init(struct denali_nand_info *denali) denali_init() argument
1423 if (denali->platform == INTEL_CE4100) { denali_init()
1435 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, denali_init()
1437 if (!denali->buf.buf) denali_init()
1440 denali->mtd.dev.parent = denali->dev; denali_init()
1441 denali_hw_init(denali); denali_init()
1442 denali_drv_init(denali); denali_init()
1448 if (request_irq(denali->irq, denali_isr, IRQF_SHARED, denali_init()
1449 DENALI_NAND_NAME, denali)) { denali_init()
1455 denali_set_intr_modes(denali, true); denali_init()
1456 denali->mtd.name = "denali-nand"; denali_init()
1457 denali->mtd.owner = THIS_MODULE; denali_init()
1458 denali->mtd.priv = &denali->nand; denali_init()
1461 denali->nand.select_chip = denali_select_chip; denali_init()
1462 denali->nand.cmdfunc = denali_cmdfunc; denali_init()
1463 denali->nand.read_byte = denali_read_byte; denali_init()
1464 denali->nand.waitfunc = denali_waitfunc; denali_init()
1471 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { denali_init()
1477 devm_kfree(denali->dev, denali->buf.buf); denali_init()
1478 denali->buf.buf = devm_kzalloc(denali->dev, denali_init()
1479 denali->mtd.writesize + denali->mtd.oobsize, denali_init()
1481 if (!denali->buf.buf) { denali_init()
1487 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); denali_init()
1493 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, denali_init()
1494 denali->mtd.writesize + denali->mtd.oobsize, denali_init()
1496 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { denali_init()
1497 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n"); denali_init()
1507 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); denali_init()
1508 denali->nand.chipsize <<= (denali->devnum - 1); denali_init()
1509 denali->nand.page_shift += (denali->devnum - 1); denali_init()
1510 denali->nand.pagemask = (denali->nand.chipsize >> denali_init()
1511 denali->nand.page_shift) - 1; denali_init()
1512 denali->nand.bbt_erase_shift += (denali->devnum - 1); denali_init()
1513 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; denali_init()
1514 denali->nand.chip_shift += (denali->devnum - 1); denali_init()
1515 denali->mtd.writesize <<= (denali->devnum - 1); denali_init()
1516 denali->mtd.oobsize <<= (denali->devnum - 1); denali_init()
1517 denali->mtd.erasesize <<= (denali->devnum - 1); denali_init()
1518 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; denali_init()
1519 denali->bbtskipbytes *= denali->devnum; denali_init()
1528 denali->nand.bbt_td = &bbt_main_descr; denali_init()
1529 denali->nand.bbt_md = &bbt_mirror_descr; denali_init()
1532 denali->nand.bbt_options |= NAND_BBT_USE_FLASH; denali_init()
1533 denali->nand.options |= NAND_SKIP_BBTSCAN; denali_init()
1534 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; denali_init()
1536 /* no subpage writes on denali */ denali_init()
1537 denali->nand.options |= NAND_NO_SUBPAGE_WRITE; denali_init()
1544 if (!nand_is_slc(&denali->nand) && denali_init()
1545 (denali->mtd.oobsize > (denali->bbtskipbytes + denali_init()
1546 ECC_15BITS * (denali->mtd.writesize / denali_init()
1549 denali->nand.ecc.strength = 15; denali_init()
1550 denali->nand.ecc.layout = &nand_15bit_oob; denali_init()
1551 denali->nand.ecc.bytes = ECC_15BITS; denali_init()
1552 iowrite32(15, denali->flash_reg + ECC_CORRECTION); denali_init()
1553 } else if (denali->mtd.oobsize < (denali->bbtskipbytes + denali_init()
1554 ECC_8BITS * (denali->mtd.writesize / denali_init()
1559 denali->nand.ecc.strength = 8; denali_init()
1560 denali->nand.ecc.layout = &nand_8bit_oob; denali_init()
1561 denali->nand.ecc.bytes = ECC_8BITS; denali_init()
1562 iowrite32(8, denali->flash_reg + ECC_CORRECTION); denali_init()
1565 denali->nand.ecc.bytes *= denali->devnum; denali_init()
1566 denali->nand.ecc.strength *= denali->devnum; denali_init()
1567 denali->nand.ecc.layout->eccbytes *= denali_init()
1568 denali->mtd.writesize / ECC_SECTOR_SIZE; denali_init()
1569 denali->nand.ecc.layout->oobfree[0].offset = denali_init()
1570 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; denali_init()
1571 denali->nand.ecc.layout->oobfree[0].length = denali_init()
1572 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - denali_init()
1573 denali->bbtskipbytes; denali_init()
1580 denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift; denali_init()
1581 denali->blksperchip = denali->totalblks / denali->nand.numchips; denali_init()
1584 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; denali_init()
1585 denali->nand.ecc.read_page = denali_read_page; denali_init()
1586 denali->nand.ecc.read_page_raw = denali_read_page_raw; denali_init()
1587 denali->nand.ecc.write_page = denali_write_page; denali_init()
1588 denali->nand.ecc.write_page_raw = denali_write_page_raw; denali_init()
1589 denali->nand.ecc.read_oob = denali_read_oob; denali_init()
1590 denali->nand.ecc.write_oob = denali_write_oob; denali_init()
1591 denali->nand.erase = denali_erase; denali_init()
1593 if (nand_scan_tail(&denali->mtd)) { denali_init()
1598 ret = mtd_device_register(&denali->mtd, NULL, 0); denali_init()
1600 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n", denali_init()
1607 denali_irq_cleanup(denali->irq, denali); denali_init()
1614 void denali_remove(struct denali_nand_info *denali) denali_remove() argument
1616 denali_irq_cleanup(denali->irq, denali); denali_remove()
1617 dma_unmap_single(denali->dev, denali->buf.dma_buf, denali_remove()
1618 denali->mtd.writesize + denali->mtd.oobsize, denali_remove()
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