| /linux-4.1.27/arch/mips/rb532/ |
| D | prom.c | 124 struct ddr_ram __iomem *ddr; in prom_init() local
128 ddr = ioremap_nocache(ddr_reg[0].start, in prom_init()
131 if (!ddr) { in prom_init()
136 ddrbase = (phys_addr_t)&ddr->ddrbase; in prom_init()
137 memsize = (phys_addr_t)&ddr->ddrmask; in prom_init()
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| /linux-4.1.27/Documentation/devicetree/bindings/arm/calxeda/ |
| D | mem-ctrlr.txt | 5 - "calxeda,hb-ddr-ctrl" for ECX-1000
6 - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
13 compatible = "calxeda,hb-ddr-ctrl";
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| /linux-4.1.27/drivers/media/pci/cx18/ |
| D | cx18-cards.c | 88 .ddr = {
135 .ddr = {
182 .ddr = {
235 .ddr = {
288 .ddr = {
348 .ddr = {
404 .ddr = {
453 .ddr = {
501 .ddr = {
554 .ddr = {
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| D | cx18-firmware.c | 338 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); in cx18_init_memory()
342 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); in cx18_init_memory()
343 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); in cx18_init_memory()
344 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); in cx18_init_memory()
349 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); in cx18_init_memory()
350 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); in cx18_init_memory()
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| D | cx18-cards.h | 149 struct cx18_ddr ddr; member
|
| /linux-4.1.27/sound/soc/intel/atom/sst/ |
| D | sst_pci.c | 61 ctx->ddr = pcim_iomap(pci, 0, in sst_platform_get_resources()
63 if (!ctx->ddr) { in sst_platform_get_resources()
67 dev_dbg(ctx->dev, "sst: DDR Ptr %p\n", ctx->ddr); in sst_platform_get_resources()
69 ctx->ddr = NULL; in sst_platform_get_resources()
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| D | sst.c | 478 fw_save->ddr = kzalloc(ctx->ddr_end - ctx->ddr_base, GFP_KERNEL); in intel_sst_suspend()
479 if (!fw_save->ddr) { in intel_sst_suspend()
481 goto ddr; in intel_sst_suspend()
487 memcpy32_fromio(fw_save->ddr, ctx->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_suspend()
492 ddr: in intel_sst_suspend()
523 memcpy32_toio(ctx->ddr, fw_save->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_resume()
528 kfree(fw_save->ddr); in intel_sst_resume()
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| D | sst_acpi.c | 213 ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base, in sst_platform_get_resources()
215 if (!ctx->ddr) { in sst_platform_get_resources()
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| D | sst.h | 344 void *ddr; member
387 void __iomem *ddr; member
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| D | sst_loader.c | 208 ram_iomem = sst_drv_ctx->ddr; in sst_parse_module_memcpy()
|
| /linux-4.1.27/arch/arm/boot/dts/ |
| D | exynos5410-smdk5410.dts | 48 samsung,dw-mshc-ddr-timing = <1 2>;
59 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | exynos5260-xyref5260.dts | 77 samsung,dw-mshc-ddr-timing = <0 2>;
90 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | k2e-clocks.dtsi | 33 clock-output-names = "ddr-3a-pll-clk";
|
| D | tegra30-cardhu-a04.dts | 25 regulator-name = "ddr";
|
| D | ecx-2000.dts | 89 compatible = "calxeda,ecx-2000-ddr-ctrl";
|
| D | exynos5420-arndale-octa.dts | 56 samsung,dw-mshc-ddr-timing = <0 2>;
69 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | exynos5422-odroidxu3.dts | 313 samsung,dw-mshc-ddr-timing = <0 2>;
325 samsung,dw-mshc-ddr-timing = <0 2>;
|
| D | exynos5250-smdk5250.dts | 352 samsung,dw-mshc-ddr-timing = <1 2>;
365 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | highbank.dts | 90 compatible = "calxeda,hb-ddr-ctrl";
|
| D | exynos5420-smdk5420.dts | 82 samsung,dw-mshc-ddr-timing = <0 2>;
97 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | exynos5250-snow.dts | 540 samsung,dw-mshc-ddr-timing = <1 2>;
553 samsung,dw-mshc-ddr-timing = <1 2>;
574 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | wm8650.dtsi | 137 clkddr: ddr {
|
| D | k2hk-clocks.dtsi | 42 clock-output-names = "ddr-3a-pll-clk";
51 clock-output-names = "ddr-3b-pll-clk";
|
| D | exynos5250-arndale.dts | 528 samsung,dw-mshc-ddr-timing = <1 2>;
542 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | exynos5250-spring.dts | 437 samsung,dw-mshc-ddr-timing = <1 2>;
455 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | stih416-clock.dtsi | 728 clockgen-ddr@0xfdde07d8 {
731 clockgen_ddr_pll: clockgen-ddr-pll {
733 compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
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| D | wm8505.dtsi | 133 clkddr: ddr {
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| D | wm8850.dtsi | 154 clkddr: ddr {
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| D | exynos5420-peach-pit.dts | 701 samsung,dw-mshc-ddr-timing = <0 2>;
719 samsung,dw-mshc-ddr-timing = <0 2>;
737 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | exynos5800-peach-pi.dts | 664 samsung,dw-mshc-ddr-timing = <0 2>;
682 samsung,dw-mshc-ddr-timing = <0 2>;
700 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | wm8750.dtsi | 143 clkddr: ddr {
|
| D | tegra114-tn7.dts | 110 regulator-name = "vd-ddr";
|
| D | k2l-clocks.dtsi | 42 clock-output-names = "ddr-3a-pll-clk";
|
| D | am335x-lxm.dts | 195 regulator-name = "vio_1v5,ddr";
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| D | exynos4412-odroid-common.dtsi | 98 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | exynos4412-origen.dts | 145 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | exynos3250-monk.dts | 412 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | r8a7794.dtsi | 541 clock-output-names = "ddr";
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| D | exynos3250-rinato.dts | 585 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | tegra114-roth.dts | 823 regulator-name = "vdd-ddr";
|
| D | tegra114-dalmore.dts | 931 regulator-name = "vddio-ddr";
|
| D | exynos4412-trats2.dts | 609 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | r8a7790.dtsi | 1072 clock-output-names = "ddr";
|
| D | r8a7791.dtsi | 1078 clock-output-names = "ddr";
|
| /linux-4.1.27/arch/arm64/boot/dts/exynos/ |
| D | exynos7-espresso.dts | 65 samsung,dw-mshc-ddr-timing = <0 2>;
79 samsung,dw-mshc-ddr-timing = <1 2>;
|
| /linux-4.1.27/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-pll.txt | 19 "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
21 "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
|
| /linux-4.1.27/Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
42 Notes for the sdr-timing and ddr-timing values:
89 samsung,dw-mshc-ddr-timing = <1 2>;
|
| D | mmc.txt | 37 - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
38 - mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
|
| /linux-4.1.27/arch/powerpc/boot/dts/fsl/ |
| D | p5020si-post.dtsi | 218 dcsr-ddr@12000 {
219 compatible = "fsl,dcsr-ddr";
223 dcsr-ddr@13000 {
224 compatible = "fsl,dcsr-ddr";
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| D | p5040si-post.dtsi | 163 dcsr-ddr@12000 {
164 compatible = "fsl,dcsr-ddr";
168 dcsr-ddr@13000 {
169 compatible = "fsl,dcsr-ddr";
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| D | t4240si-post.dtsi | 205 dcsr-ddr@12000 {
206 compatible = "fsl,dcsr-ddr";
210 dcsr-ddr@13000 {
211 compatible = "fsl,dcsr-ddr";
215 dcsr-ddr@14000 {
216 compatible = "fsl,dcsr-ddr";
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| D | p4080si-post.dtsi | 190 dcsr-ddr@12000 {
191 compatible = "fsl,dcsr-ddr";
195 dcsr-ddr@13000 {
196 compatible = "fsl,dcsr-ddr";
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| D | b4860si-post.dtsi | 78 dcsr-ddr@13000 {
79 compatible = "fsl,dcsr-ddr";
|
| D | b4si-post.dtsi | 108 dcsr-ddr@12000 {
109 compatible = "fsl,dcsr-ddr";
|
| D | p3041si-post.dtsi | 216 dcsr-ddr@12000 {
217 compatible = "fsl,dcsr-ddr";
|
| D | p2041si-post.dtsi | 189 dcsr-ddr@12000 {
190 compatible = "fsl,dcsr-ddr";
|
| D | t1040si-post.dtsi | 183 dcsr-ddr@12000 {
184 compatible = "fsl,dcsr-ddr";
|
| D | t2081si-post.dtsi | 185 dcsr-ddr@12000 {
186 compatible = "fsl,dcsr-ddr";
|
| /linux-4.1.27/drivers/gpio/ |
| D | gpio-adnp.c | 195 u8 ddr, plr, ier, isr; in adnp_gpio_dbg_show() local
199 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); in adnp_gpio_dbg_show()
232 if (ddr & BIT(j)) in adnp_gpio_dbg_show()
|
| /linux-4.1.27/Documentation/devicetree/bindings/video/ |
| D | rockchip-vop.txt | 19 aclk_vop: for ddr buffer transfer.
|
| D | adi,adv7511.txt | 24 pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
|
| /linux-4.1.27/drivers/mfd/ |
| D | sm501.c | 956 unsigned long ddr; in sm501_gpio_input() local
963 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); in sm501_gpio_input()
964 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); in sm501_gpio_input()
983 unsigned long ddr; in sm501_gpio_output() local
997 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); in sm501_gpio_output()
998 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); in sm501_gpio_output()
|
| /linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dcsr.txt | 274 Definition: Must include "fsl,dcsr-ddr"
289 dcsr-ddr@12000 {
290 compatible = "fsl,dcsr-ddr";
|
| /linux-4.1.27/drivers/mmc/core/ |
| D | mmc.c | 842 int err, ddr; in mmc_select_powerclass() local
853 ddr = card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_52; in mmc_select_powerclass()
854 if (ddr) in mmc_select_powerclass()
864 mmc_hostname(host), 1 << bus_width, ddr); in mmc_select_powerclass()
|
| /linux-4.1.27/Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra30-pinmux.txt | 97 dap, ddr, dev3, displaya, displayb, dtv, extperiph1, extperiph2,
|
| /linux-4.1.27/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 23 28 ddr DDR Cntrl
|
| /linux-4.1.27/drivers/video/fbdev/matrox/ |
| D | matroxfb_misc.c | 668 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; in parse_pins5()
702 minfo->values.memory.ddr = 1; in default_pins5()
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| D | matroxfb_base.h | 514 unsigned int ddr:1, member
|
| D | matroxfb_DAC1064.c | 768 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) { in g450_memory_init()
|
| /linux-4.1.27/drivers/infiniband/hw/qib/ |
| D | qib_iba7220.c | 2704 u64 val, ddr; in qib_7220_set_loopback() local
2722 ddr = ppd->cpspec->ibcddrctrl & ~(IBA7220_IBC_HRTBT_MASK in qib_7220_set_loopback()
2724 ppd->cpspec->ibcddrctrl = ddr | val; in qib_7220_set_loopback()
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| D | qib_iba7322.c | 588 struct txdds_ent ddr; member
7698 *ddr_dds = &v->ddr; in find_best_ent()
|
| /linux-4.1.27/drivers/video/fbdev/omap2/dss/ |
| D | dsi.c | 1875 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) in ddr2ns() argument
1880 return ddr * 1000 * 1000 / (ddr_clk / 1000); in ddr2ns()
|
| /linux-4.1.27/arch/mips/include/asm/octeon/ |
| D | cvmx-mio-defs.h | 437 uint64_t ddr:1; member
459 uint64_t ddr:1;
|
| /linux-4.1.27/drivers/pinctrl/ |
| D | pinctrl-tegra30.c | 2033 FUNCTION(ddr),
|