| /linux-4.1.27/drivers/video/fbdev/riva/ |
| D | nv_driver.c | 275 unsigned long dclk = 0; in riva_get_maxdclk() local
285 dclk = 800000; in riva_get_maxdclk()
287 dclk = 1000000; in riva_get_maxdclk()
293 dclk = 1000000; in riva_get_maxdclk()
302 dclk = 800000; in riva_get_maxdclk()
305 dclk = 1000000; in riva_get_maxdclk()
310 return dclk; in riva_get_maxdclk()
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| /linux-4.1.27/arch/mips/jz4740/ |
| D | clock.c | 482 struct divided_clk *dclk = (struct divided_clk *)clk; in jz_clk_divided_get_rate() local
488 div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1; in jz_clk_divided_get_rate()
495 struct divided_clk *dclk = (struct divided_clk *)clk; in jz_clk_divided_set_rate() local
505 else if (div > dclk->mask) in jz_clk_divided_set_rate()
506 div = dclk->mask; in jz_clk_divided_set_rate()
508 jz_clk_reg_write_mask(dclk->reg, div, dclk->mask); in jz_clk_divided_set_rate()
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| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| D | rs780_dpm.c | 571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.c | 896 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
909 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
941 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
952 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1441 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1627 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1630 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1856 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1935 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1960 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.h | 70 u32 dclk; member
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| D | radeon_uvd.c | 911 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
926 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
947 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers()
953 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| D | sumo_dpm.c | 825 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
842 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock()
860 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock()
1416 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info()
1419 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1802 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1825 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1833 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| D | rv770_dpm.c | 1440 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1446 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1457 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1463 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2155 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2158 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2162 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2164 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2440 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2484 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| D | rv6xx_dpm.c | 1520 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock()
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1537 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock()
1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1805 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1808 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| D | radeon_asic.h | 411 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
477 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
534 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
535 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
747 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
784 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| D | rv770.c | 45 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
47 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
54 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
61 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
67 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
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| D | ni_dpm.c | 3516 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3523 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3534 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3541 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3905 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ni_parse_pplib_non_clock_info()
3908 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in ni_parse_pplib_non_clock_info()
3911 rps->dclk = 0; in ni_parse_pplib_non_clock_info()
4288 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4316 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
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| D | kv_dpm.c | 836 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
842 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); in kv_populate_uvd_table()
851 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table()
2221 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2595 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in kv_parse_pplib_non_clock_info()
2598 rps->dclk = 0; in kv_parse_pplib_non_clock_info()
2854 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
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| D | radeon.h | 1351 u32 dclk; member
1437 u32 dclk; member
1699 unsigned vclk, unsigned dclk,
1965 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| D | si_dpm.c | 2278 radeon_state->vclk && radeon_state->dclk) in si_should_disable_uvd_powertune()
2967 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
5107 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) in si_is_state_ulv_compatible()
5144 if (radeon_state->vclk && radeon_state->dclk) { in si_convert_power_state_to_smc()
6637 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in si_parse_pplib_non_clock_info()
6640 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in si_parse_pplib_non_clock_info()
6643 rps->dclk = 0; in si_parse_pplib_non_clock_info()
6997 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_debugfs_print_current_performance_level()
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| D | evergreen.c | 1092 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in sumo_set_uvd_clocks() argument
1103 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS); in sumo_set_uvd_clocks()
1107 cg_scratch |= (dclk / 100) << 16; /* Mhz */ in sumo_set_uvd_clocks()
1115 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in evergreen_set_uvd_clocks() argument
1129 if (!vclk || !dclk) { in evergreen_set_uvd_clocks()
1135 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, in evergreen_set_uvd_clocks()
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| D | r600.c | 150 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in r600_set_uvd_clocks() argument
168 if (!vclk || !dclk) { in r600_set_uvd_clocks()
179 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in r600_set_uvd_clocks()
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| D | ci_dpm.c | 2632 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
5427 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ci_parse_pplib_non_clock_info()
5430 rps->dclk = 0; in ci_parse_pplib_non_clock_info()
5916 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ci_dpm_print_power_state()
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| D | r600_dpm.c | 1159 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = in r600_parse_extended_power_table()
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| D | si.c | 7273 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in si_set_uvd_clocks() argument
7286 if (!vclk || !dclk) { in si_set_uvd_clocks()
7291 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, in si_set_uvd_clocks()
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| D | btc_dpm.c | 2753 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in btc_dpm_debugfs_print_current_performance_level()
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| D | cik.c | 9714 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in cik_set_uvd_clocks() argument
9722 r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS); in cik_set_uvd_clocks()
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| /linux-4.1.27/drivers/video/fbdev/core/ |
| D | fbmon.c | 1105 u32 dclk; member
1194 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) in fb_get_hblank_by_dclk() argument
1198 dclk /= 1000; in fb_get_hblank_by_dclk()
1201 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk()
1245 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1256 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
1261 timings->hblank = fb_get_hblank_by_dclk(timings->dclk, in fb_timings_dclk()
1264 timings->hfreq = timings->dclk/timings->htotal; in fb_timings_dclk()
1356 if (timings->dclk > dclkmax) { in fb_get_mode()
1357 timings->dclk = dclkmax; in fb_get_mode()
[all …]
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| /linux-4.1.27/Documentation/devicetree/bindings/video/ |
| D | rockchip-vop.txt | 28 - dclk
44 reset-names = "axi", "ahb", "dclk";
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| /linux-4.1.27/drivers/gpu/drm/rockchip/ |
| D | rockchip_drm_vop.c | 112 struct clk *dclk; member
436 ret = clk_enable(vop->dclk); in vop_enable()
480 clk_disable(vop->dclk); in vop_enable()
523 clk_disable(vop->dclk); in vop_disable()
910 clk_disable(vop->dclk); in vop_crtc_mode_set()
959 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_mode_set()
961 ret_clk = clk_enable(vop->dclk); in vop_crtc_mode_set()
1297 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); in vop_initial()
1298 if (IS_ERR(vop->dclk)) { in vop_initial()
1300 return PTR_ERR(vop->dclk); in vop_initial()
[all …]
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| /linux-4.1.27/drivers/clk/samsung/ |
| D | Kconfig | 16 Temporary symbol to build the dclk driver based on the common clock
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| D | Makefile | 19 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
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| /linux-4.1.27/include/linux/mfd/ |
| D | si476x-platform.h | 130 enum si476x_dclk_config dclk; member
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| /linux-4.1.27/arch/blackfin/mach-bf609/ |
| D | clock.c | 343 static struct clk dclk = { variable
387 CLK(dclk, NULL, "DCLK"),
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| /linux-4.1.27/drivers/mfd/ |
| D | si476x-i2c.c | 50 core->pinmux.dclk, in si476x_core_config_pinmux()
817 core->pinmux.dclk == SI476X_DCLK_DAUDIO && in si476x_core_probe()
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| D | si476x-cmd.c | 530 enum si476x_dclk_config dclk, in si476x_core_cmd_dig_audio_pin_cfg() argument
537 PIN_CFG_BYTE(dclk), in si476x_core_cmd_dig_audio_pin_cfg()
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| /linux-4.1.27/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 31 4 = dclk (SDRAM Interface Clock)
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| /linux-4.1.27/drivers/video/fbdev/savage/ |
| D | savagefb_driver.c | 978 int width, dclk, i, j; /*, refresh; */ in savagefb_decode_var() local
1021 dclk = timings.Clock; in savagefb_decode_var()
1026 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) in savagefb_decode_var()
1033 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1040 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1085 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r); in savagefb_decode_var()
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| /linux-4.1.27/arch/arm/boot/dts/ |
| D | rk3288.dtsi | 613 reset-names = "axi", "ahb", "dclk";
644 reset-names = "axi", "ahb", "dclk";
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