Searched refs:cpu_base (Results 1 - 15 of 15) sorted by relevance

/linux-4.1.27/kernel/time/
H A Dhrtimer.c160 raw_spin_lock_irqsave(&base->cpu_base->lock, *flags); lock_hrtimer_base()
164 raw_spin_unlock_irqrestore(&base->cpu_base->lock, *flags); lock_hrtimer_base()
175 * Called with cpu_base->lock of target cpu held.
183 if (!new_base->cpu_base->hres_active) hrtimer_check_target()
187 return expires.tv64 <= new_base->cpu_base->expires_next.tv64; hrtimer_check_target()
225 raw_spin_unlock(&base->cpu_base->lock); switch_hrtimer_base()
226 raw_spin_lock(&new_base->cpu_base->lock); switch_hrtimer_base()
230 raw_spin_unlock(&new_base->cpu_base->lock); switch_hrtimer_base()
231 raw_spin_lock(&base->cpu_base->lock); switch_hrtimer_base()
252 raw_spin_lock_irqsave(&base->cpu_base->lock, *flags); lock_hrtimer_base()
446 static ktime_t __hrtimer_get_next_event(struct hrtimer_cpu_base *cpu_base) __hrtimer_get_next_event() argument
448 struct hrtimer_clock_base *base = cpu_base->clock_base; __hrtimer_get_next_event()
522 hrtimer_force_reprogram(struct hrtimer_cpu_base *cpu_base, int skip_equal) hrtimer_force_reprogram() argument
524 ktime_t expires_next = __hrtimer_get_next_event(cpu_base); hrtimer_force_reprogram()
526 if (skip_equal && expires_next.tv64 == cpu_base->expires_next.tv64) hrtimer_force_reprogram()
529 cpu_base->expires_next.tv64 = expires_next.tv64; hrtimer_force_reprogram()
545 if (cpu_base->hang_detected) hrtimer_force_reprogram()
548 if (cpu_base->expires_next.tv64 != KTIME_MAX) hrtimer_force_reprogram()
549 tick_program_event(cpu_base->expires_next, 1); hrtimer_force_reprogram()
564 * Called with interrupts disabled and base->cpu_base.lock held
569 struct hrtimer_cpu_base *cpu_base = this_cpu_ptr(&hrtimer_bases); hrtimer_reprogram() local
594 if (expires.tv64 >= cpu_base->expires_next.tv64) hrtimer_reprogram()
603 if (cpu_base->in_hrtirq) hrtimer_reprogram()
612 if (cpu_base->hang_detected) hrtimer_reprogram()
620 cpu_base->expires_next = expires; hrtimer_reprogram()
625 * Initialize the high resolution related parts of cpu_base
795 raw_spin_unlock_irqrestore(&timer->base->cpu_base->lock, *flags); unlock_hrtimer_base()
853 base->cpu_base->active_bases |= 1 << base->index; enqueue_hrtimer()
892 if (base->cpu_base->expires_next.tv64 == expires.tv64) __remove_hrtimer()
893 hrtimer_force_reprogram(base->cpu_base, 1); __remove_hrtimer()
898 base->cpu_base->active_bases &= ~(1 << base->index); __remove_hrtimer()
923 reprogram = base->cpu_base == this_cpu_ptr(&hrtimer_bases); remove_hrtimer()
982 wake_up_nohz_cpu(new_base->cpu_base->cpu); __hrtimer_start_range_ns()
983 } else if (new_base->cpu_base == this_cpu_ptr(&hrtimer_bases) && __hrtimer_start_range_ns()
993 * We need to drop cpu_base->lock to avoid a __hrtimer_start_range_ns()
996 raw_spin_unlock(&new_base->cpu_base->lock); __hrtimer_start_range_ns()
1123 struct hrtimer_cpu_base *cpu_base = this_cpu_ptr(&hrtimer_bases); hrtimer_get_next_event() local
1127 raw_spin_lock_irqsave(&cpu_base->lock, flags); hrtimer_get_next_event()
1130 mindelta = ktime_sub(__hrtimer_get_next_event(cpu_base), hrtimer_get_next_event()
1133 raw_spin_unlock_irqrestore(&cpu_base->lock, flags); hrtimer_get_next_event()
1144 struct hrtimer_cpu_base *cpu_base; __hrtimer_init() local
1149 cpu_base = raw_cpu_ptr(&hrtimer_bases); __hrtimer_init()
1155 timer->base = &cpu_base->clock_base[base]; __hrtimer_init()
1189 struct hrtimer_cpu_base *cpu_base; hrtimer_get_res() local
1192 cpu_base = raw_cpu_ptr(&hrtimer_bases); hrtimer_get_res()
1193 *tp = ktime_to_timespec(cpu_base->clock_base[base].resolution); hrtimer_get_res()
1202 struct hrtimer_cpu_base *cpu_base = base->cpu_base; __run_hrtimer() local
1218 raw_spin_unlock(&cpu_base->lock); __run_hrtimer()
1222 raw_spin_lock(&cpu_base->lock); __run_hrtimer()
1247 struct hrtimer_cpu_base *cpu_base = this_cpu_ptr(&hrtimer_bases); hrtimer_interrupt() local
1251 BUG_ON(!cpu_base->hres_active); hrtimer_interrupt()
1252 cpu_base->nr_events++; hrtimer_interrupt()
1255 raw_spin_lock(&cpu_base->lock); hrtimer_interrupt()
1256 entry_time = now = hrtimer_update_base(cpu_base); hrtimer_interrupt()
1258 cpu_base->in_hrtirq = 1; hrtimer_interrupt()
1260 * We set expires_next to KTIME_MAX here with cpu_base->lock hrtimer_interrupt()
1266 cpu_base->expires_next.tv64 = KTIME_MAX; hrtimer_interrupt()
1273 if (!(cpu_base->active_bases & (1 << i))) hrtimer_interrupt()
1276 base = cpu_base->clock_base + i; hrtimer_interrupt()
1303 expires_next = __hrtimer_get_next_event(cpu_base); hrtimer_interrupt()
1308 cpu_base->expires_next = expires_next; hrtimer_interrupt()
1309 cpu_base->in_hrtirq = 0; hrtimer_interrupt()
1310 raw_spin_unlock(&cpu_base->lock); hrtimer_interrupt()
1315 cpu_base->hang_detected = 0; hrtimer_interrupt()
1332 raw_spin_lock(&cpu_base->lock); hrtimer_interrupt()
1333 now = hrtimer_update_base(cpu_base); hrtimer_interrupt()
1334 cpu_base->nr_retries++; hrtimer_interrupt()
1343 cpu_base->nr_hangs++; hrtimer_interrupt()
1344 cpu_base->hang_detected = 1; hrtimer_interrupt()
1345 raw_spin_unlock(&cpu_base->lock); hrtimer_interrupt()
1347 if (delta.tv64 > cpu_base->max_hang_time.tv64) hrtimer_interrupt()
1348 cpu_base->max_hang_time = delta; hrtimer_interrupt()
1437 struct hrtimer_cpu_base *cpu_base = this_cpu_ptr(&hrtimer_bases); hrtimer_run_queues() local
1445 base = &cpu_base->clock_base[index]; hrtimer_run_queues()
1450 hrtimer_get_softirq_time(cpu_base); hrtimer_run_queues()
1454 raw_spin_lock(&cpu_base->lock); hrtimer_run_queues()
1466 raw_spin_unlock(&cpu_base->lock); hrtimer_run_queues()
1619 struct hrtimer_cpu_base *cpu_base = &per_cpu(hrtimer_bases, cpu); init_hrtimers_cpu() local
1623 cpu_base->clock_base[i].cpu_base = cpu_base; init_hrtimers_cpu()
1624 timerqueue_init_head(&cpu_base->clock_base[i].active); init_hrtimers_cpu()
1627 cpu_base->cpu = cpu; init_hrtimers_cpu()
1628 hrtimer_init_hres(cpu_base); init_hrtimers_cpu()
H A Dtimer_list.c94 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); print_active_timers()
110 raw_spin_unlock_irqrestore(&base->cpu_base->lock, flags); print_active_timers()
116 raw_spin_unlock_irqrestore(&base->cpu_base->lock, flags); print_active_timers()
140 struct hrtimer_cpu_base *cpu_base = &per_cpu(hrtimer_bases, cpu); print_cpu() local
146 print_base(m, cpu_base->clock_base + i, now); print_cpu()
150 (unsigned long long)(cpu_base->x)) print_cpu()
153 (unsigned long long)(ktime_to_ns(cpu_base->x))) print_cpu()
/linux-4.1.27/arch/powerpc/boot/
H A Dcuboot-c2k.c32 unsigned long cpu_base; c2k_bridge_setup() local
101 cpu_base = v[i+3]; c2k_bridge_setup()
104 buf[0] = cpu_base; c2k_bridge_setup()
107 if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base)) c2k_bridge_setup()
109 "0x%x\n\r", (u32)cpu_base); c2k_bridge_setup()
112 pci_base_hi, pci_base_lo, cpu_base, size, tbl); c2k_bridge_setup()
H A Dprpmc2800.c322 unsigned long cpu_base; prpmc2800_bridge_setup() local
380 cpu_base = v[i+3]; prpmc2800_bridge_setup()
383 buf[0] = cpu_base; prpmc2800_bridge_setup()
386 if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base)) prpmc2800_bridge_setup()
388 (u32)cpu_base); prpmc2800_bridge_setup()
391 pci_base_lo, cpu_base, size, tbl); prpmc2800_bridge_setup()
H A Dmv64x60.h58 u32 pci_base_lo, u32 cpu_base, u32 size,
H A Dmv64x60.c496 u32 pci_base_lo, u32 cpu_base, u32 size, mv64x60_config_cpu2pci_window()
499 cpu_base >>= 16; mv64x60_config_cpu2pci_window()
500 cpu_base |= MV64x60_CPU2PCI_SWAP_NONE; mv64x60_config_cpu2pci_window()
501 out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base); mv64x60_config_cpu2pci_window()
495 mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, u32 pci_base_lo, u32 cpu_base, u32 size, struct mv64x60_cpu2pci_win *offset_tbl) mv64x60_config_cpu2pci_window() argument
/linux-4.1.27/drivers/irqchip/
H A Dirq-gic.c60 union gic_base cpu_base; member in struct:gic_chip_data
109 return data->get_base(&data->cpu_base); gic_data_cpu_base()
119 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
268 void __iomem *cpu_base = gic_data_cpu_base(gic); gic_handle_irq() local
271 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); gic_handle_irq()
279 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); gic_handle_irq()
367 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); gic_cpu_if_up() local
373 bypass = readl(cpu_base + GIC_CPU_CTRL); gic_cpu_if_up()
376 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); gic_cpu_if_up()
433 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); gic_cpu_if_down() local
436 val = readl(cpu_base + GIC_CPU_CTRL); gic_cpu_if_down()
438 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); gic_cpu_if_down()
524 void __iomem *cpu_base; gic_cpu_save() local
530 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); gic_cpu_save()
532 if (!dist_base || !cpu_base) gic_cpu_save()
550 void __iomem *cpu_base; gic_cpu_restore() local
556 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); gic_cpu_restore()
558 if (!dist_base || !cpu_base) gic_cpu_restore()
573 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); gic_cpu_restore()
896 void __iomem *dist_base, void __iomem *cpu_base, gic_init_bases()
911 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); gic_init_bases()
913 !gic->cpu_base.percpu_base)) { gic_init_bases()
915 free_percpu(gic->cpu_base.percpu_base); gic_init_bases()
924 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; for_each_possible_cpu()
935 gic->cpu_base.common_base = cpu_base;
1009 void __iomem *cpu_base; gic_of_init() local
1020 cpu_base = of_iomap(node, 1); gic_of_init()
1021 WARN(!cpu_base, "unable to map gic cpu registers\n"); gic_of_init()
1026 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); gic_of_init()
1099 void __iomem *cpu_base, *dist_base; gic_v2_acpi_init() local
1128 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); gic_v2_acpi_init()
1129 if (!cpu_base) { gic_v2_acpi_init()
1137 iounmap(cpu_base); gic_v2_acpi_init()
1146 gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); gic_v2_acpi_init()
895 gic_init_bases(unsigned int gic_nr, int irq_start, void __iomem *dist_base, void __iomem *cpu_base, u32 percpu_offset, struct device_node *node) gic_init_bases() argument
H A Dirq-hip04.c57 void __iomem *cpu_base; member in struct:hip04_irq_data
83 return hip04_data->cpu_base; hip04_cpu_base()
175 void __iomem *cpu_base = hip04_data.cpu_base; hip04_handle_irq() local
178 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); hip04_handle_irq()
186 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); hip04_handle_irq()
250 void __iomem *base = intc->cpu_base; hip04_irq_cpu_init()
379 hip04_data.cpu_base = of_iomap(node, 1); hip04_of_init()
380 WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n"); hip04_of_init()
/linux-4.1.27/arch/mips/ar7/
H A Dclock.c340 int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv; tnetd7200_init_clocks() local
344 cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr); tnetd7200_init_clocks()
360 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, tnetd7200_init_clocks()
363 ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv; tnetd7200_init_clocks()
364 tnetd7200_set_clock(cpu_base, &clocks->cpu, tnetd7200_init_clocks()
373 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, tnetd7200_init_clocks()
375 cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul) tnetd7200_init_clocks()
377 tnetd7200_set_clock(cpu_base, &clocks->cpu, tnetd7200_init_clocks()
/linux-4.1.27/include/linux/
H A Dhrtimer.h78 * All state transitions are protected by cpu_base->lock.
135 * @cpu_base: per cpu clock base
146 struct hrtimer_cpu_base *cpu_base; member in struct:hrtimer_clock_base
280 return timer->base->cpu_base->hres_active; hrtimer_is_hres_active()
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A Dbgmac.c132 dma_desc = &ring->cpu_base[i]; bgmac_dma_tx_add_buf()
225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); bgmac_dma_tx_add()
264 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); bgmac_dma_tx_free()
382 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; bgmac_dma_rx_setup_desc()
520 struct bgmac_dma_desc *dma_desc = ring->cpu_base; bgmac_dma_tx_ring_free()
569 if (!ring->cpu_base) bgmac_dma_ring_desc_free()
574 dma_free_coherent(dma_dev, size, ring->cpu_base, bgmac_dma_ring_desc_free()
626 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, bgmac_dma_alloc()
629 if (!ring->cpu_base) { bgmac_dma_alloc()
651 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, bgmac_dma_alloc()
654 if (!ring->cpu_base) { bgmac_dma_alloc()
H A Dbgmac.h422 struct bgmac_dma_desc *cpu_base; member in struct:bgmac_dma_ring
H A Dtg3.c3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) tg3_pause_cpu() argument
3591 tw32(cpu_base + CPU_STATE, 0xffffffff); tg3_pause_cpu()
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); tg3_pause_cpu()
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) tg3_pause_cpu()
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) tg3_resume_cpu() argument
3623 tw32(cpu_base + CPU_STATE, 0xffffffff); tg3_resume_cpu()
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000); tg3_resume_cpu()
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) tg3_halt_cpu() argument
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); tg3_halt_cpu()
3646 if (cpu_base == RX_CPU_BASE) { tg3_halt_cpu()
3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX"); tg3_halt_cpu()
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, tg3_load_firmware_cpu() argument
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { tg3_load_firmware_cpu()
3724 err = tg3_halt_cpu(tp, cpu_base); tg3_load_firmware_cpu()
3732 tw32(cpu_base + CPU_STATE, 0xffffffff); tg3_load_firmware_cpu()
3733 tw32(cpu_base + CPU_MODE, tg3_load_firmware_cpu()
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT); tg3_load_firmware_cpu()
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) tg3_pause_cpu_and_set_pc() argument
3770 tw32(cpu_base + CPU_STATE, 0xffffffff); tg3_pause_cpu_and_set_pc()
3771 tw32_f(cpu_base + CPU_PC, pc); tg3_pause_cpu_and_set_pc()
3774 if (tr32(cpu_base + CPU_PC) == pc) tg3_pause_cpu_and_set_pc()
3776 tw32(cpu_base + CPU_STATE, 0xffffffff); tg3_pause_cpu_and_set_pc()
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); tg3_pause_cpu_and_set_pc()
3778 tw32_f(cpu_base + CPU_PC, pc); tg3_pause_cpu_and_set_pc()
3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; tg3_load_tso_firmware() local
3920 cpu_base = RX_CPU_BASE; tg3_load_tso_firmware()
3923 cpu_base = TX_CPU_BASE; tg3_load_tso_firmware()
3928 err = tg3_load_firmware_cpu(tp, cpu_base, tg3_load_tso_firmware()
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base, tg3_load_tso_firmware()
3940 __func__, tr32(cpu_base + CPU_PC), tg3_load_tso_firmware()
3945 tg3_resume_cpu(tp, cpu_base); tg3_load_tso_firmware()
/linux-4.1.27/drivers/block/
H A DDAC960.c230 loaf->cpu_free = loaf->cpu_base = cpu_addr; init_dma_loaf()
243 BUG_ON(cpu_end > loaf->cpu_base + loaf->length); slice_dma_loaf()
252 if (loaf_handle->cpu_base != NULL) free_dma_loaf()
254 loaf_handle->cpu_base, loaf_handle->dma_base); free_dma_loaf()
H A DDAC960.h112 void *cpu_base; member in struct:dma_loaf

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