Searched refs:control_1 (Results 1 – 3 of 3) sorted by relevance
169 unsigned short control_1; /* Mirror of CONTROL_1 register */ member272 dev_private->control_1 &= 0xFFFC; in me_ai_insn_read()273 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1); in me_ai_insn_read()294 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC; in me_ai_insn_read()295 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1); in me_ai_insn_read()311 dev_private->control_1 &= 0xFFFC; in me_ai_insn_read()312 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1); in me_ai_insn_read()448 dev_private->control_1 = 0; in me_reset()
1279 u64 control_1; member1423 u64 control_1; member1521 rxdp->control_1 &= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK; in vxge_hw_ring_rxd_1b_set()1522 rxdp->control_1 |= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size); in vxge_hw_ring_rxd_1b_set()1548 (u32)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1); in vxge_hw_ring_rxd_1b_get()1590 (u32)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp->control_1); in vxge_hw_ring_rxd_1b_info_get()1600 (u32)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1); in vxge_hw_ring_rxd_1b_info_get()1637 txdp->control_1 |= cksum_bits; in vxge_hw_fifo_txdl_cksum_set_bits()1674 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_ENABLE; in vxge_hw_fifo_txdl_vlan_set()1675 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag); in vxge_hw_fifo_txdl_vlan_set()
1151 rxdp->control_0 = rxdp->control_1 = 0; in vxge_hw_ring_rxd_reserve()1484 txdp->control_0 = txdp->control_1 = 0; in vxge_hw_fifo_txdl_reserve()1522 txdp->control_0 = txdp->control_1 = 0; in vxge_hw_fifo_txdl_buffer_set()1526 txdp->control_1 |= fifo->interrupt_type; in vxge_hw_fifo_txdl_buffer_set()1527 txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_NUMBER( in vxge_hw_fifo_txdl_buffer_set()