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Searched refs:clksel (Results 1 – 12 of 12) sorted by relevance

/linux-4.1.27/drivers/mmc/host/
Ddw_mmc-exynos.c133 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
137 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
139 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
141 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
145 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
147 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
181 u32 clksel; in dw_mci_exynos_resume_noirq() local
185 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_resume_noirq()
187 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_resume_noirq()
189 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { in dw_mci_exynos_resume_noirq()
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/linux-4.1.27/drivers/clk/
Dclk-qoriq.c37 u32 clksel; in cmux_set_parent() local
39 clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll; in cmux_set_parent()
41 clksel += 8; in cmux_set_parent()
42 clksel = (clksel & 0xf) << CLKSEL_SHIFT; in cmux_set_parent()
43 iowrite32be(clksel, clk->reg); in cmux_set_parent()
51 u32 clksel; in cmux_get_parent() local
53 clksel = ioread32be(clk->reg); in cmux_get_parent()
54 clksel = (clksel >> CLKSEL_SHIFT) & 0xf; in cmux_get_parent()
56 clksel -= 8; in cmux_get_parent()
57 clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4; in cmux_get_parent()
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/linux-4.1.27/arch/arm/mach-omap2/
Dclkt_clksel.c61 static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, in _get_clksel_by_parent()
64 const struct clksel *clks; in _get_clksel_by_parent()
69 for (clks = clk->clksel; clks->parent; clks++) in _get_clksel_by_parent()
121 const struct clksel *clks; in _clksel_to_divisor()
162 const struct clksel *clks; in _divisor_to_clksel()
204 if (!clk->clksel || !clk->clksel_mask) in _read_divisor()
233 const struct clksel *clks; in omap2_clksel_round_rate_div()
244 if (!clk->clksel || !clk->clksel_mask) in omap2_clksel_round_rate_div()
309 const struct clksel *clks; in omap2_clksel_find_parent_index()
320 WARN((!clk->clksel || !clk->clksel_mask), in omap2_clksel_find_parent_index()
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Dclock.h84 .clksel = _clksel, \
103 .clksel = _clksel, \
157 struct clksel { struct
/linux-4.1.27/arch/arm/mach-w90x900/
Dclksel.c41 unsigned int clksel, offset; in clock_source_select() local
43 clksel = __raw_readl(REG_CLKSEL); in clock_source_select()
56 clksel &= ~(0x03 << offset); in clock_source_select()
57 clksel |= (clkval << offset); in clock_source_select()
59 __raw_writel(clksel, REG_CLKSEL); in clock_source_select()
DMakefile8 obj-y += clksel.o dev.o cpu.o
/linux-4.1.27/drivers/clocksource/
Dcadence_ttc_timer.c471 int clksel; in ttc_timer_init() local
498 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
499 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_init()
500 clk_cs = of_clk_get(timer, clksel); in ttc_timer_init()
506 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
507 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_init()
508 clk_ce = of_clk_get(timer, clksel); in ttc_timer_init()
/linux-4.1.27/drivers/clk/rockchip/
Dclk-cpu.c111 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
113 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
117 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
118 writel(clksel->val , cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
/linux-4.1.27/arch/mips/ralink/
Drt3883.c80 u32 clksel; in ralink_clk_init() local
84 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & in ralink_clk_init()
88 switch (clksel) { in ralink_clk_init()
/linux-4.1.27/arch/arm/mach-imx/
Dmach-imx6q.c189 u32 clksel; in imx6q_1588_init() local
214 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
221 clksel); in imx6q_1588_init()
/linux-4.1.27/include/linux/clk/
Dti.h147 const struct clksel *clksel; member
/linux-4.1.27/drivers/mfd/
Dasic3.c390 unsigned long clksel = 0; in asic3_irq_probe() local
400 clksel |= CLOCK_SEL_CX; in asic3_irq_probe()
402 clksel); in asic3_irq_probe()
961 unsigned long clksel; in asic3_probe() local
992 clksel = 0; in asic3_probe()
993 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()