Searched refs:cfgcr1 (Results 1 – 4 of 4) sorted by relevance
1151 uint32_t ctrl1, cfgcr1, cfgcr2; in skl_ddi_pll_select() local1167 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | in skl_ddi_pll_select()1192 cfgcr1 = cfgcr2 = 0; in skl_ddi_pll_select()1197 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_pll_select()1852 u32 ctl, cfgcr1, cfgcr2; member1860 .cfgcr1 = DPLL1_CFGCR1,1866 .cfgcr1 = DPLL2_CFGCR1,1872 .cfgcr1 = DPLL3_CFGCR1,1896 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); in skl_ddi_pll_enable()1898 POSTING_READ(regs[pll->id].cfgcr1); in skl_ddi_pll_enable()[all …]
305 uint32_t cfgcr1, cfgcr2; member
1087 pipe_config->dpll_hw_state.cfgcr1 = 0; in skl_edp_set_pll_config()
11113 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()