1151 	uint32_t ctrl1, cfgcr1, cfgcr2;  in skl_ddi_pll_select()  local
1167 		cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |  in skl_ddi_pll_select()
1192 		cfgcr1 = cfgcr2 = 0;  in skl_ddi_pll_select()
1197 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;  in skl_ddi_pll_select()
1852 	u32 ctl, cfgcr1, cfgcr2;  member
1860 		.cfgcr1 = DPLL1_CFGCR1,
1866 		.cfgcr1 = DPLL2_CFGCR1,
1872 		.cfgcr1 = DPLL3_CFGCR1,
1896 	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);  in skl_ddi_pll_enable()
1898 	POSTING_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_enable()
1943 		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_get_hw_state()