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Searched refs:bfin_write16 (Results 1 – 33 of 33) sorted by relevance

/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
DcdefBF548.h19 #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
21 #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
23 #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
25 #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
27 #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
29 #define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
31 #define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
33 #define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
35 #define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
37 #define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
[all …]
DcdefBF544.h18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
34 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
45 #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
47 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
54 #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
56 #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
58 #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
60 #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
62 #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
[all …]
DcdefBF542.h18 #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
20 #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
22 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
24 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
26 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
28 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
30 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
32 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
34 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
36 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
[all …]
DcdefBF547.h18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
34 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
45 #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
47 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
54 #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
56 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
58 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
60 #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
66 #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
[all …]
DcdefBF54x_base.h18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
21 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
23 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
33 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
35 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
93 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
104 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
106 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
108 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
112 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
[all …]
DcdefBF549.h19 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
33 #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
35 #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
37 #define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
39 #define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
43 #define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
106 #define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
110 #define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
119 #define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
123 #define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
[all …]
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
DcdefBF525.h16 #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
18 #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
20 #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
22 #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
24 #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
26 #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
28 #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
30 #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
32 #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
34 #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
[all …]
DcdefBF522.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
25 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
27 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
74 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
85 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
87 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
89 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
93 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
[all …]
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
DcdefBF534.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
45 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
55 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
57 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
59 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
63 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
[all …]
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
DcdefBF538.h14 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
17 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
19 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
61 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
69 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
71 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
73 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
77 #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
[all …]
DcdefBF539.h14 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
30 #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
32 #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
34 #define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
36 #define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
40 #define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
94 #define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
98 #define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
104 #define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
108 #define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
[all …]
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
DcdefBF561.h17 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
20 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
22 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
27 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
29 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
31 #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
63 #define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
65 #define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
67 #define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
98 #define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
[all …]
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
DcdefBF512.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
25 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
27 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
74 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
85 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
87 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
89 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
93 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
[all …]
DcdefBF514.h16 #define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
18 #define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
22 #define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
24 #define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
36 #define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
38 #define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
40 #define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
44 #define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
50 #define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
52 #define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
[all …]
DcdefBF518.h16 #define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
18 #define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
20 #define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
48 #define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
DcdefBF532.h13 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
15 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
43 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
53 #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
55 #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
57 #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
61 #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
[all …]
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
DcdefBF60x_base.h44 #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
199 #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
207 #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
215 #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
223 #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
231 #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
239 #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
247 #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
255 #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
2427 #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
[all …]
/linux-4.1.27/drivers/tty/serial/
Dbfin_sport_uart.h62 #define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
63 #define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
64 #define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
65 #define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
66 #define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
67 #define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
68 #define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
69 #define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
70 #define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
71 #define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
[all …]
/linux-4.1.27/drivers/media/platform/blackfin/
Dppi.c65 bfin_write16(&reg->status, 0xff00); in ppi_irq_err()
76 bfin_write16(&reg->status, 0xffff); in ppi_irq_err()
142 bfin_write16(&reg->control, ppi->ppi_control); in ppi_start()
175 bfin_write16(&reg->control, ppi->ppi_control); in ppi_stop()
245 bfin_write16(&reg->control, ppi->ppi_control); in ppi_set_params()
246 bfin_write16(&reg->count, samples_per_line - 1); in ppi_set_params()
247 bfin_write16(&reg->frame, params->frame); in ppi_set_params()
259 bfin_write16(&reg->line, samples_per_line); in ppi_set_params()
260 bfin_write16(&reg->frame, params->frame); in ppi_set_params()
261 bfin_write16(&reg->hdelay, hdelay); in ppi_set_params()
[all …]
/linux-4.1.27/arch/blackfin/include/asm/
Dbfin_serial.h338 #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
339 #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
340 #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
346 #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
347 #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
348 #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
352 #define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
354 #define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
359 #define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
361 #define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
[all …]
Dbfin_twi.h18 { bfin_write16(&iface->regs_base->reg, v); }
68 bfin_write16(&iface->regs_base->fifo_ctl, v); in write_FIFO_CTL()
80 bfin_write16(&iface->regs_base->control, v); in write_CONTROL()
Dio.h19 #define __raw_writew(val, addr) bfin_write16(addr, val)
Ddef_LPBlackfin.h50 #define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) macro
64 case 2: bfin_write16(addr, val); break; \
Ddma.h65 #define DMA_MMR_WRITE bfin_write16
/linux-4.1.27/drivers/usb/musb/
Dblackfin.c58 bfin_write16(addr + offset, (u16)data); in bfin_writeb()
63 bfin_write16(addr + offset, data); in bfin_writew()
68 bfin_write16(addr + offset, (u16)data); in bfin_writel()
98 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); in bfin_write_fifo()
102 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); in bfin_write_fifo()
106 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); in bfin_write_fifo()
107 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); in bfin_write_fifo()
112 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); in bfin_write_fifo()
124 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); in bfin_write_fifo()
152 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); in bfin_read_fifo()
[all …]
/linux-4.1.27/drivers/ata/
Dpata_bf54x.c80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
90 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
94 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
98 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
102 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
106 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
114 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
126 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
130 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
[all …]
/linux-4.1.27/arch/blackfin/mach-common/
Dclocks-init.c93 bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); in init_clocks()
100 bfin_write16(PLL_CTL, PLL_CTL_VAL); in init_clocks()
/linux-4.1.27/arch/blackfin/include/mach-common/
Dpll.h64 bfin_write16(addr, val); in _bfin_write_pll_relock()
/linux-4.1.27/arch/blackfin/mm/
Dmaccess.c71 bfin_write16(dst, mmr); in probe_kernel_write()
/linux-4.1.27/arch/blackfin/mach-bf538/
Dext-gpio.c19 { bfin_write16(port + off, v); }
/linux-4.1.27/arch/blackfin/kernel/
Dtime-ts.c70 bfin_write16(TIMER_DATA_IMSK, 0); in setup_gptimer0()
Dgptimers.c311 bfin_write16(TIMER_DATA_IMSK, imask); in enable_gptimers()
Ddebug-mmrs.c448 bfin_write16(mmr, val); in sport_set()