Searched refs:__clk_get_flags (Results 1 – 18 of 18) sorted by relevance
44 if (__clk_get_flags(clk) & CLK_IS_BASIC) { in of_ti_clockdomain_setup()
247 if (__clk_get_flags(clk) & CLK_IS_BASIC) { in ti_clk_register_clk()
158 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { in ti_clk_divider_bestdiv()
599 if (__clk_get_flags(clk) & CLK_IS_BASIC) in omap2_init_clk_hw_omap_clocks()660 if (__clk_get_flags(clk) & CLK_IS_BASIC) in omap2_clk_deny_idle()679 if (__clk_get_flags(clk) & CLK_IS_BASIC) in omap2_clk_allow_idle()
714 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); in omap3_find_clkoutx2_dpll()803 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in omap3_clkoutx2_round_rate()
694 if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) in _get_clkdm()
44 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in clk_factor_round_rate()
86 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) { in clk_composite_determine_rate()
288 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { in clk_divider_bestdiv()
666 if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { in si5351_msynth_round_rate()1004 if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { in si5351_clkout_round_rate()
312 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in cdce706_divider_round_rate()
682 unsigned long __clk_get_flags(struct clk *clk) in __clk_get_flags() function686 EXPORT_SYMBOL_GPL(__clk_get_flags);
98 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT) in clk_factors_determine_rate()
137 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT) in sun6i_ahb1_clk_determine_rate()
111 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in flexgen_round_rate()
574 unsigned long __clk_get_flags(struct clk *clk);
196 clk_flags = __clk_get_flags(hw->clk); in _freq_tbl_determine_rate()
425 clk_flags = __clk_get_flags(hw->clk); in _freq_tbl_determine_rate()