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Searched refs:_MASKED_BIT_DISABLE (Results 1 – 6 of 6) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_pm.c324 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); in intel_set_memory_cxsr()
328 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); in intel_set_memory_cxsr()
5892 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ironlake_init_clock_gating()
5963 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in gen6_init_clock_gating()
5979 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); in gen6_init_clock_gating()
6153 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in haswell_init_clock_gating()
6157 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); in haswell_init_clock_gating()
6212 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ivybridge_init_clock_gating()
6257 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); in ivybridge_init_clock_gating()
6319 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in valleyview_init_clock_gating()
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Dintel_ringbuffer.c559 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); in stop_ring()
790 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
1095 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); in init_render_ring()
2330 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); in gen6_bsd_ring_write_tail()
Dintel_uncore.c1023 d->val_reset = _MASKED_BIT_DISABLE(0xffff); in fw_domain_init()
1025 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); in fw_domain_init()
Di915_gem_context.c565 intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in mi_set_context()
Dintel_lrc.c790 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); in intel_logical_ring_stop()
1146 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | in gen8_init_common_ring()
Di915_reg.h47 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) macro