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Searched refs:WREG8 (Results 1 – 10 of 10) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/mgag200/
Dmgag200_mode.c39 WREG8(DAC_INDEX + MGA1064_INDEX, 0); in mga_crtc_load_lut()
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); in mga_crtc_load_lut()
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); in mga_crtc_load_lut()
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); in mga_crtc_load_lut()
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]); in mga_crtc_load_lut()
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); in mga_crtc_load_lut()
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]); in mga_crtc_load_lut()
203 WREG8(MGAREG_CRTC_INDEX, 0x1e); in mga_g200wb_set_plls()
206 WREG8(MGAREG_CRTC_DATA, tmp+1); in mga_g200wb_set_plls()
210 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mga_g200wb_set_plls()
[all …]
Dmgag200_cursor.c23 WREG8(MGA_CURPOSXL, 0); in mga_hide_cursor()
24 WREG8(MGA_CURPOSXH, 0); in mga_hide_cursor()
58 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
59 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
64 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
65 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
75 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
76 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
81 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
82 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
[all …]
Dmgag200_drv.h45 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) macro
55 WREG8(ATTR_INDEX, reg); \
56 WREG8(ATTR_DATA, v); \
61 WREG8(MGAREG_SEQ_INDEX, reg); \
62 WREG8(MGAREG_SEQ_DATA, v); \
67 WREG8(MGAREG_CRTC_INDEX, reg); \
68 WREG8(MGAREG_CRTC_DATA, v); \
74 WREG8(MGAREG_CRTCEXT_INDEX, reg); \
75 WREG8(MGAREG_CRTCEXT_DATA, v); \
83 WREG8(GFX_INDEX, reg); \
[all …]
Dmgag200_i2c.c37 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); in mga_i2c_read_gpio()
45 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); in mga_i2c_set_gpio()
/linux-4.1.27/drivers/gpu/drm/cirrus/
Dcirrus_drv.h39 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg)) macro
48 WREG8(SEQ_INDEX, reg); \
49 WREG8(SEQ_DATA, v); \
57 WREG8(CRT_INDEX, reg); \
58 WREG8(CRT_DATA, v); \
66 WREG8(GFX_INDEX, reg); \
67 WREG8(GFX_DATA, v); \
83 WREG8(VGA_DAC_MASK, v); \
Dcirrus_mode.c46 WREG8(PALETTE_INDEX, i); in cirrus_crtc_load_lut()
47 WREG8(PALETTE_DATA, cirrus_crtc->lut_r[i]); in cirrus_crtc_load_lut()
48 WREG8(PALETTE_DATA, cirrus_crtc->lut_g[i]); in cirrus_crtc_load_lut()
49 WREG8(PALETTE_DATA, cirrus_crtc->lut_b[i]); in cirrus_crtc_load_lut()
85 WREG8(SEQ_INDEX, 0x1); in cirrus_crtc_dpms()
89 WREG8(GFX_INDEX, 0xe); in cirrus_crtc_dpms()
116 WREG8(CRT_INDEX, 0x1b); in cirrus_set_start_address()
122 WREG8(CRT_INDEX, 0x1d); in cirrus_set_start_address()
268 WREG8(SEQ_INDEX, 0x7); in cirrus_crtc_mode_set()
/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon_legacy_tv.c286 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
288 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); in radeon_wait_pll_lock()
Dr100.c2888 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2901 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
3769 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3800 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3813 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); in r100_vga_render_disable()
Dradeon_display.c62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); in avivo_crtc_load_lut()
185 WREG8(RADEON_PALETTE_INDEX, 0); in legacy_crtc_load_lut()
Dradeon.h2536 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) macro