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Searched refs:SOC_RESET_CONTROL_ADDRESS (Results 1 – 2 of 2) sorted by relevance

/linux-4.1.27/drivers/net/wireless/ath/ath10k/
Dpci.c1765 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
1766 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_si0()
1768 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
1772 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
1773 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_si0()
1775 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_si0()
1787 SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_cpu()
1788 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_cpu()
1797 SOC_RESET_CONTROL_ADDRESS); in ath10k_pci_warm_reset_ce()
1799 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, in ath10k_pci_warm_reset_ce()
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Dhw.h333 #define SOC_RESET_CONTROL_ADDRESS 0x00000000 macro