/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/ |
H A D | exynos7-clk.h | 79 #define SCLK_UART3 6 macro
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H A D | rk3188-cru-common.h | 29 #define SCLK_UART3 67 macro
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H A D | s5pv210.h | 197 #define SCLK_UART3 172 macro
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H A D | rk3288-cru.h | 41 #define SCLK_UART3 80 macro
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/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
H A D | exynos7-clk.h | 79 #define SCLK_UART3 6 macro
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H A D | rk3188-cru-common.h | 29 #define SCLK_UART3 67 macro
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H A D | s5pv210.h | 197 #define SCLK_UART3 172 macro
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H A D | rk3288-cru.h | 41 #define SCLK_UART3 80 macro
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/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/ |
H A D | exynos7-clk.h | 79 #define SCLK_UART3 6 macro
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H A D | rk3188-cru-common.h | 29 #define SCLK_UART3 67 macro
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H A D | s5pv210.h | 197 #define SCLK_UART3 172 macro
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H A D | rk3288-cru.h | 41 #define SCLK_UART3 80 macro
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/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/ |
H A D | exynos7-clk.h | 79 #define SCLK_UART3 6 macro
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H A D | rk3188-cru-common.h | 29 #define SCLK_UART3 67 macro
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H A D | s5pv210.h | 197 #define SCLK_UART3 172 macro
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H A D | rk3288-cru.h | 41 #define SCLK_UART3 80 macro
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/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/ |
H A D | exynos7-clk.h | 79 #define SCLK_UART3 6 macro
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H A D | rk3188-cru-common.h | 29 #define SCLK_UART3 67 macro
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H A D | s5pv210.h | 197 #define SCLK_UART3 172 macro
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H A D | rk3288-cru.h | 41 #define SCLK_UART3 80 macro
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/linux-4.1.27/include/dt-bindings/clock/ |
H A D | exynos7-clk.h | 79 #define SCLK_UART3 6 macro
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H A D | rk3188-cru-common.h | 29 #define SCLK_UART3 67 macro
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H A D | s5pv210.h | 197 #define SCLK_UART3 172 macro
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H A D | rk3288-cru.h | 41 #define SCLK_UART3 80 macro
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/linux-4.1.27/drivers/clk/samsung/ |
H A D | clk-s5pv210.c | 718 GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
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H A D | clk-exynos7.c | 694 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
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/linux-4.1.27/drivers/clk/rockchip/ |
H A D | clk-rk3188.c | 409 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
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H A D | clk-rk3288.c | 567 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
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