Searched refs:RING_PP_DIR_DCLV (Results 1 – 3 of 3) sorted by relevance
970 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); in hsw_mm_switch()985 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); in vgpu_mm_switch()1005 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); in gen7_mm_switch()1029 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); in gen6_mm_switch()1032 POSTING_READ(RING_PP_DIR_DCLV(ring)); in gen6_mm_switch()
2189 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); in gen6_ppgtt_info()
136 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) macro