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Searched refs:RADEON_NUM_RINGS (Results 1 – 10 of 10) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon_fence.c462 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_fence_any_seq_signaled()
497 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_fence_wait_seq_timeout()
518 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_fence_wait_seq_timeout()
542 uint64_t seq[RADEON_NUM_RINGS] = {}; in radeon_fence_wait()
583 uint64_t seq[RADEON_NUM_RINGS]; in radeon_fence_wait_any()
587 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_fence_wait_any()
621 uint64_t seq[RADEON_NUM_RINGS] = {}; in radeon_fence_wait_next()
648 uint64_t seq[RADEON_NUM_RINGS] = {}; in radeon_fence_wait_empty()
781 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_fence_note_sync()
858 for (i = 0; i < RADEON_NUM_RINGS; ++i) in radeon_fence_driver_init_ring()
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Dradeon_sa.c63 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_sa_bo_manager_init()
230 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_sa_event()
267 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_sa_bo_next_hole()
317 struct radeon_fence *fences[RADEON_NUM_RINGS]; in radeon_sa_bo_new()
318 unsigned tries[RADEON_NUM_RINGS]; in radeon_sa_bo_new()
335 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_sa_bo_new()
352 for (i = 0; i < RADEON_NUM_RINGS; ++i) in radeon_sa_bo_new()
357 for (i = 0; i < RADEON_NUM_RINGS; ++i) in radeon_sa_bo_new()
Dradeon_sync.c49 for (i = 0; i < RADEON_NUM_RINGS; ++i) in radeon_sync_create()
144 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_sync_rings()
Dradeon_device.c1291 for (i = 0; i < RADEON_NUM_RINGS; i++) { in radeon_device_init()
1294 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); in radeon_device_init()
1607 for (i = 0; i < RADEON_NUM_RINGS; i++) { in radeon_suspend_kms()
1760 unsigned ring_sizes[RADEON_NUM_RINGS]; in radeon_gpu_reset()
1761 uint32_t *ring_data[RADEON_NUM_RINGS]; in radeon_gpu_reset()
1781 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_gpu_reset()
1799 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_gpu_reset()
Dradeon_irq_kms.c122 for (i = 0; i < RADEON_NUM_RINGS; i++) in radeon_driver_irq_preinstall_kms()
170 for (i = 0; i < RADEON_NUM_RINGS; i++) in radeon_driver_irq_uninstall_kms()
Dradeon_vm.c180 struct radeon_fence *best[RADEON_NUM_RINGS] = {}; in radeon_vm_grab_id()
1004 for (i = 0; i < RADEON_NUM_RINGS; ++i) in radeon_vm_bo_update()
1179 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_vm_init()
1256 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_vm_fini()
Dradeon_ib.c262 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_ib_ring_tests()
Dradeon.h150 #define RADEON_NUM_RINGS 8 macro
360 uint64_t sync_seq[RADEON_NUM_RINGS];
544 struct list_head flist[RADEON_NUM_RINGS];
611 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
810 atomic_t ring_int[RADEON_NUM_RINGS];
955 struct radeon_vm_id ids[RADEON_NUM_RINGS];
1892 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
2377 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2381 struct radeon_ring ring[RADEON_NUM_RINGS];
Dradeon_test.c524 for (i = 1; i < RADEON_NUM_RINGS; ++i) { in radeon_test_syncing()
Dradeon_pm.c261 for (i = 0; i < RADEON_NUM_RINGS; i++) { in radeon_pm_set_clocks()
1086 for (i = 0; i < RADEON_NUM_RINGS; i++) { in radeon_dpm_change_power_state_locked()
1799 for (i = 0; i < RADEON_NUM_RINGS; ++i) { in radeon_dynpm_idle_work_handler()