| /linux-4.1.27/drivers/gpu/drm/gma500/ |
| H A D | oaktrail_device.c | 272 PSB_WVDC32(0, PP_CONTROL); oaktrail_save_display_registers()
279 PSB_WVDC32(0x58000000, DSPACNTR); oaktrail_save_display_registers()
281 PSB_WVDC32(0, DSPASURF); oaktrail_save_display_registers()
287 PSB_WVDC32(0x0, PIPEACONF); oaktrail_save_display_registers()
292 PSB_WVDC32(0, MRST_DPLL_A); oaktrail_save_display_registers()
312 PSB_WVDC32(regs->psb.saveDSPARB, DSPARB); oaktrail_restore_display_registers()
313 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1); oaktrail_restore_display_registers()
314 PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2); oaktrail_restore_display_registers()
315 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3); oaktrail_restore_display_registers()
316 PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4); oaktrail_restore_display_registers()
317 PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5); oaktrail_restore_display_registers()
318 PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6); oaktrail_restore_display_registers()
319 PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT); oaktrail_restore_display_registers()
322 PSB_WVDC32(0x80000000, VGACNTRL); oaktrail_restore_display_registers()
325 PSB_WVDC32(p->fp0, MRST_FPA0); oaktrail_restore_display_registers()
326 PSB_WVDC32(p->fp1, MRST_FPA1); oaktrail_restore_display_registers()
329 PSB_WVDC32(p->dpll, MRST_DPLL_A); oaktrail_restore_display_registers()
333 PSB_WVDC32(p->htotal, HTOTAL_A); oaktrail_restore_display_registers()
334 PSB_WVDC32(p->hblank, HBLANK_A); oaktrail_restore_display_registers()
335 PSB_WVDC32(p->hsync, HSYNC_A); oaktrail_restore_display_registers()
336 PSB_WVDC32(p->vtotal, VTOTAL_A); oaktrail_restore_display_registers()
337 PSB_WVDC32(p->vblank, VBLANK_A); oaktrail_restore_display_registers()
338 PSB_WVDC32(p->vsync, VSYNC_A); oaktrail_restore_display_registers()
339 PSB_WVDC32(p->src, PIPEASRC); oaktrail_restore_display_registers()
340 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A); oaktrail_restore_display_registers()
343 PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE); oaktrail_restore_display_registers()
347 PSB_WVDC32(p->conf, PIPEACONF); oaktrail_restore_display_registers()
350 PSB_WVDC32(p->linoff, DSPALINOFF); oaktrail_restore_display_registers()
351 PSB_WVDC32(p->stride, DSPASTRIDE); oaktrail_restore_display_registers()
352 PSB_WVDC32(p->tileoff, DSPATILEOFF); oaktrail_restore_display_registers()
355 PSB_WVDC32(p->cntr, DSPACNTR); oaktrail_restore_display_registers()
356 PSB_WVDC32(p->surf, DSPASURF); oaktrail_restore_display_registers()
359 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR); oaktrail_restore_display_registers()
360 PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS); oaktrail_restore_display_registers()
361 PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE); oaktrail_restore_display_registers()
365 PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2)); oaktrail_restore_display_registers()
371 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); oaktrail_restore_display_registers()
372 PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/ oaktrail_restore_display_registers()
373 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL); oaktrail_restore_display_registers()
374 PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); oaktrail_restore_display_registers()
375 PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); oaktrail_restore_display_registers()
376 PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL); oaktrail_restore_display_registers()
377 PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON); oaktrail_restore_display_registers()
378 PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF); oaktrail_restore_display_registers()
379 PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE); oaktrail_restore_display_registers()
380 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); oaktrail_restore_display_registers()
394 PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD); oaktrail_restore_display_registers()
395 PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0); oaktrail_restore_display_registers()
396 PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1); oaktrail_restore_display_registers()
397 PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2); oaktrail_restore_display_registers()
398 PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3); oaktrail_restore_display_registers()
399 PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4); oaktrail_restore_display_registers()
400 PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5); oaktrail_restore_display_registers()
403 PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG, oaktrail_restore_display_registers()
405 PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG, oaktrail_restore_display_registers()
407 PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); oaktrail_restore_display_registers()
|
| H A D | mdfld_device.c | 280 PSB_WVDC32(0x80000000, VGACNTRL); mdfld_restore_display_registers()
283 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); mdfld_restore_display_registers()
286 PSB_WVDC32(pipe->fp0, map->fp0); mdfld_restore_display_registers()
297 PSB_WVDC32(dpll, map->dpll); mdfld_restore_display_registers()
302 PSB_WVDC32(pipe->fp0, map->fp0); mdfld_restore_display_registers()
303 PSB_WVDC32(dpll_val, map->dpll); mdfld_restore_display_registers()
308 PSB_WVDC32(dpll_val, map->dpll); mdfld_restore_display_registers()
326 PSB_WVDC32(pipe->htotal, map->htotal); mdfld_restore_display_registers()
327 PSB_WVDC32(pipe->hblank, map->hblank); mdfld_restore_display_registers()
328 PSB_WVDC32(pipe->hsync, map->hsync); mdfld_restore_display_registers()
329 PSB_WVDC32(pipe->vtotal, map->vtotal); mdfld_restore_display_registers()
330 PSB_WVDC32(pipe->vblank, map->vblank); mdfld_restore_display_registers()
331 PSB_WVDC32(pipe->vsync, map->vsync); mdfld_restore_display_registers()
332 PSB_WVDC32(pipe->src, map->src); mdfld_restore_display_registers()
333 PSB_WVDC32(pipe->status, map->status); mdfld_restore_display_registers()
336 PSB_WVDC32(pipe->stride, map->stride); mdfld_restore_display_registers()
337 PSB_WVDC32(pipe->linoff, map->linoff); mdfld_restore_display_registers()
338 PSB_WVDC32(pipe->tileoff, map->tileoff); mdfld_restore_display_registers()
339 PSB_WVDC32(pipe->size, map->size); mdfld_restore_display_registers()
340 PSB_WVDC32(pipe->pos, map->pos); mdfld_restore_display_registers()
341 PSB_WVDC32(pipe->surf, map->surf); mdfld_restore_display_registers()
347 PSB_WVDC32(pipe->palette[i], map->palette + (i << 2)); mdfld_restore_display_registers()
349 PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL); mdfld_restore_display_registers()
350 PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); mdfld_restore_display_registers()
357 PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); mdfld_restore_display_registers()
363 PSB_WVDC32(mipi_val, mipi_reg); mdfld_restore_display_registers()
375 PSB_WVDC32(pipe->cntr, map->cntr); mdfld_restore_display_registers()
404 PSB_WVDC32(pipe->conf, map->conf); mdfld_restore_display_registers()
409 PSB_WVDC32(pipe->palette[i], map->palette + (i << 2)); mdfld_restore_display_registers()
|
| H A D | psb_irq.c | 95 PSB_WVDC32(writeVal, reg); psb_enable_pipestat()
111 PSB_WVDC32(writeVal, reg); psb_disable_pipestat()
123 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); mid_enable_pipe_event()
124 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); mid_enable_pipe_event()
135 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); mid_disable_pipe_event()
136 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); mid_disable_pipe_event()
169 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); mid_pipe_event_handler()
302 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R); psb_irq_handler()
321 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); psb_irq_preinstall()
322 PSB_WVDC32(0x00000000, PSB_INT_MASK_R); psb_irq_preinstall()
323 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); psb_irq_preinstall()
345 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); psb_irq_preinstall()
362 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); psb_irq_postinstall()
363 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); psb_irq_postinstall()
397 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); psb_irq_uninstall()
413 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); psb_irq_uninstall()
414 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); psb_irq_uninstall()
419 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R); psb_irq_uninstall()
431 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL); psb_irq_turn_on_dpst()
433 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL); psb_irq_turn_on_dpst()
436 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC); psb_irq_turn_on_dpst()
438 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE psb_irq_turn_on_dpst()
446 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR, psb_irq_turn_on_dpst()
449 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE, psb_irq_turn_on_dpst()
480 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL); psb_irq_turn_off_dpst()
486 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE, psb_irq_turn_off_dpst()
540 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); psb_enable_vblank()
541 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); psb_enable_vblank()
566 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); psb_disable_vblank()
567 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); psb_disable_vblank()
|
| H A D | oaktrail_hdmi.c | 814 PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL); oaktrail_hdmi_restore()
815 PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL); oaktrail_hdmi_restore()
816 PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST); oaktrail_hdmi_restore()
817 PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE); oaktrail_hdmi_restore()
818 PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE); oaktrail_hdmi_restore()
822 PSB_WVDC32(pipeb->src, PIPEBSRC); oaktrail_hdmi_restore()
823 PSB_WVDC32(pipeb->htotal, HTOTAL_B); oaktrail_hdmi_restore()
824 PSB_WVDC32(pipeb->hblank, HBLANK_B); oaktrail_hdmi_restore()
825 PSB_WVDC32(pipeb->hsync, HSYNC_B); oaktrail_hdmi_restore()
826 PSB_WVDC32(pipeb->vtotal, VTOTAL_B); oaktrail_hdmi_restore()
827 PSB_WVDC32(pipeb->vblank, VBLANK_B); oaktrail_hdmi_restore()
828 PSB_WVDC32(pipeb->vsync, VSYNC_B); oaktrail_hdmi_restore()
830 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC); oaktrail_hdmi_restore()
831 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B); oaktrail_hdmi_restore()
832 PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B); oaktrail_hdmi_restore()
833 PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B, PCH_HSYNC_B); oaktrail_hdmi_restore()
834 PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B); oaktrail_hdmi_restore()
835 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B); oaktrail_hdmi_restore()
836 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B); oaktrail_hdmi_restore()
838 PSB_WVDC32(pipeb->conf, PIPEBCONF); oaktrail_hdmi_restore()
839 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF); oaktrail_hdmi_restore()
842 PSB_WVDC32(pipeb->linoff, DSPBLINOFF); oaktrail_hdmi_restore()
843 PSB_WVDC32(pipeb->stride, DSPBSTRIDE); oaktrail_hdmi_restore()
844 PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF); oaktrail_hdmi_restore()
845 PSB_WVDC32(pipeb->cntr, DSPBCNTR); oaktrail_hdmi_restore()
846 PSB_WVDC32(pipeb->surf, DSPBSURF); oaktrail_hdmi_restore()
849 PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR); oaktrail_hdmi_restore()
850 PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS); oaktrail_hdmi_restore()
851 PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE); oaktrail_hdmi_restore()
855 PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2)); oaktrail_hdmi_restore()
|
| H A D | psb_device.c | 226 PSB_WVDC32(regs->saveDSPARB, DSPARB); psb_restore_display_registers()
227 PSB_WVDC32(regs->saveDSPFW1, DSPFW1); psb_restore_display_registers()
228 PSB_WVDC32(regs->saveDSPFW2, DSPFW2); psb_restore_display_registers()
229 PSB_WVDC32(regs->saveDSPFW3, DSPFW3); psb_restore_display_registers()
230 PSB_WVDC32(regs->saveDSPFW4, DSPFW4); psb_restore_display_registers()
231 PSB_WVDC32(regs->saveDSPFW5, DSPFW5); psb_restore_display_registers()
232 PSB_WVDC32(regs->saveDSPFW6, DSPFW6); psb_restore_display_registers()
233 PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT); psb_restore_display_registers()
236 PSB_WVDC32(0x80000000, VGACNTRL); psb_restore_display_registers()
|
| H A D | psb_drv.c | 370 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); psb_driver_load()
371 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); psb_driver_load()
372 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R); psb_driver_load()
|
| H A D | power.c | 110 PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); gma_resume_display()
|
| H A D | gtt.c | 407 PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL); psb_gtt_takedown()
439 PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); psb_gtt_init()
|
| H A D | psb_drv.h | 900 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) macro
|