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Searched refs:PIN (Results 1 – 15 of 15) sorted by relevance

/linux-4.1.27/drivers/pinctrl/meson/
Dpinctrl-meson8b.c130 static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
131 static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
132 static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
133 static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
134 static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) };
135 static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
136 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
137 static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0),
138 PIN(GPIOX_7, 0) };
139 static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
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Dpinctrl-meson8.c159 static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
160 static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
161 static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
162 static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
163 static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
164 static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
166 static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) };
167 static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
168 PIN(GPIOX_3, 0) };
169 static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
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Dpinctrl-meson.h158 #define PIN(x, b) (b + x) macro
173 .pins = (const unsigned int[]){ PIN(gpio, b) }, \
209 #define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
/linux-4.1.27/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx27-pinctrl.txt10 setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
12 PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
13 configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
90 For convenience there are macros defined in imx27-pinfunc.h which provide PIN
Dqcom,apq8084-pinctrl.txt57 PIN CONFIGURATION NODES:
Dqcom,msm8960-pinctrl.txt57 PIN CONFIGURATION NODES:
Dqcom,msm8916-pinctrl.txt57 PIN CONFIGURATION NODES:
/linux-4.1.27/Documentation/devicetree/bindings/gpio/
Dgpio-mxs.txt3 The Freescale MXS GPIO controller is part of MXS PIN controller. The
6 As the GPIO controller is embedded in the PIN controller and all the
7 GPIO ports share the same IO space with PIN controller, the GPIO node
/linux-4.1.27/Documentation/arm/Samsung-S3C24XX/
DGPIO.txt93 PIN Numbers
149 Getting and setting the state of a PIN
156 Getting the IRQ number associated with a PIN
/linux-4.1.27/Documentation/arm/Samsung/
DGPIO.txt29 PIN configuration
/linux-4.1.27/arch/avr32/mach-at32ap/include/mach/
Dat32ap700x.h143 #define ATMEL_LCDC(PORT, PIN) (ATMEL_LCDC_##PORT##_##PIN) argument
/linux-4.1.27/Documentation/
Dpinctrl.txt1 PINCTRL (PIN CONTROL) subsystem
17 Definition of PIN CONTROLLER:
23 Definition of PIN:
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
32 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
480 - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
493 - The combination of a FUNCTION and a PIN GROUP determine a certain function
507 - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
535 - PINS for a certain FUNCTION using a certain PIN GROUP on a certain
536 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
Dkernel-parameters.txt898 Disable PIN 1 of APIC timer
1098 Enable PIN 1 of APIC timer
/linux-4.1.27/arch/blackfin/mach-bf527/
DKconfig35 Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
/linux-4.1.27/
DMAINTAINERS7690 PIN CONTROL SUBSYSTEM
7698 PIN CONTROLLER - ATMEL AT91
7704 PIN CONTROLLER - INTEL
7710 PIN CONTROLLER - RENESAS
7716 PIN CONTROLLER - SAMSUNG
7724 PIN CONTROLLER - ST SPEAR