Searched refs:PD0 (Results 1 – 16 of 16) sorted by relevance
/linux-4.1.27/arch/blackfin/include/mach-common/ |
D | ports-d.h | 8 #define PD0 (1 << 0) macro
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/linux-4.1.27/arch/arc/mm/ |
D | tlbex.S | 218 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu 234 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid 237 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
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/linux-4.1.27/Documentation/hwmon/ |
D | max197 | 40 7,6 PD1,PD0 Clock and Power-Down modes
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/linux-4.1.27/arch/arm/boot/dts/ |
D | at91sam9m10g45ek.dts | 121 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
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D | at91sam9263.dtsi | 439 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
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D | at91sam9x5.dtsi | 554 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
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D | at91sam9g45.dtsi | 680 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
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D | sama5d3.dtsi | 610 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
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/linux-4.1.27/arch/powerpc/boot/dts/ |
D | kmeter1.dts | 227 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
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/linux-4.1.27/drivers/pinctrl/sh-pfc/ |
D | pfc-shx3.c | 327 PINMUX_GPIO(PD0),
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D | pfc-sh7786.c | 449 PINMUX_GPIO(PD0),
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D | pfc-sh7785.c | 713 PINMUX_GPIO(PD0),
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D | pfc-sh7203.c | 764 PINMUX_GPIO(PD0),
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D | pfc-sh7264.c | 1134 PINMUX_GPIO(PD0),
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D | pfc-sh7269.c | 1510 PINMUX_GPIO(PD0),
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/linux-4.1.27/drivers/iommu/ |
D | msm_iommu_hw-8xxx.h | 601 #define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v) 788 #define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0) 1168 #define PD0 (PD0_MASK << PD0_SHIFT) macro
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