Searched refs:PANEL_DISPLAY_CTRL (Results 1 - 4 of 4) sorted by relevance
/linux-4.1.27/drivers/staging/sm750fb/ |
H A D | ddk750_display.c | 20 ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL); setDisplayControl() 29 PANEL_DISPLAY_CTRL, TIMING, ENABLE); setDisplayControl() 30 POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); setDisplayControl() 33 PANEL_DISPLAY_CTRL, PLANE, ENABLE); setDisplayControl() 40 ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | setDisplayControl() 41 FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | setDisplayControl() 42 FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE); setDisplayControl() 51 POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); setDisplayControl() 52 } while((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != setDisplayControl() 66 PANEL_DISPLAY_CTRL, PLANE, DISABLE); setDisplayControl() 67 POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); setDisplayControl() 70 PANEL_DISPLAY_CTRL, TIMING, DISABLE); setDisplayControl() 71 POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); setDisplayControl() 142 (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) == waitNextVerticalSync() 209 reg = PEEK32(PANEL_DISPLAY_CTRL); swPanelPowerSequence() 210 reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,FPEN,disp); swPanelPowerSequence() 211 POKE32(PANEL_DISPLAY_CTRL,reg); swPanelPowerSequence() 215 reg = PEEK32(PANEL_DISPLAY_CTRL); swPanelPowerSequence() 216 reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,DATA,disp); swPanelPowerSequence() 217 POKE32(PANEL_DISPLAY_CTRL,reg); swPanelPowerSequence() 220 reg = PEEK32(PANEL_DISPLAY_CTRL); swPanelPowerSequence() 221 reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,VBIASEN,disp); swPanelPowerSequence() 222 POKE32(PANEL_DISPLAY_CTRL,reg); swPanelPowerSequence() 226 reg = PEEK32(PANEL_DISPLAY_CTRL); swPanelPowerSequence() 227 reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,FPEN,disp); swPanelPowerSequence() 228 POKE32(PANEL_DISPLAY_CTRL,reg); swPanelPowerSequence() 238 reg = PEEK32(PANEL_DISPLAY_CTRL); ddk750_setLogicalDispOut() 239 reg = FIELD_VALUE(reg,PANEL_DISPLAY_CTRL,SELECT,(output & PNL_2_MASK)>>PNL_2_OFFSET); ddk750_setLogicalDispOut() 240 POKE32(PANEL_DISPLAY_CTRL,reg); ddk750_setLogicalDispOut()
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H A D | ddk750_mode.c | 144 ulTmpValue = FIELD_VALUE(0,PANEL_DISPLAY_CTRL,VSYNC_PHASE,pModeParam->vertical_sync_polarity)| programModeRegisters() 145 FIELD_VALUE(0,PANEL_DISPLAY_CTRL,HSYNC_PHASE,pModeParam->horizontal_sync_polarity)| programModeRegisters() 146 FIELD_VALUE(0,PANEL_DISPLAY_CTRL,CLOCK_PHASE,pModeParam->clock_phase_polarity)| programModeRegisters() 147 FIELD_SET(0,PANEL_DISPLAY_CTRL,TIMING,ENABLE)| programModeRegisters() 148 FIELD_SET(0,PANEL_DISPLAY_CTRL,PLANE,ENABLE); programModeRegisters() 150 ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | programModeRegisters() 151 FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | programModeRegisters() 152 FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE)| programModeRegisters() 153 FIELD_SET(0,PANEL_DISPLAY_CTRL,VSYNC,ACTIVE_LOW); programModeRegisters() 155 ulReg = (PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) programModeRegisters() 156 & FIELD_CLEAR(PANEL_DISPLAY_CTRL, CLOCK_PHASE) programModeRegisters() 157 & FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE) programModeRegisters() 158 & FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE) programModeRegisters() 159 & FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING) programModeRegisters() 160 & FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE); programModeRegisters() 164 * PANEL_DISPLAY_CTRL register seems requiring few writes programModeRegisters() 171 POKE32(PANEL_DISPLAY_CTRL,ulTmpValue|ulReg); programModeRegisters() 173 while((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg)) programModeRegisters() 178 POKE32(PANEL_DISPLAY_CTRL,ulTmpValue|ulReg); programModeRegisters()
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H A D | sm750_hw.c | 163 POKE32(PANEL_DISPLAY_CTRL, hw_sm750_inithw() 164 FIELD_VALUE(PEEK32(PANEL_DISPLAY_CTRL), hw_sm750_inithw() 165 PANEL_DISPLAY_CTRL, hw_sm750_inithw() 389 reg = PEEK32(PANEL_DISPLAY_CTRL); hw_sm750_crtc_setMode() 390 POKE32(PANEL_DISPLAY_CTRL, hw_sm750_crtc_setMode() 392 PANEL_DISPLAY_CTRL, FORMAT, hw_sm750_crtc_setMode() 548 POKE32(PANEL_DISPLAY_CTRL, FIELD_VALUE(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, DATA, pps)); hw_sm750_setBLANK()
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H A D | ddk750_reg.h | 1050 #define PANEL_DISPLAY_CTRL 0x080000 macro
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