Searched refs:PACKET0 (Results 1 - 21 of 21) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
H A Duvd_v2_2.c45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); uvd_v2_2_fence_emit()
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); uvd_v2_2_fence_emit()
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); uvd_v2_2_fence_emit()
51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); uvd_v2_2_fence_emit()
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); uvd_v2_2_fence_emit()
56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); uvd_v2_2_fence_emit()
58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); uvd_v2_2_fence_emit()
79 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); uvd_v2_2_semaphore_emit()
82 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); uvd_v2_2_semaphore_emit()
85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); uvd_v2_2_semaphore_emit()
H A Duvd_v1_0.c87 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); uvd_v1_0_fence_emit()
89 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); uvd_v1_0_fence_emit()
91 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); uvd_v1_0_fence_emit()
94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); uvd_v1_0_fence_emit()
96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); uvd_v1_0_fence_emit()
98 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); uvd_v1_0_fence_emit()
185 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); uvd_v1_0_init()
189 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); uvd_v1_0_init()
193 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); uvd_v1_0_init()
198 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); uvd_v1_0_init()
201 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); uvd_v1_0_init()
433 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); uvd_v1_0_ring_test()
485 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); uvd_v1_0_ib_execute()
487 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); uvd_v1_0_ib_execute()
H A Duvd_v3_1.c47 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); uvd_v3_1_semaphore_emit()
50 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); uvd_v3_1_semaphore_emit()
53 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); uvd_v3_1_semaphore_emit()
H A Dr300.c191 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); r300_fence_ring_emit()
193 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); r300_fence_ring_emit()
196 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_fence_ring_emit()
198 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); r300_fence_ring_emit()
201 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); r300_fence_ring_emit()
205 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); r300_fence_ring_emit()
208 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); r300_fence_ring_emit()
211 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); r300_fence_ring_emit()
213 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); r300_fence_ring_emit()
244 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); r300_ring_start()
250 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); r300_ring_start()
252 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); r300_ring_start()
256 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); r300_ring_start()
258 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); r300_ring_start()
260 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); r300_ring_start()
262 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_ring_start()
264 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); r300_ring_start()
266 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); r300_ring_start()
270 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); r300_ring_start()
272 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_ring_start()
274 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); r300_ring_start()
276 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); r300_ring_start()
286 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); r300_ring_start()
295 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); r300_ring_start()
297 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); r300_ring_start()
300 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); r300_ring_start()
H A Drv515.c70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); rv515_ring_start()
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); rv515_ring_start()
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); rv515_ring_start()
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); rv515_ring_start()
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); rv515_ring_start()
84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); rv515_ring_start()
86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); rv515_ring_start()
88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); rv515_ring_start()
90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); rv515_ring_start()
92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); rv515_ring_start()
94 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); rv515_ring_start()
96 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); rv515_ring_start()
98 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); rv515_ring_start()
100 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); rv515_ring_start()
110 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); rv515_ring_start()
119 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); rv515_ring_start()
121 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); rv515_ring_start()
123 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); rv515_ring_start()
125 radeon_ring_write(ring, PACKET0(0x20C8, 0)); rv515_ring_start()
H A Dr200.c105 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); r200_copy_dma()
113 radeon_ring_write(ring, PACKET0(0x720, 2)); r200_copy_dma()
120 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); r200_copy_dma()
H A Dradeon_uvd.c706 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); radeon_uvd_send_msg()
708 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); radeon_uvd_send_msg()
710 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); radeon_uvd_send_msg()
H A Dr420.c219 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); r420_cp_errata_init()
233 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r420_cp_errata_fini()
H A Dr100.c841 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); r100_ring_hdp_flush()
844 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); r100_ring_hdp_flush()
857 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); r100_fence_ring_emit()
859 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); r100_fence_ring_emit()
862 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); r100_fence_ring_emit()
866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); r100_fence_ring_emit()
868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); r100_fence_ring_emit()
943 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); r100_copy_blit()
945 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); r100_copy_blit()
982 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); r100_ring_start()
1415 * PACKET0 - VLINE_START_END + value
1416 * PACKET0 - WAIT_UNTIL +_value
3655 radeon_ring_write(ring, PACKET0(scratch, 0)); r100_ring_test()
3682 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); r100_ring_ib_execute()
3686 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); r100_ring_ib_execute()
3710 ib.ptr[0] = PACKET0(scratch, 0); r100_ib_test()
H A Dr300d.h60 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
H A Dni.c2532 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); cayman_vm_flush()
2536 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); cayman_vm_flush()
2540 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); cayman_vm_flush()
H A Drv515d.h200 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
H A Drv770d.h984 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
H A Dnid.h1140 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
H A Dr100d.h59 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
H A Dcikd.h1683 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
H A Dsid.h1584 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
H A Devergreend.h1533 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
H A Dr600_cs.c810 * PACKET0 - VLINE_START_END + value
H A Dr600d.h1583 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
H A Dr600.c2860 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); r600_fence_ring_emit()

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