87 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v1_0_fence_emit()
89 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v1_0_fence_emit()
91 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v1_0_fence_emit()
94 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v1_0_fence_emit()
96 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v1_0_fence_emit()
98 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v1_0_fence_emit()
185 	tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);  in uvd_v1_0_init()
189 	tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v1_0_init()
193 	tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v1_0_init()
198 	radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v1_0_init()
201 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));  in uvd_v1_0_init()
433 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in uvd_v1_0_ring_test()
485 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));  in uvd_v1_0_ib_execute()
487 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));  in uvd_v1_0_ib_execute()