Searched refs:OUTREG (Results 1 - 11 of 11) sorted by relevance

/linux-4.1.27/drivers/video/fbdev/aty/
H A Dradeon_accel.c36 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) | radeon_fixup_offset()
38 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); radeon_fixup_offset()
39 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); radeon_fixup_offset()
47 OUTREG(DP_GUI_MASTER_CNTL, radeonfb_prim_fillrect()
52 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]); radeonfb_prim_fillrect()
54 OUTREG(DP_BRUSH_FRGD_CLR, region->color); radeonfb_prim_fillrect()
55 OUTREG(DP_WRITE_MSK, 0xffffffff); radeonfb_prim_fillrect()
56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); radeonfb_prim_fillrect()
59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); radeonfb_prim_fillrect()
60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); radeonfb_prim_fillrect()
63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx); radeonfb_prim_fillrect()
64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); radeonfb_prim_fillrect()
113 OUTREG(DP_GUI_MASTER_CNTL, radeonfb_prim_copyarea()
119 OUTREG(DP_WRITE_MSK, 0xffffffff); radeonfb_prim_copyarea()
120 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) radeonfb_prim_copyarea()
124 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); radeonfb_prim_copyarea()
125 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); radeonfb_prim_copyarea()
128 OUTREG(SRC_Y_X, (sy << 16) | sx); radeonfb_prim_copyarea()
129 OUTREG(DST_Y_X, (dy << 16) | dx); radeonfb_prim_copyarea()
130 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w); radeonfb_prim_copyarea()
217 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | radeonfb_engine_reset()
222 OUTREG(RBBM_SOFT_RESET, 0); radeonfb_engine_reset()
224 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ radeonfb_engine_reset()
226 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | radeonfb_engine_reset()
235 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32) radeonfb_engine_reset()
246 OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET); radeonfb_engine_reset()
248 OUTREG(HOST_PATH_CNTL, host_path_cntl); radeonfb_engine_reset()
251 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); radeonfb_engine_reset()
253 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); radeonfb_engine_reset()
262 OUTREG(RB3D_CNTL, 0); radeonfb_engine_init()
268 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | radeonfb_engine_init()
277 OUTREG(RB2D_DSTCACHE_MODE, 0); radeonfb_engine_init()
286 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) | radeonfb_engine_init()
288 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); radeonfb_engine_init()
289 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); radeonfb_engine_init()
298 OUTREG(DEFAULT_SC_TOP_LEFT, 0); radeonfb_engine_init()
299 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | radeonfb_engine_init()
306 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | radeonfb_engine_init()
313 OUTREG(DST_LINE_START, 0); radeonfb_engine_init()
314 OUTREG(DST_LINE_END, 0); radeonfb_engine_init()
317 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); radeonfb_engine_init()
318 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); radeonfb_engine_init()
321 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); radeonfb_engine_init()
322 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); radeonfb_engine_init()
325 OUTREG(DP_WRITE_MSK, 0xffffffff); radeonfb_engine_init()
H A Dradeon_pm.c551 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN); OUTMC()
552 OUTREG( MC_IND_DATA, value); OUTMC()
557 OUTREG( MC_IND_INDEX, indx); INMC()
702 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); radeon_pm_restore_regs()
703 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); radeon_pm_restore_regs()
704 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); radeon_pm_restore_regs()
705 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); radeon_pm_restore_regs()
706 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); radeon_pm_restore_regs()
707 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); radeon_pm_restore_regs()
709 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); radeon_pm_restore_regs()
710 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]); radeon_pm_restore_regs()
711 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]); radeon_pm_restore_regs()
712 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]); radeon_pm_restore_regs()
713 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]); radeon_pm_restore_regs()
714 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); radeon_pm_restore_regs()
715 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]); radeon_pm_restore_regs()
716 OUTREG(AGP_CNTL, rinfo->save_regs[16]); radeon_pm_restore_regs()
717 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]); radeon_pm_restore_regs()
718 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]); radeon_pm_restore_regs()
721 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); radeon_pm_restore_regs()
722 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); radeon_pm_restore_regs()
723 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); radeon_pm_restore_regs()
724 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]); radeon_pm_restore_regs()
725 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]); radeon_pm_restore_regs()
726 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]); radeon_pm_restore_regs()
727 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]); radeon_pm_restore_regs()
728 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]); radeon_pm_restore_regs()
729 OUTREG(GPIO_MONID, rinfo->save_regs[27]); radeon_pm_restore_regs()
730 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]); radeon_pm_restore_regs()
735 OUTREG(GPIOPAD_MASK, 0x0001ffff); radeon_pm_disable_iopad()
736 OUTREG(GPIOPAD_EN, 0x00000400); radeon_pm_disable_iopad()
737 OUTREG(GPIOPAD_A, 0x00000000); radeon_pm_disable_iopad()
738 OUTREG(ZV_LCDPAD_MASK, 0x00000000); radeon_pm_disable_iopad()
739 OUTREG(ZV_LCDPAD_EN, 0x00000000); radeon_pm_disable_iopad()
740 OUTREG(ZV_LCDPAD_A, 0x00000000); radeon_pm_disable_iopad()
741 OUTREG(GPIO_VGA_DDC, 0x00030000); radeon_pm_disable_iopad()
742 OUTREG(GPIO_DVI_DDC, 0x00000000); radeon_pm_disable_iopad()
743 OUTREG(GPIO_MONID, 0x00030000); radeon_pm_disable_iopad()
744 OUTREG(GPIO_CRT2_DDC, 0x00000000); radeon_pm_disable_iopad()
788 OUTREG(BUS_CNTL1, reg); radeon_pm_low_current()
802 OUTREG(TV_DAC_CNTL, reg); radeon_pm_low_current()
806 OUTREG(TMDS_TRANSMITTER_CNTL, reg); radeon_pm_low_current()
810 OUTREG(DAC_CNTL, reg); radeon_pm_low_current()
814 OUTREG(DAC_CNTL2, reg); radeon_pm_low_current()
818 OUTREG(TV_DAC_CNTL, reg); radeon_pm_low_current()
910 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & radeon_pm_setup_for_suspend()
963 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); radeon_pm_setup_for_suspend()
964 OUTREG(BUS_CNTL1, radeon_pm_setup_for_suspend()
968 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1)); radeon_pm_setup_for_suspend()
969 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000); radeon_pm_setup_for_suspend()
974 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) radeon_pm_setup_for_suspend()
982 OUTREG(AGP_CNTL, radeon_pm_setup_for_suspend()
1007 OUTREG(DISP_MISC_CNTL, disp_mis_cntl); radeon_pm_setup_for_suspend()
1029 OUTREG(DISP_PWR_MAN, disp_pwr_man); radeon_pm_setup_for_suspend()
1047 OUTREG(DISP_PWR_MAN, disp_pwr_man); radeon_pm_setup_for_suspend()
1050 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) radeon_pm_setup_for_suspend()
1052 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) radeon_pm_setup_for_suspend()
1109 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); radeon_pm_program_mode_reg()
1114 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); radeon_pm_program_mode_reg()
1119 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); radeon_pm_program_mode_reg()
1257 OUTREG( CRTC_MORE_CNTL, 0); radeon_pm_full_reset_sdram()
1258 OUTREG( FP_GEN_CNTL, 0); radeon_pm_full_reset_sdram()
1259 OUTREG( FP2_GEN_CNTL,0); radeon_pm_full_reset_sdram()
1261 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) ); radeon_pm_full_reset_sdram()
1262 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) ); radeon_pm_full_reset_sdram()
1284 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl radeon_pm_full_reset_sdram()
1305 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); radeon_pm_full_reset_sdram()
1315 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); radeon_pm_full_reset_sdram()
1321 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl); radeon_pm_full_reset_sdram()
1330 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl radeon_pm_full_reset_sdram()
1335 OUTREG(MEM_SDRAM_MODE_REG, radeon_pm_full_reset_sdram()
1342 OUTREG(MEM_SDRAM_MODE_REG, radeon_pm_full_reset_sdram()
1345 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); radeon_pm_full_reset_sdram()
1352 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20)); radeon_pm_full_reset_sdram()
1355 OUTREG( MEM_SDRAM_MODE_REG, radeon_pm_full_reset_sdram()
1373 OUTREG( MEM_SDRAM_MODE_REG, radeon_pm_full_reset_sdram()
1376 OUTREG(EXT_MEM_CNTL, memRefreshCntl); radeon_pm_full_reset_sdram()
1384 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl radeon_pm_full_reset_sdram()
1388 OUTREG( MEM_SDRAM_MODE_REG, radeon_pm_full_reset_sdram()
1414 OUTREG( MEM_SDRAM_MODE_REG, radeon_pm_full_reset_sdram()
1417 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); radeon_pm_full_reset_sdram()
1420 OUTREG( CRTC_GEN_CNTL, crtcGenCntl); radeon_pm_full_reset_sdram()
1421 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2); radeon_pm_full_reset_sdram()
1422 OUTREG( FP_GEN_CNTL, fp_gen_cntl); radeon_pm_full_reset_sdram()
1423 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl); radeon_pm_full_reset_sdram()
1425 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl); radeon_pm_full_reset_sdram()
1439 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE); radeon_pm_reset_pad_ctlr_strength()
1560 OUTREG(VGA_DDA_ON_OFF, r2ec); radeon_pm_m10_disable_spread_spectrum()
1574 OUTREG(VGA_DDA_ON_OFF, r2ec); radeon_pm_m10_disable_spread_spectrum()
1587 OUTREG(VGA_DDA_ON_OFF, r2ec); radeon_pm_m10_enable_lvds_spread_spectrum()
1606 OUTREG(VGA_DDA_ON_OFF, r2ec); radeon_pm_m10_enable_lvds_spread_spectrum()
1611 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN); radeon_pm_m10_enable_lvds_spread_spectrum()
1617 OUTREG(LVDS_PLL_CNTL, tmp); radeon_pm_m10_enable_lvds_spread_spectrum()
1689 OUTREG(MC_CNTL, rinfo->save_regs[46]); radeon_pm_m10_reconfigure_mc()
1690 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); radeon_pm_m10_reconfigure_mc()
1691 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); radeon_pm_m10_reconfigure_mc()
1692 OUTREG(MEM_SDRAM_MODE_REG, radeon_pm_m10_reconfigure_mc()
1694 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); radeon_pm_m10_reconfigure_mc()
1695 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); radeon_pm_m10_reconfigure_mc()
1696 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); radeon_pm_m10_reconfigure_mc()
1697 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); radeon_pm_m10_reconfigure_mc()
1698 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); radeon_pm_m10_reconfigure_mc()
1699 OUTREG(MC_DEBUG, rinfo->save_regs[53]); radeon_pm_m10_reconfigure_mc()
1717 OUTREG(MC_IND_INDEX, 0); radeon_pm_m10_reconfigure_mc()
1725 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); radeon_reinitialize_M10()
1726 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); radeon_reinitialize_M10()
1727 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); radeon_reinitialize_M10()
1728 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); radeon_reinitialize_M10()
1729 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); radeon_reinitialize_M10()
1730 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); radeon_reinitialize_M10()
1731 OUTREG(BUS_CNTL, rinfo->save_regs[36]); radeon_reinitialize_M10()
1732 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); radeon_reinitialize_M10()
1733 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); radeon_reinitialize_M10()
1734 OUTREG(FCP_CNTL, rinfo->save_regs[38]); radeon_reinitialize_M10()
1735 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); radeon_reinitialize_M10()
1736 OUTREG(DAC_CNTL, rinfo->save_regs[40]); radeon_reinitialize_M10()
1737 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); radeon_reinitialize_M10()
1738 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); radeon_reinitialize_M10()
1741 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); radeon_reinitialize_M10()
1754 OUTREG(SURFACE_CNTL, 0); radeon_reinitialize_M10()
1761 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M10()
1765 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M10()
1768 OUTREG(AGP_CNTL, rinfo->save_regs[16]); radeon_reinitialize_M10()
1769 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); radeon_reinitialize_M10()
1770 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); radeon_reinitialize_M10()
1778 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]); radeon_reinitialize_M10()
1779 OUTREG(FW_CNTL, rinfo->save_regs[57]); radeon_reinitialize_M10()
1780 OUTREG(HDP_DEBUG, rinfo->save_regs[96]); radeon_reinitialize_M10()
1781 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); radeon_reinitialize_M10()
1782 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); radeon_reinitialize_M10()
1783 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); radeon_reinitialize_M10()
1789 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL) radeon_reinitialize_M10()
1791 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL) radeon_reinitialize_M10()
1796 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) radeon_reinitialize_M10()
1895 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); radeon_reinitialize_M10()
1897 OUTREG(PALETTE_30_DATA, 0x15555555); radeon_reinitialize_M10()
1898 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); radeon_reinitialize_M10()
1901 OUTREG(PALETTE_30_DATA, 0x15555555); radeon_reinitialize_M10()
1903 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); radeon_reinitialize_M10()
1907 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]); radeon_reinitialize_M10()
1908 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]); radeon_reinitialize_M10()
1911 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & radeon_reinitialize_M10()
1913 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); radeon_reinitialize_M10()
1915 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]); radeon_reinitialize_M10()
1918 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); radeon_reinitialize_M10()
1919 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); radeon_reinitialize_M10()
1920 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); radeon_reinitialize_M10()
1927 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); radeon_reinitialize_M10()
1931 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); radeon_reinitialize_M10()
1932 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); radeon_reinitialize_M10()
1950 OUTREG(MC_CNTL, rinfo->save_regs[46]); radeon_pm_m9p_reconfigure_mc()
1951 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); radeon_pm_m9p_reconfigure_mc()
1952 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); radeon_pm_m9p_reconfigure_mc()
1953 OUTREG(MEM_SDRAM_MODE_REG, radeon_pm_m9p_reconfigure_mc()
1955 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); radeon_pm_m9p_reconfigure_mc()
1956 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); radeon_pm_m9p_reconfigure_mc()
1957 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); radeon_pm_m9p_reconfigure_mc()
1958 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); radeon_pm_m9p_reconfigure_mc()
1959 OUTREG(MC_DEBUG, rinfo->save_regs[53]); radeon_pm_m9p_reconfigure_mc()
1960 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); radeon_pm_m9p_reconfigure_mc()
1968 OUTREG(MC_IND_INDEX, 0); radeon_pm_m9p_reconfigure_mc()
1969 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); radeon_pm_m9p_reconfigure_mc()
1979 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); radeon_reinitialize_M9P()
1980 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); radeon_reinitialize_M9P()
1981 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); radeon_reinitialize_M9P()
1982 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); radeon_reinitialize_M9P()
1983 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); radeon_reinitialize_M9P()
1984 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); radeon_reinitialize_M9P()
1985 OUTREG(BUS_CNTL, rinfo->save_regs[36]); radeon_reinitialize_M9P()
1986 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); radeon_reinitialize_M9P()
1987 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); radeon_reinitialize_M9P()
1988 OUTREG(FCP_CNTL, rinfo->save_regs[38]); radeon_reinitialize_M9P()
1989 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); radeon_reinitialize_M9P()
1991 OUTREG(DAC_CNTL, rinfo->save_regs[40]); radeon_reinitialize_M9P()
1992 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); radeon_reinitialize_M9P()
2005 OUTREG(SURFACE_CNTL, 0); radeon_reinitialize_M9P()
2012 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M9P()
2016 OUTREG(TV_DAC_CNTL, tmp); radeon_reinitialize_M9P()
2020 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); radeon_reinitialize_M9P()
2021 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); radeon_reinitialize_M9P()
2022 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); radeon_reinitialize_M9P()
2024 OUTREG(AGP_CNTL, rinfo->save_regs[16]); radeon_reinitialize_M9P()
2025 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */ radeon_reinitialize_M9P()
2026 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); radeon_reinitialize_M9P()
2033 OUTREG(FW_CNTL, rinfo->save_regs[57]); radeon_reinitialize_M9P()
2036 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) radeon_reinitialize_M9P()
2111 OUTREG(CRTC_GEN_CNTL, 0x04000000); radeon_reinitialize_M9P()
2112 OUTREG(CRTC2_GEN_CNTL, 0x04000000); radeon_reinitialize_M9P()
2113 OUTREG(FP_GEN_CNTL, 0x00004008); radeon_reinitialize_M9P()
2114 OUTREG(FP2_GEN_CNTL, 0x00000008); radeon_reinitialize_M9P()
2115 OUTREG(LVDS_GEN_CNTL, 0x08000008); radeon_reinitialize_M9P()
2127 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); radeon_reinitialize_M9P()
2129 OUTREG(PALETTE_30_DATA, 0x15555555); radeon_reinitialize_M9P()
2130 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); radeon_reinitialize_M9P()
2133 OUTREG(PALETTE_30_DATA, 0x15555555); radeon_reinitialize_M9P()
2135 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); radeon_reinitialize_M9P()
2139 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]); radeon_reinitialize_M9P()
2140 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000); radeon_reinitialize_M9P()
2147 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); radeon_reinitialize_M9P()
2148 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); radeon_reinitialize_M9P()
2149 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); radeon_reinitialize_M9P()
2164 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & radeon_reinitialize_M9P()
2166 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON); radeon_reinitialize_M9P()
2167 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); radeon_reinitialize_M9P()
2174 OUTREG(0x2ec, 0x6332a020); radeon_reinitialize_M9P()
2189 OUTREG(0x2ec, 0x6332a3f0); radeon_reinitialize_M9P()
2196 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); radeon_reinitialize_M9P()
2200 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); radeon_reinitialize_M9P()
2201 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); radeon_reinitialize_M9P()
2219 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2220 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2221 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2222 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2223 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2224 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2227 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2233 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2234 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2235 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2236 OUTREG(DAC_CNTL, 0xff00410a);
2237 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2238 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2240 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2241 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2242 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2243 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2246 OUTREG(MC_IND_INDEX, 0);
2248 OUTREG(MC_IND_INDEX, 0);
2250 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2344 OUTREG(MC_IND_INDEX, 0);
2346 OUTREG(MC_IND_INDEX, 0);
2349 OUTREG(MC_IND_INDEX, 0);
2351 OUTREG(MC_IND_INDEX, 0);
2357 OUTREG(MEM_CNTL, 0x29002901);
2358 OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2359 OUTREG(EXT_MEM_CNTL, 0x1a394333);
2360 OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2361 OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2362 OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
2363 OUTREG(MC_DEBUG, 0);
2364 OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2367 OUTREG(MC_IND_INDEX, 0);
2369 OUTREG(MC_IND_INDEX, 0);
2371 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2376 OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
2379 OUTREG(FP_GEN_CNTL, tmp);
2383 OUTREG(DISP_OUTPUT_CNTL, tmp);
2396 OUTREG(CRTC_MORE_CNTL, 0);
2399 OUTREG(CRTC_PITCH, 32);
2412 OUTREG(FP_GEN_CNTL, tmp);
2414 OUTREG(FP_GEN_CNTL, tmp);
2416 OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2417 OUTREG(CRTC_MORE_CNTL, 0);
2421 OUTREG(CRTC_MORE_CNTL, tmp);
2427 OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2428 OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2433 OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2434 OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2435 OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2436 OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2437 OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2438 OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2439 OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2440 OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2441 OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2442 OUTREG(FP_HORZ_STRETCH, 0);
2443 OUTREG(FP_VERT_STRETCH, 0);
2444 OUTREG(OVR_CLR, 0);
2445 OUTREG(OVR_WID_LEFT_RIGHT, 0);
2446 OUTREG(OVR_WID_TOP_BOTTOM, 0);
2460 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2481 OUTREG(CRTC2_GEN_CNTL, c2gc);
2483 OUTREG(CRTC_GEN_CNTL, cgc);
2484 OUTREG(CRTC_EXT_CNTL, cec);
2485 OUTREG(CRTC_PITCH, 0xa0);
2486 OUTREG(CRTC_OFFSET, 0);
2487 OUTREG(CRTC_OFFSET_CNTL, 0);
2489 OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2490 OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2494 OUTREG(0x2a8, 0x0000061b);
2496 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2499 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2502 OUTREG(FP_GEN_CNTL, tmp2);
2505 OUTREG(FP_GEN_CNTL, tmp2);
2507 OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2509 OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2511 OUTREG(CUR_OFFSET, 0);
2683 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN)); radeonfb_pci_suspend()
2685 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON)); radeonfb_pci_suspend()
2686 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000); radeonfb_pci_suspend()
2688 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON)); radeonfb_pci_suspend()
2881 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000); radeonfb_pm_init()
H A Dradeon_backlight.c78 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); radeon_bl_update_status()
93 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); radeon_bl_update_status()
109 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); radeon_bl_update_status()
112 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); radeon_bl_update_status()
H A Dradeon_base.c313 OUTREG(MPP_TB_CONFIG, temp); radeon_map_ROM()
851 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + radeonfb_pan_display()
891 OUTREG(LVDS_GEN_CNTL, tmp); radeonfb_ioctl()
905 OUTREG(CRTC_EXT_CNTL, tmp); radeonfb_ioctl()
961 OUTREG(CRTC_EXT_CNTL, val); radeon_screen_blank()
983 OUTREG(LVDS_GEN_CNTL, target_val); radeon_screen_blank()
985 OUTREG(LVDS_GEN_CNTL, target_val radeon_screen_blank()
992 OUTREG(LVDS_GEN_CNTL, target_val); radeon_screen_blank()
1003 OUTREG(LVDS_GEN_CNTL, val); radeon_screen_blank()
1016 OUTREG(LVDS_GEN_CNTL, val); radeon_screen_blank()
1019 OUTREG(LVDS_GEN_CNTL, val); radeon_screen_blank()
1086 OUTREG(PALETTE_INDEX, pindex>>1); radeon_setcolreg()
1087 OUTREG(PALETTE_DATA, radeon_setcolreg()
1096 OUTREG(PALETTE_INDEX, pindex); radeon_setcolreg()
1097 OUTREG(PALETTE_DATA, (red << 16) | radeon_setcolreg()
1141 OUTREG(DAC_CNTL2, dac_cntl2); radeonfb_setcolreg()
1171 OUTREG(DAC_CNTL2, dac_cntl2); radeonfb_setcmap()
1341 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); radeon_lvds_timer_func()
1362 OUTREG(common_regs[i].reg, common_regs[i].val); radeon_write_mode()
1366 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); radeon_write_mode()
1367 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); radeon_write_mode()
1368 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); radeon_write_mode()
1371 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); radeon_write_mode()
1374 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); radeon_write_mode()
1376 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); radeon_write_mode()
1377 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); radeon_write_mode()
1378 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); radeon_write_mode()
1379 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); radeon_write_mode()
1380 OUTREG(CRTC_OFFSET, 0); radeon_write_mode()
1381 OUTREG(CRTC_OFFSET_CNTL, 0); radeon_write_mode()
1382 OUTREG(CRTC_PITCH, mode->crtc_pitch); radeon_write_mode()
1383 OUTREG(SURFACE_CNTL, mode->surface_cntl); radeon_write_mode()
1389 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); radeon_write_mode()
1390 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); radeon_write_mode()
1391 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); radeon_write_mode()
1392 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); radeon_write_mode()
1393 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); radeon_write_mode()
1394 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); radeon_write_mode()
1395 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); radeon_write_mode()
1396 OUTREG(TMDS_CRC, mode->tmds_crc); radeon_write_mode()
1397 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); radeon_write_mode()
1925 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); fixup_memory_mappings()
1930 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); fixup_memory_mappings()
1931 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); fixup_memory_mappings()
1939 OUTREG(MC_FB_LOCATION, fixup_memory_mappings()
1943 OUTREG(MC_FB_LOCATION, 0x7fff0000); fixup_memory_mappings()
1955 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); fixup_memory_mappings()
1957 OUTREG(MC_AGP_LOCATION, 0xffffe000); fixup_memory_mappings()
1964 OUTREG(DISPLAY_BASE_ADDR, aper_base); fixup_memory_mappings()
1966 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); fixup_memory_mappings()
1967 OUTREG(OV0_BASE_ADDR, aper_base); fixup_memory_mappings()
1969 OUTREG(DISPLAY_BASE_ADDR, 0); fixup_memory_mappings()
1971 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); fixup_memory_mappings()
1972 OUTREG(OV0_BASE_ADDR, 0); fixup_memory_mappings()
1977 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); fixup_memory_mappings()
1978 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); fixup_memory_mappings()
1980 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); fixup_memory_mappings()
2005 OUTREG(MC_FB_LOCATION, tom); radeon_identify_vram()
2006 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); radeon_identify_vram()
2007 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); radeon_identify_vram()
2008 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); radeon_identify_vram()
2011 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); radeon_identify_vram()
H A Dradeon_i2c.c27 OUTREG(chan->ddc_reg, val); radeon_gpio_setscl()
41 OUTREG(chan->ddc_reg, val); radeon_gpio_setsda()
H A Dradeonfb.h393 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) macro
405 OUTREG(addr, tmp); _OUTREGP()
447 OUTREG(CLOCK_CNTL_INDEX, tmp); radeon_pll_errata_after_data()
449 OUTREG(CLOCK_CNTL_INDEX, save); radeon_pll_errata_after_data()
470 OUTREG(CLOCK_CNTL_DATA, val); __OUTPLL()
H A Dradeon_monitor.c327 OUTREG(CRTC_EXT_CNTL, ulData); radeon_crt_is_connected()
341 OUTREG(DAC_EXT_CNTL, ulData); radeon_crt_is_connected()
349 OUTREG(DAC_CNTL, ulData); radeon_crt_is_connected()
360 OUTREG(DAC_CNTL, ulOrigDAC_CNTL ); radeon_crt_is_connected()
361 OUTREG(DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL ); radeon_crt_is_connected()
362 OUTREG(CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL); radeon_crt_is_connected()
/linux-4.1.27/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c408 OUTREG(DSPABASE, offset); intelfbhw_pan_display()
430 OUTREG(DSPACNTR, tmp); intelfbhw_do_blank()
433 OUTREG(DSPABASE, tmp); intelfbhw_do_blank()
465 OUTREG(ADPA, tmp); intelfbhw_do_blank()
509 OUTREG(palette_reg + (regno << 2), intelfbhw_setcolreg()
1301 OUTREG(VGACNTRL, tmp); intelfbhw_program_mode()
1358 OUTREG(pipe_conf_reg, tmp); intelfbhw_program_mode()
1370 OUTREG(pipe_conf_reg, tmp); intelfbhw_program_mode()
1374 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE); intelfbhw_program_mode()
1379 OUTREG(DSPACNTR, tmp); intelfbhw_program_mode()
1382 OUTREG(DSPBCNTR, tmp); intelfbhw_program_mode()
1387 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE); intelfbhw_program_mode()
1388 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE); intelfbhw_program_mode()
1389 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE); intelfbhw_program_mode()
1395 OUTREG(ADPA, tmp); intelfbhw_program_mode()
1398 OUTREG(0x61204, 0xabcd0000); intelfbhw_program_mode()
1403 OUTREG(dpll_reg, tmp); intelfbhw_program_mode()
1406 OUTREG(fp0_reg, *fp0); intelfbhw_program_mode()
1407 OUTREG(fp1_reg, *fp1); intelfbhw_program_mode()
1410 OUTREG(dpll_reg, *dpll); intelfbhw_program_mode()
1413 OUTREG(DVOB, hw->dvob); intelfbhw_program_mode()
1414 OUTREG(DVOC, hw->dvoc); intelfbhw_program_mode()
1417 OUTREG(0x61204, 0x00000000); intelfbhw_program_mode()
1420 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE); intelfbhw_program_mode()
1421 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); intelfbhw_program_mode()
1424 OUTREG(hsync_reg, *hs); intelfbhw_program_mode()
1425 OUTREG(hblank_reg, *hb); intelfbhw_program_mode()
1426 OUTREG(htotal_reg, *ht); intelfbhw_program_mode()
1427 OUTREG(vsync_reg, *vs); intelfbhw_program_mode()
1428 OUTREG(vblank_reg, *vb); intelfbhw_program_mode()
1429 OUTREG(vtotal_reg, *vt); intelfbhw_program_mode()
1430 OUTREG(src_size_reg, *ss); intelfbhw_program_mode()
1435 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN); intelfbhw_program_mode()
1438 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN); intelfbhw_program_mode()
1441 OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */ intelfbhw_program_mode()
1444 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE); intelfbhw_program_mode()
1450 OUTREG(ADPA, tmp); intelfbhw_program_mode()
1462 OUTREG(DSPACNTR, tmp); intelfbhw_program_mode()
1463 OUTREG(DSPACNTR, intelfbhw_program_mode()
1469 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); intelfbhw_program_mode()
1470 OUTREG(DSPASTRIDE, hw->disp_a_stride); intelfbhw_program_mode()
1471 OUTREG(DSPABASE, hw->disp_a_base); intelfbhw_program_mode()
1477 OUTREG(DSPACNTR, tmp); intelfbhw_program_mode()
1478 OUTREG(DSPABASE, hw->disp_a_base); intelfbhw_program_mode()
1597 OUTREG(FENCE + (i << 2), 0); reset_state()
1610 OUTREG(PRI_RING_LENGTH, 0); reset_state()
1611 OUTREG(PRI_RING_HEAD, 0); reset_state()
1612 OUTREG(PRI_RING_TAIL, 0); reset_state()
1613 OUTREG(PRI_RING_START, 0); reset_state()
1647 OUTREG(PRI_RING_LENGTH, 0); intelfbhw_2d_start()
1648 OUTREG(PRI_RING_TAIL, 0); intelfbhw_2d_start()
1649 OUTREG(PRI_RING_HEAD, 0); intelfbhw_2d_start()
1651 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK); intelfbhw_2d_start()
1652 OUTREG(PRI_RING_LENGTH, intelfbhw_2d_start()
1855 OUTREG(CURSOR_A_CONTROL, tmp); intelfbhw_cursor_init()
1856 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); intelfbhw_cursor_init()
1862 OUTREG(CURSOR_CONTROL, tmp); intelfbhw_cursor_init()
1863 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12); intelfbhw_cursor_init()
1866 OUTREG(CURSOR_SIZE, tmp); intelfbhw_cursor_init()
1885 OUTREG(CURSOR_A_CONTROL, tmp); intelfbhw_cursor_hide()
1887 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); intelfbhw_cursor_hide()
1891 OUTREG(CURSOR_CONTROL, tmp); intelfbhw_cursor_hide()
1914 OUTREG(CURSOR_A_CONTROL, tmp); intelfbhw_cursor_show()
1916 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); intelfbhw_cursor_show()
1920 OUTREG(CURSOR_CONTROL, tmp); intelfbhw_cursor_show()
1940 OUTREG(CURSOR_A_POSITION, tmp); intelfbhw_cursor_setpos()
1943 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); intelfbhw_cursor_setpos()
1952 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK); intelfbhw_cursor_setcolor()
1953 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK); intelfbhw_cursor_setcolor()
1954 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK); intelfbhw_cursor_setcolor()
1955 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK); intelfbhw_cursor_setcolor()
2027 OUTREG(PIPEASTAT, INREG(PIPEASTAT)); intelfbhw_irq()
2032 OUTREG(DSPABASE, dinfo->vsync.pan_offset); intelfbhw_irq()
2077 OUTREG(DSPABASE, dinfo->vsync.pan_offset); intelfbhw_disable_irq()
H A Dintelfb_i2c.c60 OUTREG(chan->reg, (state ? SCL_VAL_OUT : 0) | intelfb_gpio_setscl()
71 OUTREG(chan->reg, (state ? SDA_VAL_OUT : 0) | intelfb_gpio_setsda()
82 OUTREG(chan->reg, SCL_DIR_MASK); intelfb_gpio_getscl()
83 OUTREG(chan->reg, 0); intelfb_gpio_getscl()
94 OUTREG(chan->reg, SDA_DIR_MASK); intelfb_gpio_getsda()
95 OUTREG(chan->reg, 0); intelfb_gpio_getsda()
H A Dintelfbhw.h530 #define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \ macro
547 OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \
H A Dintelfbdrv.c1372 OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); intelfb_set_par()

Completed in 384 milliseconds