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Searched refs:MSC01E_INT_SW0 (Results 1 – 2 of 2) sorted by relevance

/linux-4.1.27/arch/mips/mti-malta/
Dmalta-int.c262 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
350 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); in arch_init_irq()
352 cpu_ipi_resched_irq = MSC01E_INT_SW0; in arch_init_irq()
/linux-4.1.27/arch/mips/include/asm/mips-boards/
Dmaltaint.h49 #define MSC01E_INT_SW0 1 macro