/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723be/ |
H A D | phy.c | 242 rtl_set_bbreg(hw, addr, MASKDWORD, data); _rtl8723be_config_bb_reg() 584 MASKDWORD, _rtl8723be_phy_config_bb_with_headerfile() 616 MASKDWORD, _rtl8723be_phy_config_bb_with_headerfile() 870 MASKDWORD); rtl8723be_phy_get_hw_reg_originalvalue() 1528 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_iqk() 1530 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_iqk() 1540 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_a_iqk() 1541 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_a_iqk() 1543 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_a_iqk() 1544 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_iqk() 1545 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_iqk() 1546 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_iqk() 1548 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); _rtl8723be_phy_path_a_iqk() 1549 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); _rtl8723be_phy_path_a_iqk() 1550 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_iqk() 1551 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_iqk() 1553 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl8723be_phy_path_a_iqk() 1555 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_iqk() 1558 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_a_iqk() 1559 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_a_iqk() 1564 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_iqk() 1567 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl8723be_phy_path_a_iqk() 1568 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl8723be_phy_path_a_iqk() 1569 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl8723be_phy_path_a_iqk() 1601 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk() 1604 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk() 1613 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_rx_iqk() 1616 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_a_rx_iqk() 1617 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_a_rx_iqk() 1620 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_a_rx_iqk() 1621 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk() 1622 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk() 1623 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk() 1625 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); _rtl8723be_phy_path_a_rx_iqk() 1626 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_rx_iqk() 1627 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_rx_iqk() 1628 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_rx_iqk() 1631 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl8723be_phy_path_a_rx_iqk() 1634 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_rx_iqk() 1637 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_a_rx_iqk() 1638 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_a_rx_iqk() 1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk() 1646 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk() 1647 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk() 1648 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk() 1672 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); _rtl8723be_phy_path_a_rx_iqk() 1676 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk() 1688 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_a_rx_iqk() 1691 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk() 1692 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_a_rx_iqk() 1693 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk() 1694 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_a_rx_iqk() 1696 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_rx_iqk() 1697 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); _rtl8723be_phy_path_a_rx_iqk() 1698 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_a_rx_iqk() 1699 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_a_rx_iqk() 1702 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); _rtl8723be_phy_path_a_rx_iqk() 1705 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_a_rx_iqk() 1708 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_a_rx_iqk() 1709 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_a_rx_iqk() 1714 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk() 1717 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk() 1718 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_a_rx_iqk() 1721 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_a_rx_iqk() 1748 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_iqk() 1750 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); _rtl8723be_phy_path_b_iqk() 1758 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_b_iqk() 1759 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_b_iqk() 1761 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_b_iqk() 1762 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_iqk() 1763 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_iqk() 1764 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_iqk() 1766 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); _rtl8723be_phy_path_b_iqk() 1767 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_iqk() 1768 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_iqk() 1769 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_iqk() 1772 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl8723be_phy_path_b_iqk() 1775 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_b_iqk() 1778 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_b_iqk() 1779 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_b_iqk() 1784 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_iqk() 1787 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_iqk() 1788 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_iqk() 1789 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_iqk() 1821 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk() 1823 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); _rtl8723be_phy_path_b_rx_iqk() 1837 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl8723be_phy_path_b_rx_iqk() 1838 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_b_rx_iqk() 1841 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_b_rx_iqk() 1842 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk() 1843 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk() 1844 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk() 1846 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); _rtl8723be_phy_path_b_rx_iqk() 1847 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_rx_iqk() 1848 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_rx_iqk() 1849 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_rx_iqk() 1852 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl8723be_phy_path_b_rx_iqk() 1854 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_b_rx_iqk() 1857 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_b_rx_iqk() 1858 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_b_rx_iqk() 1863 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk() 1865 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk() 1866 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk() 1867 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk() 1891 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); _rtl8723be_phy_path_b_rx_iqk() 1896 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk() 1908 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl8723be_phy_path_b_rx_iqk() 1911 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk() 1912 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl8723be_phy_path_b_rx_iqk() 1913 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk() 1914 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl8723be_phy_path_b_rx_iqk() 1916 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_rx_iqk() 1917 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); _rtl8723be_phy_path_b_rx_iqk() 1918 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); _rtl8723be_phy_path_b_rx_iqk() 1919 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); _rtl8723be_phy_path_b_rx_iqk() 1922 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); _rtl8723be_phy_path_b_rx_iqk() 1924 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl8723be_phy_path_b_rx_iqk() 1927 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl8723be_phy_path_b_rx_iqk() 1928 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl8723be_phy_path_b_rx_iqk() 1933 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl8723be_phy_path_b_rx_iqk() 1935 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk() 1936 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl8723be_phy_path_b_rx_iqk() 1972 MASKDWORD) >> 22) & 0x3FF; _rtl8723be_phy_path_b_fill_iqk_matrix() 2124 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); _rtl8723be_phy_iq_calibrate() 2130 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl8723be_phy_iq_calibrate() 2131 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl8723be_phy_iq_calibrate() 2132 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl8723be_phy_iq_calibrate() 2140 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2142 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2156 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2158 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2177 MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2180 MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2194 MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2197 MASKDWORD) & _rtl8723be_phy_iq_calibrate() 2207 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); _rtl8723be_phy_iq_calibrate() 2218 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); _rtl8723be_phy_iq_calibrate() 2227 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); _rtl8723be_phy_iq_calibrate() 2228 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); _rtl8723be_phy_iq_calibrate() 2315 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1); _rtl8723be_phy_set_rfpath_switch() 2317 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2); _rtl8723be_phy_set_rfpath_switch() 2359 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); rtl8723be_phy_iq_calibrate() 2461 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); rtl8723be_phy_iq_calibrate()
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H A D | dm.c | 541 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); rtl8723be_dm_false_alarm_counter_statistics() 545 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); rtl8723be_dm_false_alarm_counter_statistics() 549 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); rtl8723be_dm_false_alarm_counter_statistics() 553 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); rtl8723be_dm_false_alarm_counter_statistics() 572 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD); rtl8723be_dm_false_alarm_counter_statistics() 645 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, rtl8723be_set_iqk_matrix() 659 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, rtl8723be_set_iqk_matrix()
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H A D | rf.c | 383 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); _rtl8723be_write_ofdm_power_reg()
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H A D | reg.h | 2253 #define MASKDWORD 0xffffffff macro
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723ae/ |
H A D | phy.c | 291 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl8723e_phy_config_bb_with_headerfile() 301 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, _rtl8723e_phy_config_bb_with_headerfile() 577 ROFDM0_RXDETECTOR2, MASKDWORD); rtl8723e_phy_get_hw_reg_originalvalue() 916 MASKDWORD, 0x00255); _rtl8723e_phy_sw_rf_seting() 922 MASKDWORD, backuprf0x1a); _rtl8723e_phy_sw_rf_seting() 1043 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); _rtl8723e_phy_path_a_iqk() 1044 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); _rtl8723e_phy_path_a_iqk() 1045 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); _rtl8723e_phy_path_a_iqk() 1046 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, _rtl8723e_phy_path_a_iqk() 1050 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); _rtl8723e_phy_path_a_iqk() 1051 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); _rtl8723e_phy_path_a_iqk() 1052 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); _rtl8723e_phy_path_a_iqk() 1053 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); _rtl8723e_phy_path_a_iqk() 1056 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); _rtl8723e_phy_path_a_iqk() 1057 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl8723e_phy_path_a_iqk() 1058 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl8723e_phy_path_a_iqk() 1062 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl8723e_phy_path_a_iqk() 1063 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl8723e_phy_path_a_iqk() 1064 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl8723e_phy_path_a_iqk() 1065 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl8723e_phy_path_a_iqk() 1086 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl8723e_phy_path_b_iqk() 1087 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl8723e_phy_path_b_iqk() 1089 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl8723e_phy_path_b_iqk() 1090 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl8723e_phy_path_b_iqk() 1091 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl8723e_phy_path_b_iqk() 1092 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl8723e_phy_path_b_iqk() 1093 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl8723e_phy_path_b_iqk() 1183 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD); _rtl8723e_phy_iq_calibrate() 1200 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); _rtl8723e_phy_iq_calibrate() 1201 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); _rtl8723e_phy_iq_calibrate() 1202 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); _rtl8723e_phy_iq_calibrate() 1204 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl8723e_phy_iq_calibrate() 1205 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl8723e_phy_iq_calibrate() 1206 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl8723e_phy_iq_calibrate() 1208 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl8723e_phy_iq_calibrate() 1209 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); _rtl8723e_phy_iq_calibrate() 1213 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); _rtl8723e_phy_iq_calibrate() 1215 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); _rtl8723e_phy_iq_calibrate() 1216 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl8723e_phy_iq_calibrate() 1217 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl8723e_phy_iq_calibrate() 1218 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl8723e_phy_iq_calibrate() 1222 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1224 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1226 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1228 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1234 MASKDWORD) & 0x3FF0000) >> _rtl8723e_phy_iq_calibrate() 1237 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; _rtl8723e_phy_iq_calibrate() 1249 MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1252 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1255 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1258 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1264 MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1267 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl8723e_phy_iq_calibrate() 1271 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); _rtl8723e_phy_iq_calibrate() 1272 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); _rtl8723e_phy_iq_calibrate() 1273 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); _rtl8723e_phy_iq_calibrate() 1274 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl8723e_phy_iq_calibrate() 1275 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); _rtl8723e_phy_iq_calibrate() 1277 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); _rtl8723e_phy_iq_calibrate()
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H A D | dm.c | 183 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); rtl8723e_dm_false_alarm_counter_statistics() 186 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); rtl8723e_dm_false_alarm_counter_statistics() 190 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); rtl8723e_dm_false_alarm_counter_statistics() 689 MASKDWORD) & 0x1CC000) >> 14; rtl8723e_dm_rf_saving() 692 MASKDWORD) & BIT(3)) >> 3; rtl8723e_dm_rf_saving() 695 MASKDWORD) & 0xFF000000) >> 24; rtl8723e_dm_rf_saving() 697 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12; rtl8723e_dm_rf_saving()
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H A D | hw.c | 990 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); rtl8723e_hw_init() 991 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); rtl8723e_hw_init() 993 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); rtl8723e_hw_init() 994 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); rtl8723e_hw_init() 995 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); rtl8723e_hw_init() 996 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); rtl8723e_hw_init() 997 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); rtl8723e_hw_init() 998 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); rtl8723e_hw_init()
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H A D | rf.c | 377 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); _rtl8723e_write_ofdm_power_reg()
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H A D | reg.h | 2092 #define MASKDWORD 0xffffffff macro
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192c/ |
H A D | phy_common.c | 67 if (bitmask != MASKDWORD) { rtl92c_phy_set_bb_reg() 114 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl92c_phy_rf_serial_read() 118 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl92c_phy_rf_serial_read() 121 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92c_phy_rf_serial_read() 124 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl92c_phy_rf_serial_read() 126 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92c_phy_rf_serial_read() 165 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl92c_phy_rf_serial_write() 426 ROFDM0_RXDETECTOR2, MASKDWORD); rtl92c_phy_get_hw_reg_originalvalue() 780 MASKDWORD, 0x00255); _rtl92c_phy_sw_rf_seting() 785 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, _rtl92c_phy_sw_rf_seting() 936 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); _rtl92c_phy_path_a_iqk() 937 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); _rtl92c_phy_path_a_iqk() 938 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); _rtl92c_phy_path_a_iqk() 939 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, _rtl92c_phy_path_a_iqk() 943 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); _rtl92c_phy_path_a_iqk() 944 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); _rtl92c_phy_path_a_iqk() 945 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); _rtl92c_phy_path_a_iqk() 946 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); _rtl92c_phy_path_a_iqk() 949 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); _rtl92c_phy_path_a_iqk() 950 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl92c_phy_path_a_iqk() 951 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92c_phy_path_a_iqk() 955 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92c_phy_path_a_iqk() 956 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92c_phy_path_a_iqk() 957 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92c_phy_path_a_iqk() 958 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl92c_phy_path_a_iqk() 979 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl92c_phy_path_b_iqk() 980 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl92c_phy_path_b_iqk() 982 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92c_phy_path_b_iqk() 983 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92c_phy_path_b_iqk() 984 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92c_phy_path_b_iqk() 985 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl92c_phy_path_b_iqk() 986 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl92c_phy_path_b_iqk() 1012 MASKDWORD) >> 22) & 0x3FF; _rtl92c_phy_path_a_fill_iqk_matrix() 1052 MASKDWORD) >> 22) & 0x3FF; _rtl92c_phy_path_b_fill_iqk_matrix() 1088 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); _rtl92c_phy_save_adda_registers() 1109 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); _rtl92c_phy_reload_adda_registers() 1132 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); _rtl92c_phy_path_adda_on() 1134 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn); _rtl92c_phy_path_adda_on() 1138 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn); _rtl92c_phy_path_adda_on() 1157 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl92c_phy_path_a_standby() 1158 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl92c_phy_path_a_standby() 1159 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92c_phy_path_a_standby() 1167 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); _rtl92c_phy_pi_mode_switch() 1168 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); _rtl92c_phy_pi_mode_switch() 1250 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD); _rtl92c_phy_iq_calibrate() 1267 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); _rtl92c_phy_iq_calibrate() 1268 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); _rtl92c_phy_iq_calibrate() 1269 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); _rtl92c_phy_iq_calibrate() 1271 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl92c_phy_iq_calibrate() 1272 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl92c_phy_iq_calibrate() 1273 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl92c_phy_iq_calibrate() 1275 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl92c_phy_iq_calibrate() 1276 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); _rtl92c_phy_iq_calibrate() 1280 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); _rtl92c_phy_iq_calibrate() 1282 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); _rtl92c_phy_iq_calibrate() 1283 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92c_phy_iq_calibrate() 1284 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl92c_phy_iq_calibrate() 1285 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl92c_phy_iq_calibrate() 1289 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1291 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1293 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1295 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1301 MASKDWORD) & 0x3FF0000) >> _rtl92c_phy_iq_calibrate() 1304 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; _rtl92c_phy_iq_calibrate() 1316 MASKDWORD) & _rtl92c_phy_iq_calibrate() 1319 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1322 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1325 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1331 MASKDWORD) & _rtl92c_phy_iq_calibrate() 1334 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92c_phy_iq_calibrate() 1338 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); _rtl92c_phy_iq_calibrate() 1339 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); _rtl92c_phy_iq_calibrate() 1340 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); _rtl92c_phy_iq_calibrate() 1341 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl92c_phy_iq_calibrate() 1342 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); _rtl92c_phy_iq_calibrate() 1344 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); _rtl92c_phy_iq_calibrate()
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H A D | dm_common.c | 232 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics() 235 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics() 239 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics() 242 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); rtl92c_dm_false_alarm_counter_statistics() 762 MASKDWORD) & MASKOFDM_D; rtl92c_dm_txpower_tracking_callback_thermalmeter() 778 MASKDWORD) & MASKOFDM_D; rtl92c_dm_txpower_tracking_callback_thermalmeter() 795 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK; rtl92c_dm_txpower_tracking_callback_thermalmeter() 1006 MASKDWORD, value32); rtl92c_dm_txpower_tracking_callback_thermalmeter() 1021 MASKDWORD, rtl92c_dm_txpower_tracking_callback_thermalmeter() 1104 MASKDWORD, value32); rtl92c_dm_txpower_tracking_callback_thermalmeter() 1120 MASKDWORD, rtl92c_dm_txpower_tracking_callback_thermalmeter() 1234 MASKDWORD) & 0x1CC000) >> 14; rtl92c_dm_rf_saving() 1237 MASKDWORD) & BIT(3)) >> 3; rtl92c_dm_rf_saving() 1240 MASKDWORD) & 0xFF000000) >> 24; rtl92c_dm_rf_saving() 1242 rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & rtl92c_dm_rf_saving()
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723com/ |
H A D | phy_common.c | 62 if (bitmask != MASKDWORD) { rtl8723_phy_set_bb_reg() 105 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); rtl8723_phy_rf_serial_read() 109 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); rtl8723_phy_rf_serial_read() 112 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, rtl8723_phy_rf_serial_read() 115 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); rtl8723_phy_rf_serial_read() 117 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, rtl8723_phy_rf_serial_read() 156 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); rtl8723_phy_rf_serial_write() 315 MASKDWORD) >> 22) & 0x3FF; rtl8723_phy_path_a_fill_iqk_matrix() 351 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); rtl8723_save_adda_registers() 374 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); rtl8723_phy_reload_adda_registers() 401 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); rtl8723_phy_path_adda_on() 403 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); rtl8723_phy_path_adda_on() 408 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); rtl8723_phy_path_adda_on() 412 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); rtl8723_phy_path_adda_on() 433 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); rtl8723_phy_path_a_standby() 434 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); rtl8723_phy_path_a_standby() 435 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); rtl8723_phy_path_a_standby() 444 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); rtl8723_phy_pi_mode_switch() 445 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); rtl8723_phy_pi_mode_switch()
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/ |
H A D | phy.c | 247 if (bitmask != MASKDWORD) { rtl92d_phy_set_bb_reg() 280 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl92d_phy_rf_serial_read() 284 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl92d_phy_rf_serial_read() 287 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92d_phy_rf_serial_read() 290 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl92d_phy_rf_serial_read() 293 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92d_phy_rf_serial_read() 326 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl92d_phy_rf_serial_write() 573 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl92d_phy_config_bb_with_headerfile() 585 MASKDWORD, _rtl92d_phy_config_bb_with_headerfile() 601 MASKDWORD, _rtl92d_phy_config_bb_with_headerfile() 617 MASKDWORD, _rtl92d_phy_config_bb_with_headerfile() 872 MASKDWORD); rtl92d_phy_get_hw_reg_originalvalue() 1438 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); _rtl92d_phy_patha_iqk() 1439 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); _rtl92d_phy_patha_iqk() 1441 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk() 1442 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk() 1444 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); _rtl92d_phy_patha_iqk() 1445 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); _rtl92d_phy_patha_iqk() 1448 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk() 1449 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); _rtl92d_phy_patha_iqk() 1450 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); _rtl92d_phy_patha_iqk() 1451 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); _rtl92d_phy_patha_iqk() 1455 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl92d_phy_patha_iqk() 1458 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl92d_phy_patha_iqk() 1459 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92d_phy_patha_iqk() 1466 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_patha_iqk() 1468 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92d_phy_patha_iqk() 1470 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92d_phy_patha_iqk() 1472 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl92d_phy_patha_iqk() 1508 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); _rtl92d_phy_patha_iqk_5g_normal() 1509 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); _rtl92d_phy_patha_iqk_5g_normal() 1510 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); _rtl92d_phy_patha_iqk_5g_normal() 1511 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); _rtl92d_phy_patha_iqk_5g_normal() 1514 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); _rtl92d_phy_patha_iqk_5g_normal() 1515 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); _rtl92d_phy_patha_iqk_5g_normal() 1516 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); _rtl92d_phy_patha_iqk_5g_normal() 1517 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); _rtl92d_phy_patha_iqk_5g_normal() 1521 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl92d_phy_patha_iqk_5g_normal() 1523 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); _rtl92d_phy_patha_iqk_5g_normal() 1524 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); _rtl92d_phy_patha_iqk_5g_normal() 1529 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl92d_phy_patha_iqk_5g_normal() 1530 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92d_phy_patha_iqk_5g_normal() 1537 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal() 1539 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal() 1541 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal() 1543 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl92d_phy_patha_iqk_5g_normal() 1565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, _rtl92d_phy_patha_iqk_5g_normal() 1567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, _rtl92d_phy_patha_iqk_5g_normal() 1582 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl92d_phy_pathb_iqk() 1583 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl92d_phy_pathb_iqk() 1589 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_pathb_iqk() 1591 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92d_phy_pathb_iqk() 1593 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92d_phy_pathb_iqk() 1595 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl92d_phy_pathb_iqk() 1597 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl92d_phy_pathb_iqk() 1625 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); _rtl92d_phy_pathb_iqk_5g_normal() 1626 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); _rtl92d_phy_pathb_iqk_5g_normal() 1627 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); _rtl92d_phy_pathb_iqk_5g_normal() 1628 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); _rtl92d_phy_pathb_iqk_5g_normal() 1631 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); _rtl92d_phy_pathb_iqk_5g_normal() 1632 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); _rtl92d_phy_pathb_iqk_5g_normal() 1633 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); _rtl92d_phy_pathb_iqk_5g_normal() 1634 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); _rtl92d_phy_pathb_iqk_5g_normal() 1638 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl92d_phy_pathb_iqk_5g_normal() 1641 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); _rtl92d_phy_pathb_iqk_5g_normal() 1642 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); _rtl92d_phy_pathb_iqk_5g_normal() 1648 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); _rtl92d_phy_pathb_iqk_5g_normal() 1649 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl92d_phy_pathb_iqk_5g_normal() 1657 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal() 1659 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal() 1661 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal() 1663 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal() 1665 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl92d_phy_pathb_iqk_5g_normal() 1683 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, _rtl92d_phy_pathb_iqk_5g_normal() 1685 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, _rtl92d_phy_pathb_iqk_5g_normal() 1699 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); _rtl92d_phy_save_adda_registers() 1724 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); _rtl92d_phy_reload_adda_registers() 1752 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); _rtl92d_phy_path_adda_on() 1775 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl92d_phy_patha_standby() 1776 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); _rtl92d_phy_patha_standby() 1777 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92d_phy_patha_standby() 1788 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); _rtl92d_phy_pimode_switch() 1789 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); _rtl92d_phy_pimode_switch() 1820 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); _rtl92d_phy_iq_calibrate() 1843 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); _rtl92d_phy_iq_calibrate() 1844 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); _rtl92d_phy_iq_calibrate() 1845 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); _rtl92d_phy_iq_calibrate() 1848 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, _rtl92d_phy_iq_calibrate() 1850 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, _rtl92d_phy_iq_calibrate() 1857 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate() 1859 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate() 1862 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92d_phy_iq_calibrate() 1863 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl92d_phy_iq_calibrate() 1864 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl92d_phy_iq_calibrate() 1870 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate() 1872 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate() 1874 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl92d_phy_iq_calibrate() 1876 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl92d_phy_iq_calibrate() 1884 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate() 1886 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate() 1902 MASKDWORD) & 0x3FF0000) >> 16; _rtl92d_phy_iq_calibrate() 1904 MASKDWORD) & 0x3FF0000) >> 16; _rtl92d_phy_iq_calibrate() 1906 MASKDWORD) & 0x3FF0000) >> 16; _rtl92d_phy_iq_calibrate() 1908 MASKDWORD) & 0x3FF0000) >> 16; _rtl92d_phy_iq_calibrate() 1915 MASKDWORD) & 0x3FF0000) >> 16; _rtl92d_phy_iq_calibrate() 1917 MASKDWORD) & 0x3FF0000) >> 16; _rtl92d_phy_iq_calibrate() 1929 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl92d_phy_iq_calibrate() 1949 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); _rtl92d_phy_iq_calibrate() 1950 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); _rtl92d_phy_iq_calibrate() 1987 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); _rtl92d_phy_iq_calibrate_5g_normal() 2017 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); _rtl92d_phy_iq_calibrate_5g_normal() 2018 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); _rtl92d_phy_iq_calibrate_5g_normal() 2019 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); _rtl92d_phy_iq_calibrate_5g_normal() 2023 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate_5g_normal() 2025 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); _rtl92d_phy_iq_calibrate_5g_normal() 2028 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92d_phy_iq_calibrate_5g_normal() 2029 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); _rtl92d_phy_iq_calibrate_5g_normal() 2030 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); _rtl92d_phy_iq_calibrate_5g_normal() 2034 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2036 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2038 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2040 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2046 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2048 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2061 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2063 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2065 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2067 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2072 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2074 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl92d_phy_iq_calibrate_5g_normal() 2085 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl92d_phy_iq_calibrate_5g_normal() 2185 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ _rtl92d_phy_patha_fill_iqk_matrix() 2216 MASKDWORD)); _rtl92d_phy_patha_fill_iqk_matrix() 2244 MASKDWORD) >> 22) & 0x3FF; _rtl92d_phy_pathb_fill_iqk_matrix() 2905 MASKDWORD); rtl92d_phy_sw_chnl() 3413 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration() 3415 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration() 3469 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration() 3472 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration() 3475 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration() 3478 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, rtl92d_update_bbrf_configuration() 3505 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); rtl92d_update_bbrf_configuration() 3506 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); rtl92d_update_bbrf_configuration()
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H A D | dm.c | 170 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); rtl92d_dm_false_alarm_counter_statistics() 173 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); rtl92d_dm_false_alarm_counter_statistics() 175 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); rtl92d_dm_false_alarm_counter_statistics() 178 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); rtl92d_dm_false_alarm_counter_statistics() 713 MASKDWORD) & MASKCCK; rtl92d_bandtype_2_4G() 872 MASKDWORD) & MASKOFDM_D; rtl92d_dm_txpower_tracking_callback_thermalmeter() 886 MASKDWORD) & MASKOFDM_D; rtl92d_dm_txpower_tracking_callback_thermalmeter() 1067 MASKDWORD, value32); rtl92d_dm_txpower_tracking_callback_thermalmeter() 1079 MASKDWORD, rtl92d_dm_txpower_tracking_callback_thermalmeter() 1180 MASKDWORD, value32); rtl92d_dm_txpower_tracking_callback_thermalmeter() 1190 MASKDWORD, rtl92d_dm_txpower_tracking_callback_thermalmeter() 1205 rtl_get_bbreg(hw, 0xc80, MASKDWORD), rtl92d_dm_txpower_tracking_callback_thermalmeter() 1206 rtl_get_bbreg(hw, 0xc94, MASKDWORD), rtl92d_dm_txpower_tracking_callback_thermalmeter()
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H A D | rf.c | 363 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); _rtl92d_write_ofdm_power_reg()
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H A D | hw.c | 1038 0x2a, MASKDWORD); rtl92de_hw_init()
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ee/ |
H A D | phy.c | 91 if (bitmask != MASKDWORD) { rtl92ee_phy_set_bb_reg() 176 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl92ee_phy_rf_serial_read() 180 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl92ee_phy_rf_serial_read() 183 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92ee_phy_rf_serial_read() 186 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl92ee_phy_rf_serial_read() 223 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl92ee_phy_rf_serial_write() 324 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); _rtl92ee_config_rf_reg() 333 MASKDWORD); _rtl92ee_config_rf_reg() 343 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); _rtl92ee_config_rf_reg() 355 MASKDWORD); _rtl92ee_config_rf_reg() 399 rtl_set_bbreg(hw, addr, MASKDWORD , data); _rtl92ee_config_bb_reg() 762 rtl_set_bbreg(hw, array[i], MASKDWORD, phy_config_bb_with_hdr_file() 792 MASKDWORD, phy_config_bb_with_hdr_file() 1063 ROFDM0_RXDETECTOR2, MASKDWORD); rtl92ee_phy_get_hw_reg_originalvalue() 1971 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_iqk() 1973 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_iqk() 1975 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_a_iqk() 1976 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_iqk() 1977 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_iqk() 1978 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_iqk() 1980 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); _rtl92ee_phy_path_a_iqk() 1981 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); _rtl92ee_phy_path_a_iqk() 1984 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl92ee_phy_path_a_iqk() 1987 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl92ee_phy_path_a_iqk() 1988 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_a_iqk() 1992 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92ee_phy_path_a_iqk() 1993 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl92ee_phy_path_a_iqk() 1994 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl92ee_phy_path_a_iqk() 2012 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_iqk() 2014 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_iqk() 2016 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_iqk() 2017 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_iqk() 2019 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_iqk() 2020 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_iqk() 2021 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_b_iqk() 2022 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_iqk() 2024 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); _rtl92ee_phy_path_b_iqk() 2025 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); _rtl92ee_phy_path_b_iqk() 2028 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); _rtl92ee_phy_path_b_iqk() 2031 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_b_iqk() 2032 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_b_iqk() 2036 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl92ee_phy_path_b_iqk() 2037 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl92ee_phy_path_b_iqk() 2038 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl92ee_phy_path_b_iqk() 2057 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk() 2069 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_rx_iqk() 2072 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_path_a_rx_iqk() 2073 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_a_rx_iqk() 2076 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_a_rx_iqk() 2077 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk() 2078 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk() 2079 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk() 2081 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_a_rx_iqk() 2082 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); _rtl92ee_phy_path_a_rx_iqk() 2085 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl92ee_phy_path_a_rx_iqk() 2088 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_a_rx_iqk() 2089 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_a_rx_iqk() 2094 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk() 2095 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk() 2096 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk() 2104 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk() 2111 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); _rtl92ee_phy_path_a_rx_iqk() 2114 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk() 2127 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_rx_iqk() 2130 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_a_rx_iqk() 2133 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk() 2134 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_a_rx_iqk() 2135 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk() 2136 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_a_rx_iqk() 2138 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_a_rx_iqk() 2139 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); _rtl92ee_phy_path_a_rx_iqk() 2142 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); _rtl92ee_phy_path_a_rx_iqk() 2144 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_a_rx_iqk() 2145 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_a_rx_iqk() 2149 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk() 2150 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_a_rx_iqk() 2154 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_a_rx_iqk() 2173 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk() 2184 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_rx_iqk() 2187 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_path_b_rx_iqk() 2188 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_b_rx_iqk() 2191 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk() 2192 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk() 2193 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_b_rx_iqk() 2194 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk() 2196 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_b_rx_iqk() 2197 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); _rtl92ee_phy_path_b_rx_iqk() 2200 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl92ee_phy_path_b_rx_iqk() 2203 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_b_rx_iqk() 2204 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_b_rx_iqk() 2209 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk() 2210 reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk() 2211 reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk() 2219 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk() 2226 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); _rtl92ee_phy_path_b_rx_iqk() 2229 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk() 2241 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_path_b_rx_iqk() 2244 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_path_b_rx_iqk() 2247 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk() 2248 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk() 2249 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); _rtl92ee_phy_path_b_rx_iqk() 2250 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); _rtl92ee_phy_path_b_rx_iqk() 2252 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); _rtl92ee_phy_path_b_rx_iqk() 2253 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); _rtl92ee_phy_path_b_rx_iqk() 2256 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); _rtl92ee_phy_path_b_rx_iqk() 2258 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); _rtl92ee_phy_path_b_rx_iqk() 2259 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl92ee_phy_path_b_rx_iqk() 2263 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk() 2264 reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk() 2265 reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); _rtl92ee_phy_path_b_rx_iqk() 2268 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl92ee_phy_path_b_rx_iqk() 2293 MASKDWORD) >> 22) & 0x3FF; _rtl92ee_phy_path_a_fill_iqk_matrix() 2338 MASKDWORD) >> 22) & 0x3FF; _rtl92ee_phy_path_b_fill_iqk_matrix() 2378 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); _rtl92ee_phy_save_adda_registers() 2400 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); _rtl92ee_phy_reload_adda_registers() 2423 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0fc01616); _rtl92ee_phy_path_adda_on() 2425 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); _rtl92ee_phy_path_adda_on() 2429 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); _rtl92ee_phy_path_adda_on() 2440 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl92ee_phy_path_a_standby() 2442 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl92ee_phy_path_a_standby() 2561 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); _rtl92ee_phy_iq_calibrate() 2562 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); _rtl92ee_phy_iq_calibrate() 2563 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); _rtl92ee_phy_iq_calibrate() 2574 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_iq_calibrate() 2575 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_iq_calibrate() 2576 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_iq_calibrate() 2586 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2589 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2606 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2610 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2628 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl92ee_phy_iq_calibrate() 2629 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl92ee_phy_iq_calibrate() 2630 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl92ee_phy_iq_calibrate() 2639 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2643 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2659 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2663 MASKDWORD) & 0x3FF0000) _rtl92ee_phy_iq_calibrate() 2679 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); _rtl92ee_phy_iq_calibrate() 2704 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); _rtl92ee_phy_iq_calibrate() 2705 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); _rtl92ee_phy_iq_calibrate()
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H A D | dm.c | 164 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); rtl92ee_dm_false_alarm_counter_statistics() 168 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); rtl92ee_dm_false_alarm_counter_statistics() 172 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); rtl92ee_dm_false_alarm_counter_statistics() 176 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); rtl92ee_dm_false_alarm_counter_statistics() 186 ret_value = rtl_get_bbreg(hw, DM_REG_SC_CNT_11N, MASKDWORD); rtl92ee_dm_false_alarm_counter_statistics() 199 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD); rtl92ee_dm_false_alarm_counter_statistics()
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H A D | reg.h | 2200 #define MASKDWORD 0xffffffff macro
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8188ee/ |
H A D | phy.c | 92 if (bitmask != MASKDWORD) { rtl88e_phy_set_bb_reg() 182 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl88e_phy_rf_serial_read() 186 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl88e_phy_rf_serial_read() 189 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl88e_phy_rf_serial_read() 192 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl88e_phy_rf_serial_read() 229 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl88e_phy_rf_serial_write() 362 rtl_set_bbreg(hw, addr, MASKDWORD, data); _rtl8188e_config_bb_reg() 479 rtl_set_bbreg(hw, array_table[i], MASKDWORD, handle_branch2() 504 MASKDWORD, handle_branch2() 840 MASKDWORD); rtl88e_phy_get_hw_reg_originalvalue() 1389 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); _rtl88e_phy_path_a_iqk() 1390 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); _rtl88e_phy_path_a_iqk() 1391 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); _rtl88e_phy_path_a_iqk() 1392 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); _rtl88e_phy_path_a_iqk() 1394 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); _rtl88e_phy_path_a_iqk() 1395 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); _rtl88e_phy_path_a_iqk() 1396 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); _rtl88e_phy_path_a_iqk() 1400 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl88e_phy_path_a_iqk() 1401 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); _rtl88e_phy_path_a_iqk() 1402 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); _rtl88e_phy_path_a_iqk() 1403 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); _rtl88e_phy_path_a_iqk() 1417 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); _rtl88e_phy_path_b_iqk() 1418 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); _rtl88e_phy_path_b_iqk() 1420 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); _rtl88e_phy_path_b_iqk() 1421 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); _rtl88e_phy_path_b_iqk() 1422 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); _rtl88e_phy_path_b_iqk() 1423 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); _rtl88e_phy_path_b_iqk() 1424 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); _rtl88e_phy_path_b_iqk() 1446 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl88e_phy_path_a_rx_iqk() 1451 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl88e_phy_path_a_rx_iqk() 1454 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); _rtl88e_phy_path_a_rx_iqk() 1455 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); _rtl88e_phy_path_a_rx_iqk() 1458 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); _rtl88e_phy_path_a_rx_iqk() 1459 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); _rtl88e_phy_path_a_rx_iqk() 1460 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); _rtl88e_phy_path_a_rx_iqk() 1461 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); _rtl88e_phy_path_a_rx_iqk() 1464 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl88e_phy_path_a_rx_iqk() 1466 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl88e_phy_path_a_rx_iqk() 1467 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl88e_phy_path_a_rx_iqk() 1471 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl88e_phy_path_a_rx_iqk() 1472 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk() 1473 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk() 1485 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); _rtl88e_phy_path_a_rx_iqk() 1488 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); _rtl88e_phy_path_a_rx_iqk() 1493 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); _rtl88e_phy_path_a_rx_iqk() 1496 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); _rtl88e_phy_path_a_rx_iqk() 1499 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); _rtl88e_phy_path_a_rx_iqk() 1500 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); _rtl88e_phy_path_a_rx_iqk() 1501 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); _rtl88e_phy_path_a_rx_iqk() 1502 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); _rtl88e_phy_path_a_rx_iqk() 1505 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); _rtl88e_phy_path_a_rx_iqk() 1507 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); _rtl88e_phy_path_a_rx_iqk() 1508 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); _rtl88e_phy_path_a_rx_iqk() 1512 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); _rtl88e_phy_path_a_rx_iqk() 1513 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk() 1514 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); _rtl88e_phy_path_a_rx_iqk() 1515 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); _rtl88e_phy_path_a_rx_iqk() 1535 MASKDWORD) >> 22) & 0x3FF; _rtl88e_phy_path_a_fill_iqk_matrix() 1571 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); _rtl88e_phy_save_adda_registers() 1592 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); _rtl88e_phy_reload_adda_registers() 1615 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); _rtl88e_phy_path_adda_on() 1617 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); _rtl88e_phy_path_adda_on() 1621 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); _rtl88e_phy_path_adda_on() 1640 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); _rtl88e_phy_path_a_standby() 1641 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl88e_phy_path_a_standby() 1642 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl88e_phy_path_a_standby() 1650 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); _rtl88e_phy_pi_mode_switch() 1651 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); _rtl88e_phy_pi_mode_switch() 1756 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); _rtl88e_phy_iq_calibrate() 1757 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); _rtl88e_phy_iq_calibrate() 1758 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); _rtl88e_phy_iq_calibrate() 1766 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); _rtl88e_phy_iq_calibrate() 1767 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); _rtl88e_phy_iq_calibrate() 1771 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); _rtl88e_phy_iq_calibrate() 1773 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); _rtl88e_phy_iq_calibrate() 1775 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); _rtl88e_phy_iq_calibrate() 1776 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); _rtl88e_phy_iq_calibrate() 1777 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); _rtl88e_phy_iq_calibrate() 1783 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1785 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1796 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1798 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1818 MASKDWORD) & _rtl88e_phy_iq_calibrate() 1821 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1824 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1827 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1833 MASKDWORD) & _rtl88e_phy_iq_calibrate() 1836 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & _rtl88e_phy_iq_calibrate() 1841 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); _rtl88e_phy_iq_calibrate() 1854 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); _rtl88e_phy_iq_calibrate() 1856 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); _rtl88e_phy_iq_calibrate() 1857 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); _rtl88e_phy_iq_calibrate() 1858 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); _rtl88e_phy_iq_calibrate()
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H A D | dm.c | 189 MASKDWORD, value32); rtl88e_set_iqk_matrix() 199 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, rtl88e_set_iqk_matrix() 214 MASKDWORD, ofdmswing_table[ofdm_index]); rtl88e_set_iqk_matrix() 222 MASKDWORD, ofdmswing_table[ofdm_index]); rtl88e_set_iqk_matrix() 381 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics() 385 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics() 389 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics() 393 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics() 402 ret_value = rtl_get_bbreg(hw, REG_SC_CNT, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics() 415 ret_value = rtl_get_bbreg(hw, RCCK0_CCA_CNT, MASKDWORD); rtl88e_dm_false_alarm_counter_statistics() 925 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & dm_txpower_track_cb_therm() 940 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK; dm_txpower_track_cb_therm() 1324 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); rtl88e_dm_rx_hw_antena_div_init() 1326 MASKDWORD, value32 | (BIT(23) | BIT(25))); rtl88e_dm_rx_hw_antena_div_init() 1333 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); rtl88e_dm_rx_hw_antena_div_init() 1346 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); rtl88e_dm_trx_hw_antenna_div_init() 1347 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD, rtl88e_dm_trx_hw_antenna_div_init() 1355 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); rtl88e_dm_trx_hw_antenna_div_init() 1382 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); rtl88e_dm_fast_training_init() 1384 MASKDWORD, value32 | (BIT(23) | BIT(25))); rtl88e_dm_fast_training_init() 1385 value32 = rtl_get_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, MASKDWORD); rtl88e_dm_fast_training_init() 1387 MASKDWORD, value32 | (BIT(16) | BIT(17))); rtl88e_dm_fast_training_init() 1391 MASKDWORD, 0); rtl88e_dm_fast_training_init() 1400 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); rtl88e_dm_fast_training_init() 1604 MASKDWORD, value32); rtl88e_set_next_mac_address_target() 1629 MASKDWORD, value32); rtl88e_set_next_mac_address_target()
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H A D | rf.c | 380 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); _rtl88e_write_ofdm_power_reg()
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H A D | reg.h | 2238 #define MASKDWORD 0xffffffff macro
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/ |
H A D | rf.c | 129 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval); rtl8821ae_phy_rf6052_set_cck_txpower() 136 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval); rtl8821ae_phy_rf6052_set_cck_txpower() 362 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); _rtl8821ae_write_ofdm_power_reg()
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H A D | phy.c | 144 if (bitmask != MASKDWORD) { rtl8821ae_phy_set_bb_reg() 294 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl8821ae_phy_rf_serial_write() 743 rtl_set_bbreg(hw, addr, MASKDWORD, data); _rtl8821ae_config_bb_reg() 1826 rtl_set_bbreg(hw, v1, MASKDWORD, v2); _rtl8821ae_phy_config_bb_with_headerfile() 1847 rtl_set_bbreg(hw, v1, MASKDWORD, _rtl8821ae_phy_config_bb_with_headerfile() 2180 ROFDM0_RXDETECTOR2, MASKDWORD); rtl8821ae_phy_get_hw_reg_originalvalue()
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H A D | hw.c | 1812 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0); _rtl8812ae_bb8812_config_1t() 1814 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0); _rtl8812ae_bb8812_config_1t() 1815 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0); _rtl8812ae_bb8812_config_1t()
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H A D | reg.h | 2340 #define MASKDWORD 0xffffffff macro
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192se/ |
H A D | phy.c | 84 if (bitmask != MASKDWORD) { rtl92s_phy_set_bb_reg() 113 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); _rtl92s_phy_rf_serial_read() 118 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); _rtl92s_phy_rf_serial_read() 123 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, _rtl92s_phy_rf_serial_read() 128 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); _rtl92s_phy_rf_serial_read() 131 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong | _rtl92s_phy_rf_serial_read() 173 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); _rtl92s_phy_rf_serial_write() 844 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD, _rtl92s_phy_config_bb() 849 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD, _rtl92s_phy_config_bb() 1133 MASKDWORD); rtl92s_phy_get_hw_reg_originalvalue()
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H A D | dm.c | 414 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); _rtl92s_dm_false_alarm_counter_statistics() 417 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); _rtl92s_dm_false_alarm_counter_statistics() 420 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); _rtl92s_dm_false_alarm_counter_statistics() 428 ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD); _rtl92s_dm_false_alarm_counter_statistics()
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ce/ |
H A D | hw.c | 995 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); rtl92ce_hw_init() 996 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); rtl92ce_hw_init() 998 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); rtl92ce_hw_init() 999 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); rtl92ce_hw_init() 1000 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); rtl92ce_hw_init() 1001 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); rtl92ce_hw_init() 1002 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); rtl92ce_hw_init() 1003 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); rtl92ce_hw_init()
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H A D | phy.c | 206 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl92ce_phy_config_bb_with_headerfile() 216 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, _rtl92ce_phy_config_bb_with_headerfile()
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H A D | rf.c | 369 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal); _rtl92c_write_ofdm_power_reg()
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/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192cu/ |
H A D | phy.c | 196 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, _rtl92cu_phy_config_bb_with_headerfile() 206 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, _rtl92cu_phy_config_bb_with_headerfile()
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H A D | rf.c | 357 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal); _rtl92c_write_ofdm_power_reg()
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H A D | hw.c | 1027 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); rtl92cu_hw_init() 1028 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); rtl92cu_hw_init()
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/linux-4.1.27/drivers/net/wireless/rtlwifi/btcoexist/ |
H A D | halbtcoutsrc.c | 515 if (bit_mask != MASKDWORD) {/*if not "double word" write*/ halbtc_bitmask_write_1byte()
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/linux-4.1.27/drivers/net/wireless/rtlwifi/ |
H A D | wifi.h | 46 #define MASKDWORD 0xffffffff macro 62 #define MASKDWORD 0xffffffff macro
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H A D | core.c | 92 rtl_set_bbreg(hw, addr, MASKDWORD, data); rtl_bb_delay()
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