Home
last modified time | relevance | path

Searched refs:IOMEM (Results 1 – 73 of 73) sorted by relevance

/linux-4.1.27/arch/arm/mach-omap1/include/mach/
Domap1510.h58 #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
59 #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
60 #define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
61 #define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
62 #define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
63 #define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
66 #define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
67 #define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
70 #define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
71 #define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
[all …]
Dhardware.h76 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
126 #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
/linux-4.1.27/arch/arm/mach-spear/include/mach/
Dspear.h22 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
29 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
33 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
50 #define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000)
55 #define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)
58 #define VA_SYSRAM0_BASE IOMEM(0xF9800000)
62 #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000)
64 #define VA_UART_BASE IOMEM(0xFD000000)
67 #define VA_MISC_BASE IOMEM(0xFD700000)
70 #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000)
[all …]
/linux-4.1.27/arch/arm/mach-omap1/
Dfpga.h31 #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
32 #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
33 #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
34 #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
35 #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
36 #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
37 #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
Dboard-ams-delta.c528 .membase = IOMEM(MODEM_VIRT),
/linux-4.1.27/arch/arm/mach-ebsa110/
Dcore.h34 #define PIT_BASE IOMEM(0xfc000000) /* trick 0 */
35 #define SOFT_BASE IOMEM(0xfd000000) /* trick 1 */
36 #define IRQ_MASK IOMEM(0xfe000000) /* trick 3 - read */
37 #define IRQ_MSET IOMEM(0xfe000000) /* trick 3 - write */
38 #define IRQ_STAT IOMEM(0xff000000) /* trick 4 - read */
39 #define IRQ_MCLR IOMEM(0xff000000) /* trick 4 - write */
/linux-4.1.27/arch/arm/mach-shmobile/
Dclock-sh73a0.c24 #define FRQCRA IOMEM(0xe6150000)
25 #define FRQCRB IOMEM(0xe6150004)
26 #define FRQCRD IOMEM(0xe61500e4)
27 #define VCLKCR1 IOMEM(0xe6150008)
28 #define VCLKCR2 IOMEM(0xe615000C)
29 #define VCLKCR3 IOMEM(0xe615001C)
30 #define ZBCKCR IOMEM(0xe6150010)
31 #define FLCKCR IOMEM(0xe6150014)
32 #define SD0CKCR IOMEM(0xe6150074)
33 #define SD1CKCR IOMEM(0xe6150078)
[all …]
Dsmp-sh73a0.c28 #define WUPCR IOMEM(0xe6151010)
29 #define SRESCR IOMEM(0xe6151018)
30 #define PSTR IOMEM(0xe6151040)
31 #define SBAR IOMEM(0xe6180020)
32 #define APARMBAREA IOMEM(0xe6f10020)
63 shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); in sh73a0_smp_prepare_cpus()
Dclock-r8a7740.c42 #define FRQCRA IOMEM(0xe6150000)
43 #define FRQCRB IOMEM(0xe6150004)
44 #define VCLKCR1 IOMEM(0xE6150008)
45 #define VCLKCR2 IOMEM(0xE615000c)
46 #define FRQCRC IOMEM(0xe61500e0)
47 #define FSIACKCR IOMEM(0xe6150018)
48 #define PLLC01CR IOMEM(0xe6150028)
50 #define SUBCKCR IOMEM(0xe6150080)
51 #define USBCKCR IOMEM(0xe615008c)
53 #define MSTPSR0 IOMEM(0xe6150030)
[all …]
Dclock-r8a7778.c41 #define MSTPCR0 IOMEM(0xffc80030)
42 #define MSTPCR1 IOMEM(0xffc80034)
43 #define MSTPCR3 IOMEM(0xffc8003c)
44 #define MSTPSR1 IOMEM(0xffc80044)
45 #define MSTPSR4 IOMEM(0xffc80048)
46 #define MSTPSR6 IOMEM(0xffc8004c)
47 #define MSTPCR4 IOMEM(0xffc80050)
48 #define MSTPCR5 IOMEM(0xffc80054)
49 #define MSTPCR6 IOMEM(0xffc80058)
Dsetup-r8a7779.c74 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
75 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
76 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
77 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
78 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
80 #define INT2NTSR0 IOMEM(0xfe700060)
81 #define INT2NTSR1 IOMEM(0xfe700064)
663 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); in r8a7779_add_standard_devices()
Dintc-sh73a0.c257 #define PINTER0_VIRT IOMEM(0xe69000a0)
258 #define PINTER1_VIRT IOMEM(0xe69000a4)
259 #define PINTRR0 IOMEM(0xe69000d0)
260 #define PINTRR1 IOMEM(0xe69000d4)
312 void __iomem *gic_dist_base = IOMEM(0xf0001000); in sh73a0_init_irq()
313 void __iomem *gic_cpu_base = IOMEM(0xf0000100); in sh73a0_init_irq()
Dsmp-r8a7779.c32 #define AVECR IOMEM(0xfe700040)
108 shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); in r8a7779_smp_prepare_cpus()
Dclock-r8a7779.c49 #define MSTPCR0 IOMEM(0xffc80030)
50 #define MSTPCR1 IOMEM(0xffc80034)
51 #define MSTPCR3 IOMEM(0xffc8003c)
52 #define MSTPSR1 IOMEM(0xffc80044)
Dboard-kzm9g.c242 .phy = IOMEM(0xe60781e0), /* USBPHYINT */
243 .cr2 = IOMEM(0xe605810c), /* USBCR2 */
881 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); in kzm_init()
896 #define RESCNT2 IOMEM(0xe6188020) in kzm9g_restart()
Dboard-armadillo800eva.c153 #define USBCR1 IOMEM(0xe605810a)
1224 #define GPIO_PORT7CR IOMEM(0xe6050007)
1225 #define GPIO_PORT8CR IOMEM(0xe6050008)
1314 l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff); in eva_init()
1344 #define RESCNT2 IOMEM(0xe6188020)
Dpm-r8a7740.c18 #define SYSC_BASE IOMEM(0xe6180000)
Dsetup-sh73a0.c751 #define SRCR2 IOMEM(0xe61580b0)
792 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); in sh73a0_generic_init()
Dsetup-r8a7740.c840 l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff); in r8a7740_generic_init()
/linux-4.1.27/arch/arm/mach-ep93xx/
Dts72xx.h17 #define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000)
29 #define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000)
37 #define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000)
44 #define TS72XX_RTC_INDEX_VIRT_BASE IOMEM(0xfebf9000)
48 #define TS72XX_RTC_DATA_VIRT_BASE IOMEM(0xfebf8000)
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
Daddr-map.h23 #define PERIPH_VIRT IOMEM(0xf2000000)
31 #define SMEMC_VIRT IOMEM(0xf6000000)
38 #define DMEMC_VIRT IOMEM(0xf6100000)
50 #define IMEMC_VIRT IOMEM(0xfe000000)
Dpalmtx.h76 #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000)
89 #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000)
90 #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000)
Dzeus.h71 #define ZEUS_CPLD IOMEM(0xf0000000)
79 #define ZEUS_PC104IO IOMEM(0xf1000000)
Dlpd270.h16 #define LPD270_CPLD_VIRT IOMEM(0xf0000000)
Dsmemc.h16 #define SMEMC_VIRT IOMEM(0xf6000000)
Dballoon3.h28 #define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */
Dhardware.h40 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
/linux-4.1.27/arch/arm/mach-omap2/
Diomap.h34 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
37 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
40 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
43 #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
46 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
49 #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
/linux-4.1.27/arch/arm/mach-tegra/
Diomap.h110 #define IO_IRAM_VIRT IOMEM(0xFE400000)
114 #define IO_CPU_VIRT IOMEM(0xFE440000)
118 #define IO_PPSB_VIRT IOMEM(0xFE200000)
122 #define IO_APB_VIRT IOMEM(0xFE000000)
/linux-4.1.27/arch/arm/mach-netx/include/mach/
Dnetx-regs.h118 #define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
188 #define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
233 #define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs))
243 #define NETX_MIIMU IOMEM(NETX_VA_MIIMU)
320 #define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs))
337 #define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs))
358 #define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs))
428 #define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs))
Dhardware.h36 #define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
/linux-4.1.27/arch/arm/mach-dove/include/mach/
Ddove.h28 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
41 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
45 #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
49 #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
/linux-4.1.27/arch/arm/include/asm/
Dv7m.h4 #define V7M_SCS_ICTR IOMEM(0xe000e004)
7 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
Dassembler.h30 #define IOMEM(x) (x) macro
Dio.h173 #define IOMEM(x) ((void __force __iomem *)(x)) macro
/linux-4.1.27/arch/arm/mach-mmp/include/mach/
Daddr-map.h21 #define APB_VIRT_BASE IOMEM(0xfe000000)
25 #define AXI_VIRT_BASE IOMEM(0xfe200000)
/linux-4.1.27/arch/arm/mach-ep93xx/include/mach/
Dep93xx-regs.h22 #define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
29 #define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
/linux-4.1.27/arch/arm/mach-rpc/include/mach/
Dhardware.h33 #define EASI_BASE IOMEM(0xe5000000)
37 #define IO_BASE IOMEM(0xe0000000)
/linux-4.1.27/arch/arm/mach-imx/
Dmx31.h79 #define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
95 #define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
99 #define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
119 #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
Dhardware.h104 #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
Dmx1.h78 #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
Dmx21.h99 #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
Dmx35.h118 #define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
Dmach-kzm_arm11_01.c44 #define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
Dmx27.h128 #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
/linux-4.1.27/arch/arm/mach-cns3xxx/
Dcore.c93 gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), in cns3xxx_init_irq()
94 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); in cns3xxx_init_irq()
99 u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); in cns3xxx_power_off()
251 cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); in cns3xxx_timer_init()
378 u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); in cns3xxx_init()
Ddevices.c100 u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); in cns3xxx_sdhci_init()
/linux-4.1.27/arch/arm/mach-sa1100/include/mach/
Dhardware.h35 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
50 #define __MREG(x) IOMEM(io_p2v(x))
Duncompress.h11 #define IOMEM(x) (x) macro
Dsimpad.h90 #define CS3_BASE IOMEM(0xf1000000)
/linux-4.1.27/arch/arm/mach-u300/
Dcore.c59 #define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
62 #define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
97 #define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
104 #define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
/linux-4.1.27/arch/arm/mach-mv78xx0/include/mach/
Dmv78xx0.h44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000)
/linux-4.1.27/arch/arm/mach-orion5x/include/mach/
Dorion5x.h40 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000)
56 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
/linux-4.1.27/arch/arm/mach-realview/include/mach/
Dhardware.h40 #define __io_address(n) IOMEM(IO_ADDRESS(n))
/linux-4.1.27/arch/arm/mach-ks8695/include/mach/
Dhardware.h36 #define KS8695_IO_VA IOMEM(0xF0000000)
/linux-4.1.27/arch/arm/mach-ux500/
Ddb8500-regs.h186 #define UX500_VIRT_ROM IOMEM(0xf0000000)
193 #define __io_address(n) IOMEM(IO_ADDRESS(n))
/linux-4.1.27/arch/arm/mach-lpc32xx/include/mach/
Dhardware.h28 #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
/linux-4.1.27/arch/arm/mach-davinci/include/mach/
Dhardware.h31 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
Duncompress.h28 #define IOMEM(x) ((void __force __iomem *)(x)) macro
/linux-4.1.27/arch/arm/mach-gemini/include/mach/
Dhardware.h72 #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
/linux-4.1.27/arch/arm/mach-clps711x/include/mach/
Dhardware.h27 #define CLPS711X_VIRT_BASE IOMEM(0xfeff0000)
/linux-4.1.27/drivers/gpio/
Dgpio-zevio.c70 return readl(IOMEM(c->chip.regs + section_offset + port_offset)); in zevio_gpio_port_get()
77 writel(val, IOMEM(c->chip.regs + section_offset + port_offset)); in zevio_gpio_port_set()
/linux-4.1.27/arch/arm/plat-omap/
Dsram.c58 omap_sram_ceil = IOMEM(new_ceil); in omap_sram_push_address()
/linux-4.1.27/arch/arm/mach-spear/
Dplatsmp.c37 static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
/linux-4.1.27/arch/arm/mach-ixp4xx/include/mach/
Dixp4xx-regs.h46 #define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000)
54 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
61 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
/linux-4.1.27/drivers/input/mouse/
Drpcmouse.c45 b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70); in rpcmouse_irq()
/linux-4.1.27/arch/arm/mach-iop32x/
Dglantank.c183 __raw_writeb(0x01, IOMEM(0xfe8d0004)); in glantank_power_off()
/linux-4.1.27/arch/arm/mach-integrator/
Dpci_v3.c58 #define PCI_MEMORY_VADDR IOMEM(0xe8000000)
59 #define PCI_CONFIG_VADDR IOMEM(0xec000000)
/linux-4.1.27/arch/hexagon/include/asm/
Dio.h38 #define IOMEM(x) ((void __force __iomem *)(x)) macro
/linux-4.1.27/arch/arm/mach-clps711x/
Dboard-p720t.c58 #define SYSPLD_PHYS_BASE IOMEM(CS1_PHYS_BASE)
/linux-4.1.27/arch/arm/mach-orion5x/
Dts78xx-setup.c39 #define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
/linux-4.1.27/arch/mips/alchemy/common/
Dclock.c107 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x)))) macro
294 void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR); in alchemy_clk_setup_mem()
/linux-4.1.27/drivers/char/hw_random/
DKconfig26 tristate "Timer IOMEM HW Random Number Generator support"