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Searched refs:HDLC_ENCODING_DIFF_BIPHASE_LEVEL (Results 1 – 4 of 4) sorted by relevance

/linux-4.1.27/include/uapi/linux/
Dsynclink.h109 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 macro
/linux-4.1.27/drivers/tty/
Dsynclink_gt.c4322 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4395 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4454 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: in sync_mode()
Dsynclink.c4766 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4841 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
5018 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
Dsynclinkmp.c4587 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */ in hdlc_mode()