Searched refs:GIC_DIST_ENABLE_SET (Results 1 – 6 of 6) sorted by relevance
49 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { in gic_configure_irq()66 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); in gic_configure_irq()113 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); in gic_cpu_config()
162 gic_poke_irq(d, GIC_DIST_ENABLE_SET); in gic_unmask_irq()185 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; in gic_irq_set_irqchip_state()209 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); in gic_irq_get_irqchip_state()473 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_dist_save()514 dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_dist_restore()537 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_cpu_save()563 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_cpu_restore()
109 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + in hip04_unmask_irq()
98 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in prcmu_gic_pending_irq()152 GIC_DIST_ENABLE_SET + (i + 1) * 4); in prcmu_copy_gic_settings()
33 #define GIC_DIST_ENABLE_SET 0x100 macro
336 .base = GIC_DIST_ENABLE_SET,