Searched refs:FLD_VAL (Results 1 - 9 of 9) sorted by relevance

/linux-4.1.27/drivers/video/fbdev/omap2/dss/
H A Dhdmi_wp.c124 l |= FLD_VAL(video_fmt->y_res, 31, 16); hdmi_wp_video_config_format()
125 l |= FLD_VAL(video_fmt->x_res, 15, 0); hdmi_wp_video_config_format()
155 timing_h |= FLD_VAL(timings->hbp, 31, 20); hdmi_wp_video_config_timing()
156 timing_h |= FLD_VAL(timings->hfp, 19, 8); hdmi_wp_video_config_timing()
157 timing_h |= FLD_VAL(timings->hsw, 7, 0); hdmi_wp_video_config_timing()
160 timing_v |= FLD_VAL(timings->vbp, 31, 20); hdmi_wp_video_config_timing()
161 timing_v |= FLD_VAL(timings->vfp, 19, 8); hdmi_wp_video_config_timing()
162 timing_v |= FLD_VAL(timings->vsw, 7, 0); hdmi_wp_video_config_timing()
H A Ddispc.c653 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) dispc_ovl_set_scale_coef()
654 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) dispc_ovl_set_scale_coef()
655 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) dispc_ovl_set_scale_coef()
656 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); dispc_ovl_set_scale_coef()
657 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) dispc_ovl_set_scale_coef()
658 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) dispc_ovl_set_scale_coef()
659 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) dispc_ovl_set_scale_coef()
660 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); dispc_ovl_set_scale_coef()
675 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) dispc_ovl_set_scale_coef()
676 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); dispc_ovl_set_scale_coef()
689 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) dispc_ovl_write_color_conv_coef()
749 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); dispc_ovl_set_pos()
757 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); dispc_ovl_set_input_size()
772 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); dispc_ovl_set_output_size()
1088 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | dispc_mgr_set_cpr_coef()
1089 FLD_VAL(coefs->rb, 9, 0); dispc_mgr_set_cpr_coef()
1090 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | dispc_mgr_set_cpr_coef()
1091 FLD_VAL(coefs->gb, 9, 0); dispc_mgr_set_cpr_coef()
1092 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | dispc_mgr_set_cpr_coef()
1093 FLD_VAL(coefs->bb, 9, 0); dispc_mgr_set_cpr_coef()
1129 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | dispc_mgr_set_size()
1130 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); dispc_mgr_set_size()
1235 FLD_VAL(high, hi_start, hi_end) | dispc_ovl_set_fifo_threshold()
1236 FLD_VAL(low, lo_start, lo_end)); dispc_ovl_set_fifo_threshold()
1324 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); dispc_ovl_set_mflag_threshold()
1378 val = FLD_VAL(vinc, vinc_start, vinc_end) | dispc_ovl_set_fir()
1379 FLD_VAL(hinc, hinc_start, hinc_end); dispc_ovl_set_fir()
1383 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); dispc_ovl_set_fir()
1396 val = FLD_VAL(vaccu, vert_start, vert_end) | dispc_ovl_set_vid_accu0()
1397 FLD_VAL(haccu, hor_start, hor_end); dispc_ovl_set_vid_accu0()
1410 val = FLD_VAL(vaccu, vert_start, vert_end) | dispc_ovl_set_vid_accu1()
1411 FLD_VAL(haccu, hor_start, hor_end); dispc_ovl_set_vid_accu1()
1421 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); dispc_ovl_set_vid_accu2_0()
1430 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); dispc_ovl_set_vid_accu2_1()
3009 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | _dispc_mgr_set_lcd_timings()
3010 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | _dispc_mgr_set_lcd_timings()
3011 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); _dispc_mgr_set_lcd_timings()
3012 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | _dispc_mgr_set_lcd_timings()
3013 FLD_VAL(vfp, dispc.feat->fp_start, 8) | _dispc_mgr_set_lcd_timings()
3014 FLD_VAL(vbp, dispc.feat->bp_start, 20); _dispc_mgr_set_lcd_timings()
3077 l = FLD_VAL(onoff, 17, 17) | _dispc_mgr_set_lcd_timings()
3078 FLD_VAL(rf, 16, 16) | _dispc_mgr_set_lcd_timings()
3079 FLD_VAL(de, 15, 15) | _dispc_mgr_set_lcd_timings()
3080 FLD_VAL(ipc, 14, 14) | _dispc_mgr_set_lcd_timings()
3081 FLD_VAL(hs, 13, 13) | _dispc_mgr_set_lcd_timings()
3082 FLD_VAL(vs, 12, 12); _dispc_mgr_set_lcd_timings()
3156 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); dispc_mgr_set_lcd_divisor()
H A Drfbi.c732 l |= FLD_VAL(parallelmode, 1, 0); rfbi_configure_bus()
733 l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */ rfbi_configure_bus()
734 l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */ rfbi_configure_bus()
735 l |= FLD_VAL(datatype, 6, 5); rfbi_configure_bus()
736 /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ rfbi_configure_bus()
737 l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */ rfbi_configure_bus()
738 l |= FLD_VAL(cycleformat, 10, 9); rfbi_configure_bus()
739 l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */ rfbi_configure_bus()
740 l |= FLD_VAL(0, 16, 16); /* A0POLARITY */ rfbi_configure_bus()
741 l |= FLD_VAL(0, 17, 17); /* REPOLARITY */ rfbi_configure_bus()
742 l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */ rfbi_configure_bus()
743 l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */ rfbi_configure_bus()
744 l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */ rfbi_configure_bus()
745 l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */ rfbi_configure_bus()
H A Ddss.h71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
74 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
H A Ddsi.c2231 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); dsi_config_tx_fifo()
2264 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); dsi_config_rx_fifo()
2682 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | dsi_vc_write_long_header()
2683 FLD_VAL(ecc, 31, 24); dsi_vc_write_long_header()
3701 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | dsi_proto_timings()
3702 FLD_VAL(exit_hs_mode_lat, 15, 0); dsi_proto_timings()
3956 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ dsi_update_screen_dispc()
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Dtc35876x-dsi-lvds.c38 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
210 (FLD_VAL(lvmx03, 29, 24) | FLD_VAL(lvmx02, 20, 16) | \
211 FLD_VAL(lvmx01, 12, 8) | FLD_VAL(lvmx00, 4, 0))
362 tc35876x_regw(i2c, PPI_TX_RX_TA, FLD_VAL(txtagocnt, 26, 16) | tc35876x_configure_lvds_bridge()
363 FLD_VAL(txtasurecnt, 10, 0)); tc35876x_configure_lvds_bridge()
364 tc35876x_regw(i2c, PPI_LPTXTIMECNT, FLD_VAL(ppi_lptxtimecnt, 10, 0)); tc35876x_configure_lvds_bridge()
366 tc35876x_regw(i2c, PPI_D0S_CLRSIPOCOUNT, FLD_VAL(1, 5, 0)); tc35876x_configure_lvds_bridge()
367 tc35876x_regw(i2c, PPI_D1S_CLRSIPOCOUNT, FLD_VAL(1, 5, 0)); tc35876x_configure_lvds_bridge()
368 tc35876x_regw(i2c, PPI_D2S_CLRSIPOCOUNT, FLD_VAL(1, 5, 0)); tc35876x_configure_lvds_bridge()
369 tc35876x_regw(i2c, PPI_D3S_CLRSIPOCOUNT, FLD_VAL(1, 5, 0)); tc35876x_configure_lvds_bridge()
380 tc35876x_regw(i2c, LVPHY0, FLD_VAL(1, 20, 16) | tc35876x_configure_lvds_bridge()
381 FLD_VAL(2, 15, 14) | FLD_VAL(6, 4, 0)); /* 0x00048006 */ tc35876x_configure_lvds_bridge()
387 tc35876x_regw(i2c, HTIM1, FLD_VAL(40, 24, 16) | FLD_VAL(40, 8, 0)); tc35876x_configure_lvds_bridge()
390 tc35876x_regw(i2c, HTIM2, FLD_VAL(80, 24, 16) | FLD_VAL(1280, 10, 0)); tc35876x_configure_lvds_bridge()
393 tc35876x_regw(i2c, VTIM1, FLD_VAL(14, 23, 16) | FLD_VAL(10, 7, 0)); tc35876x_configure_lvds_bridge()
396 tc35876x_regw(i2c, VTIM2, FLD_VAL(14, 23, 16) | FLD_VAL(800, 10, 0)); tc35876x_configure_lvds_bridge()
H A Dmdfld_dsi_pkg_sender.c233 val = FLD_VAL(param, 23, 16) | FLD_VAL(cmd, 15, 8) | send_short_pkg()
234 FLD_VAL(virtual_channel, 7, 6) | FLD_VAL(data_type, 5, 0); send_short_pkg()
297 val = FLD_VAL(len, 23, 8) | FLD_VAL(virtual_channel, 7, 6) | send_long_pkg()
298 FLD_VAL(data_type, 5, 0); send_long_pkg()
H A Dmdfld_dsi_output.h45 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
48 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
/linux-4.1.27/drivers/crypto/
H A Domap-aes.c48 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
274 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); omap_aes_write_ctrl()

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