/linux-4.1.27/drivers/clk/ti/ |
H A D | clk-7xx.c | 25 DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), 26 DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), 27 DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), 28 DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"), 29 DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), 30 DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), 31 DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), 32 DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"), 33 DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"), 34 DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"), 35 DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"), 36 DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"), 37 DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"), 38 DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"), 39 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), 40 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), 41 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), 42 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), 43 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), 44 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 45 DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"), 46 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 47 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), 48 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), 49 DT_CLK(NULL, "sys_clkin1", "sys_clkin1"), 50 DT_CLK(NULL, "sys_clkin2", "sys_clkin2"), 51 DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"), 52 DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"), 53 DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"), 54 DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"), 55 DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"), 56 DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"), 57 DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), 58 DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), 59 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), 60 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), 61 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), 62 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), 63 DT_CLK(NULL, "abe_clk", "abe_clk"), 64 DT_CLK(NULL, "aess_fclk", "aess_fclk"), 65 DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"), 66 DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), 67 DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"), 68 DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"), 69 DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"), 70 DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"), 71 DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"), 72 DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"), 73 DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"), 74 DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"), 75 DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"), 76 DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"), 77 DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), 78 DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"), 79 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), 80 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 81 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 82 DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), 83 DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), 84 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 85 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 86 DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"), 87 DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"), 88 DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"), 89 DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"), 90 DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"), 91 DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), 92 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), 93 DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"), 94 DT_CLK(NULL, "iva_dclk", "iva_dclk"), 95 DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"), 96 DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"), 97 DT_CLK(NULL, "gpu_dclk", "gpu_dclk"), 98 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), 99 DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"), 100 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), 101 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), 102 DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"), 103 DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"), 104 DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"), 105 DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"), 106 DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"), 107 DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"), 108 DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"), 109 DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), 110 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 111 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 112 DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"), 113 DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), 114 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), 115 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), 116 DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"), 117 DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"), 118 DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"), 119 DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"), 120 DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"), 121 DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"), 122 DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"), 123 DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"), 124 DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"), 125 DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"), 126 DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"), 127 DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"), 128 DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"), 129 DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"), 130 DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"), 131 DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), 132 DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), 133 DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), 134 DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), 135 DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), 136 DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), 137 DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), 138 DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"), 139 DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"), 140 DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"), 141 DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"), 142 DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"), 143 DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"), 144 DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"), 145 DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"), 146 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), 147 DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), 148 DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), 149 DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"), 150 DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), 151 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), 152 DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), 153 DT_CLK(NULL, "eve_clk", "eve_clk"), 154 DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), 155 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), 156 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), 157 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), 158 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), 159 DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"), 160 DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"), 161 DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"), 162 DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"), 163 DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), 164 DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), 165 DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), 166 DT_CLK(NULL, "mlb_clk", "mlb_clk"), 167 DT_CLK(NULL, "mlbp_clk", "mlbp_clk"), 168 DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"), 169 DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"), 170 DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"), 171 DT_CLK(NULL, "video1_div_clk", "video1_div_clk"), 172 DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"), 173 DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"), 174 DT_CLK(NULL, "video2_div_clk", "video2_div_clk"), 175 DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"), 176 DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), 177 DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), 178 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), 179 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), 180 DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), 181 DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), 182 DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), 183 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 184 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 185 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 186 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 187 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 188 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), 189 DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), 190 DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), 191 DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"), 192 DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"), 193 DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"), 194 DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"), 195 DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), 196 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"), 197 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"), 198 DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"), 199 DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"), 200 DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"), 201 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"), 202 DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"), 203 DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"), 204 DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"), 205 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"), 206 DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), 207 DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), 208 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"), 209 DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), 210 DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"), 211 DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"), 212 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"), 213 DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"), 214 DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"), 215 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"), 216 DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"), 217 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"), 218 DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"), 219 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"), 220 DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"), 221 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"), 222 DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"), 223 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"), 224 DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"), 225 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"), 226 DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"), 227 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"), 228 DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), 229 DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"), 230 DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), 231 DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"), 232 DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"), 233 DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"), 234 DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"), 235 DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"), 236 DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"), 237 DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"), 238 DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), 239 DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), 240 DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"), 241 DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"), 242 DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"), 243 DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"), 244 DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), 245 DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), 246 DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), 247 DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), 248 DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), 249 DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), 250 DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), 251 DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), 252 DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), 253 DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"), 254 DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"), 255 DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"), 256 DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"), 257 DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"), 258 DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"), 259 DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"), 260 DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"), 261 DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"), 262 DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"), 263 DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"), 264 DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"), 265 DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"), 266 DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 267 DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 268 DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 269 DT_CLK("omap_i2c.4", "ick", "dummy_ck"), 270 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), 271 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), 272 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), 273 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), 274 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), 275 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), 276 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), 277 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), 278 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), 279 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), 280 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), 281 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), 282 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), 283 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), 284 DT_CLK(NULL, "uart1_ick", "dummy_ck"), 285 DT_CLK(NULL, "uart2_ick", "dummy_ck"), 286 DT_CLK(NULL, "uart3_ick", "dummy_ck"), 287 DT_CLK(NULL, "uart4_ick", "dummy_ck"), 288 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), 289 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 290 DT_CLK("omap_wdt", "ick", "dummy_ck"), 291 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 292 DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"), 293 DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"), 294 DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"), 295 DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"), 296 DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"), 297 DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"), 298 DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"), 299 DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), 300 DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), 301 DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"), 302 DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"), 303 DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"), 304 DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"), 305 DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"), 306 DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"), 307 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
|
H A D | clk-3xxx.c | 24 DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), 25 DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), 26 DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), 27 DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), 28 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 29 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 30 DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"), 31 DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"), 32 DT_CLK("twl", "fck", "osc_sys_ck"), 33 DT_CLK(NULL, "sys_ck", "sys_ck"), 34 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), 35 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), 36 DT_CLK(NULL, "sys_altclk", "sys_altclk"), 37 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), 38 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"), 39 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"), 40 DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"), 41 DT_CLK(NULL, "dpll3_ck", "dpll3_ck"), 42 DT_CLK(NULL, "core_ck", "core_ck"), 43 DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"), 44 DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"), 45 DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"), 46 DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"), 47 DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"), 48 DT_CLK(NULL, "dpll4_ck", "dpll4_ck"), 49 DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"), 50 DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"), 51 DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"), 52 DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"), 53 DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"), 54 DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"), 55 DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"), 56 DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"), 57 DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"), 58 DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"), 59 DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"), 60 DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"), 61 DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"), 62 DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"), 63 DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"), 64 DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"), 65 DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"), 66 DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"), 67 DT_CLK(NULL, "sys_clkout2", "sys_clkout2"), 68 DT_CLK(NULL, "corex2_fck", "corex2_fck"), 69 DT_CLK(NULL, "dpll1_fck", "dpll1_fck"), 70 DT_CLK(NULL, "mpu_ck", "mpu_ck"), 71 DT_CLK(NULL, "arm_fck", "arm_fck"), 72 DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"), 73 DT_CLK(NULL, "l3_ick", "l3_ick"), 74 DT_CLK(NULL, "l4_ick", "l4_ick"), 75 DT_CLK(NULL, "rm_ick", "rm_ick"), 76 DT_CLK(NULL, "gpt10_fck", "gpt10_fck"), 77 DT_CLK(NULL, "gpt11_fck", "gpt11_fck"), 78 DT_CLK(NULL, "core_96m_fck", "core_96m_fck"), 79 DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"), 80 DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"), 81 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"), 82 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), 83 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), 84 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"), 85 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"), 86 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), 87 DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"), 88 DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"), 89 DT_CLK(NULL, "uart2_fck", "uart2_fck"), 90 DT_CLK(NULL, "uart1_fck", "uart1_fck"), 91 DT_CLK(NULL, "core_12m_fck", "core_12m_fck"), 92 DT_CLK("omap_hdq.0", "fck", "hdq_fck"), 93 DT_CLK(NULL, "hdq_fck", "hdq_fck"), 94 DT_CLK(NULL, "core_l3_ick", "core_l3_ick"), 95 DT_CLK(NULL, "sdrc_ick", "sdrc_ick"), 96 DT_CLK(NULL, "gpmc_fck", "gpmc_fck"), 97 DT_CLK(NULL, "core_l4_ick", "core_l4_ick"), 98 DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"), 99 DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"), 100 DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"), 101 DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"), 102 DT_CLK("omap_hdq.0", "ick", "hdq_ick"), 103 DT_CLK(NULL, "hdq_ick", "hdq_ick"), 104 DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"), 105 DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"), 106 DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"), 107 DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"), 108 DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"), 109 DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"), 110 DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"), 111 DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"), 112 DT_CLK("omap_i2c.3", "ick", "i2c3_ick"), 113 DT_CLK("omap_i2c.2", "ick", "i2c2_ick"), 114 DT_CLK("omap_i2c.1", "ick", "i2c1_ick"), 115 DT_CLK(NULL, "i2c3_ick", "i2c3_ick"), 116 DT_CLK(NULL, "i2c2_ick", "i2c2_ick"), 117 DT_CLK(NULL, "i2c1_ick", "i2c1_ick"), 118 DT_CLK(NULL, "uart2_ick", "uart2_ick"), 119 DT_CLK(NULL, "uart1_ick", "uart1_ick"), 120 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), 121 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), 122 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), 123 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"), 124 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"), 125 DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"), 126 DT_CLK(NULL, "init_60m_fclk", "dummy_ck"), 127 DT_CLK(NULL, "gpt1_fck", "gpt1_fck"), 128 DT_CLK(NULL, "aes2_ick", "aes2_ick"), 129 DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"), 130 DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"), 131 DT_CLK(NULL, "sha12_ick", "sha12_ick"), 132 DT_CLK(NULL, "wdt2_fck", "wdt2_fck"), 133 DT_CLK("omap_wdt", "ick", "wdt2_ick"), 134 DT_CLK(NULL, "wdt2_ick", "wdt2_ick"), 135 DT_CLK(NULL, "wdt1_ick", "wdt1_ick"), 136 DT_CLK(NULL, "gpio1_ick", "gpio1_ick"), 137 DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"), 138 DT_CLK(NULL, "gpt12_ick", "gpt12_ick"), 139 DT_CLK(NULL, "gpt1_ick", "gpt1_ick"), 140 DT_CLK(NULL, "per_96m_fck", "per_96m_fck"), 141 DT_CLK(NULL, "per_48m_fck", "per_48m_fck"), 142 DT_CLK(NULL, "uart3_fck", "uart3_fck"), 143 DT_CLK(NULL, "gpt2_fck", "gpt2_fck"), 144 DT_CLK(NULL, "gpt3_fck", "gpt3_fck"), 145 DT_CLK(NULL, "gpt4_fck", "gpt4_fck"), 146 DT_CLK(NULL, "gpt5_fck", "gpt5_fck"), 147 DT_CLK(NULL, "gpt6_fck", "gpt6_fck"), 148 DT_CLK(NULL, "gpt7_fck", "gpt7_fck"), 149 DT_CLK(NULL, "gpt8_fck", "gpt8_fck"), 150 DT_CLK(NULL, "gpt9_fck", "gpt9_fck"), 151 DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"), 152 DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"), 153 DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"), 154 DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"), 155 DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"), 156 DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"), 157 DT_CLK(NULL, "wdt3_fck", "wdt3_fck"), 158 DT_CLK(NULL, "per_l4_ick", "per_l4_ick"), 159 DT_CLK(NULL, "gpio6_ick", "gpio6_ick"), 160 DT_CLK(NULL, "gpio5_ick", "gpio5_ick"), 161 DT_CLK(NULL, "gpio4_ick", "gpio4_ick"), 162 DT_CLK(NULL, "gpio3_ick", "gpio3_ick"), 163 DT_CLK(NULL, "gpio2_ick", "gpio2_ick"), 164 DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), 165 DT_CLK(NULL, "uart3_ick", "uart3_ick"), 166 DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), 167 DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), 168 DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), 169 DT_CLK(NULL, "gpt6_ick", "gpt6_ick"), 170 DT_CLK(NULL, "gpt5_ick", "gpt5_ick"), 171 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), 172 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), 173 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), 174 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), 175 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"), 176 DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"), 177 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), 178 DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"), 179 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"), 180 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"), 181 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), 182 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), 183 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), 184 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"), 185 DT_CLK("etb", "emu_src_ck", "emu_src_ck"), 186 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"), 187 DT_CLK(NULL, "pclk_fck", "pclk_fck"), 188 DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"), 189 DT_CLK(NULL, "atclk_fck", "atclk_fck"), 190 DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"), 191 DT_CLK(NULL, "traceclk_fck", "traceclk_fck"), 192 DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"), 193 DT_CLK(NULL, "gpt12_fck", "gpt12_fck"), 194 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), 195 DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), 196 DT_CLK(NULL, "timer_sys_ck", "sys_ck"), 197 DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"), 202 DT_CLK(NULL, "aes1_ick", "aes1_ick"), 203 DT_CLK("omap_rng", "ick", "rng_ick"), 204 DT_CLK("omap3-rom-rng", "ick", "rng_ick"), 205 DT_CLK(NULL, "sha11_ick", "sha11_ick"), 206 DT_CLK(NULL, "des1_ick", "des1_ick"), 207 DT_CLK(NULL, "cam_mclk", "cam_mclk"), 208 DT_CLK(NULL, "cam_ick", "cam_ick"), 209 DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"), 210 DT_CLK(NULL, "security_l3_ick", "security_l3_ick"), 211 DT_CLK(NULL, "pka_ick", "pka_ick"), 212 DT_CLK(NULL, "icr_ick", "icr_ick"), 213 DT_CLK("omap-aes", "ick", "aes2_ick"), 214 DT_CLK("omap-sham", "ick", "sha12_ick"), 215 DT_CLK(NULL, "des2_ick", "des2_ick"), 216 DT_CLK(NULL, "mspro_ick", "mspro_ick"), 217 DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"), 218 DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"), 219 DT_CLK(NULL, "sr1_fck", "sr1_fck"), 220 DT_CLK(NULL, "sr2_fck", "sr2_fck"), 221 DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"), 222 DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"), 223 DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"), 224 DT_CLK(NULL, "dpll2_fck", "dpll2_fck"), 225 DT_CLK(NULL, "iva2_ck", "iva2_ck"), 226 DT_CLK(NULL, "modem_fck", "modem_fck"), 227 DT_CLK(NULL, "sad2d_ick", "sad2d_ick"), 228 DT_CLK(NULL, "mad2d_ick", "mad2d_ick"), 229 DT_CLK(NULL, "mspro_fck", "mspro_fck"), 230 DT_CLK(NULL, "dpll2_ck", "dpll2_ck"), 231 DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"), 236 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), 237 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), 238 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"), 239 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), 240 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), 241 DT_CLK(NULL, "usim_fck", "usim_fck"), 242 DT_CLK(NULL, "usim_ick", "usim_ick"), 247 DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"), 248 DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"), 249 DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"), 250 DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"), 251 DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"), 252 DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"), 253 DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"), 254 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), 255 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), 256 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"), 257 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), 258 DT_CLK(NULL, "fac_ick", "fac_ick"), 259 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), 260 DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"), 261 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), 262 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"), 263 DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), 268 DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"), 269 DT_CLK(NULL, "dpll5_ck", "dpll5_ck"), 270 DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"), 271 DT_CLK(NULL, "sgx_fck", "sgx_fck"), 272 DT_CLK(NULL, "sgx_ick", "sgx_ick"), 273 DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"), 274 DT_CLK(NULL, "ts_fck", "ts_fck"), 275 DT_CLK(NULL, "usbtll_fck", "usbtll_fck"), 276 DT_CLK(NULL, "usbtll_ick", "usbtll_ick"), 277 DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"), 278 DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"), 279 DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"), 280 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), 281 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"), 282 DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), 283 DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"), 284 DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"), 285 DT_CLK(NULL, "usbhost_ick", "usbhost_ick"), 290 DT_CLK(NULL, "ipss_ick", "ipss_ick"), 291 DT_CLK(NULL, "rmii_ck", "rmii_ck"), 292 DT_CLK(NULL, "pclk_ck", "pclk_ck"), 293 DT_CLK(NULL, "emac_ick", "emac_ick"), 294 DT_CLK(NULL, "emac_fck", "emac_fck"), 295 DT_CLK("davinci_emac.0", NULL, "emac_ick"), 296 DT_CLK("davinci_mdio.0", NULL, "emac_fck"), 297 DT_CLK("vpfe-capture", "master", "vpfe_ick"), 298 DT_CLK("vpfe-capture", "slave", "vpfe_fck"), 299 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), 300 DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), 301 DT_CLK(NULL, "hecc_ck", "hecc_ck"), 302 DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), 303 DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), 308 DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"), 309 DT_CLK(NULL, "uart4_fck", "uart4_fck"), 310 DT_CLK(NULL, "uart4_ick", "uart4_ick"),
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H A D | clk-54xx.c | 29 DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), 30 DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), 31 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), 32 DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), 33 DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), 34 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), 35 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), 36 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), 37 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), 38 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 39 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 40 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), 41 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), 42 DT_CLK(NULL, "sys_clkin", "sys_clkin"), 43 DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), 44 DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), 45 DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), 46 DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), 47 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), 48 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), 49 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), 50 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), 51 DT_CLK(NULL, "abe_clk", "abe_clk"), 52 DT_CLK(NULL, "abe_iclk", "abe_iclk"), 53 DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), 54 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), 55 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 56 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 57 DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"), 58 DT_CLK(NULL, "c2c_fclk", "c2c_fclk"), 59 DT_CLK(NULL, "c2c_iclk", "c2c_iclk"), 60 DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), 61 DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"), 62 DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), 63 DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), 64 DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), 65 DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), 66 DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), 67 DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), 68 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), 69 DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), 70 DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), 71 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), 72 DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), 73 DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"), 74 DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"), 75 DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), 76 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 77 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 78 DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), 79 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 80 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), 81 DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), 82 DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), 83 DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), 84 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 85 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), 86 DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), 87 DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"), 88 DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"), 89 DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"), 90 DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"), 91 DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"), 92 DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"), 93 DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), 94 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), 95 DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), 96 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), 97 DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"), 98 DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), 99 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), 100 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), 101 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), 102 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), 103 DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), 104 DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"), 105 DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), 106 DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), 107 DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), 108 DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), 109 DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), 110 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), 111 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), 112 DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), 113 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 114 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 115 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 116 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 117 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 118 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), 119 DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), 120 DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), 121 DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), 122 DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"), 123 DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"), 124 DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"), 125 DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), 126 DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), 127 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), 128 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), 129 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"), 130 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), 131 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), 132 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"), 133 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), 134 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), 135 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), 136 DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"), 137 DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), 138 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), 139 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), 140 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), 141 DT_CLK(NULL, "aess_fclk", "aess_fclk"), 142 DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), 143 DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"), 144 DT_CLK(NULL, "fdif_fclk", "fdif_fclk"), 145 DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), 146 DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), 147 DT_CLK(NULL, "hsi_fclk", "hsi_fclk"), 148 DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), 149 DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"), 150 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), 151 DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"), 152 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), 153 DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"), 154 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), 155 DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"), 156 DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), 157 DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"), 158 DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), 159 DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"), 160 DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), 161 DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), 162 DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), 163 DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), 164 DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), 165 DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), 166 DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), 167 DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), 168 DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), 169 DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), 170 DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), 171 DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), 172 DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), 173 DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), 174 DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), 175 DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), 176 DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), 177 DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), 178 DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), 179 DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), 180 DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), 181 DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), 182 DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), 183 DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), 184 DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), 185 DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 186 DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 187 DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 188 DT_CLK("omap_i2c.4", "ick", "dummy_ck"), 189 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), 190 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), 191 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), 192 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), 193 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), 194 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), 195 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), 196 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), 197 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), 198 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), 199 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), 200 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), 201 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), 202 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), 203 DT_CLK(NULL, "uart1_ick", "dummy_ck"), 204 DT_CLK(NULL, "uart2_ick", "dummy_ck"), 205 DT_CLK(NULL, "uart3_ick", "dummy_ck"), 206 DT_CLK(NULL, "uart4_ick", "dummy_ck"), 207 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), 208 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 209 DT_CLK("omap_wdt", "ick", "dummy_ck"), 210 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 211 DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"), 212 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"), 213 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"), 214 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"), 215 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"), 216 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"), 217 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"), 218 DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 219 DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 220 DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 221 DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
|
H A D | clk-44xx.c | 35 DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"), 36 DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), 37 DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), 38 DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"), 39 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), 40 DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), 41 DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), 42 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), 43 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), 44 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), 45 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), 46 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 47 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 48 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), 49 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), 50 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), 51 DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"), 52 DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"), 53 DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), 54 DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), 55 DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"), 56 DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"), 57 DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"), 58 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), 59 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), 60 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), 61 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), 62 DT_CLK(NULL, "abe_clk", "abe_clk"), 63 DT_CLK(NULL, "aess_fclk", "aess_fclk"), 64 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), 65 DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"), 66 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 67 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 68 DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"), 69 DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"), 70 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), 71 DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"), 72 DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"), 73 DT_CLK(NULL, "div_core_ck", "div_core_ck"), 74 DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"), 75 DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"), 76 DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"), 77 DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"), 78 DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), 79 DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), 80 DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"), 81 DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"), 82 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), 83 DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), 84 DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"), 85 DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"), 86 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 87 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 88 DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"), 89 DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"), 90 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 91 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 92 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), 93 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), 94 DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), 95 DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"), 96 DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"), 97 DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"), 98 DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"), 99 DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"), 100 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), 101 DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"), 102 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), 103 DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"), 104 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), 105 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), 106 DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"), 107 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), 108 DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"), 109 DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"), 110 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), 111 DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"), 112 DT_CLK(NULL, "l3_div_ck", "l3_div_ck"), 113 DT_CLK(NULL, "l4_div_ck", "l4_div_ck"), 114 DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"), 115 DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"), 116 DT_CLK("smp_twd", NULL, "mpu_periphclk"), 117 DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"), 118 DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"), 119 DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"), 120 DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"), 121 DT_CLK(NULL, "aes1_fck", "aes1_fck"), 122 DT_CLK(NULL, "aes2_fck", "aes2_fck"), 123 DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), 124 DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"), 125 DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), 126 DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"), 127 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), 128 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), 129 DT_CLK(NULL, "dss_fck", "dss_fck"), 130 DT_CLK("omapdss_dss", "ick", "dss_fck"), 131 DT_CLK(NULL, "fdif_fck", "fdif_fck"), 132 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 133 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 134 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 135 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 136 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 137 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), 138 DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"), 139 DT_CLK(NULL, "hsi_fck", "hsi_fck"), 140 DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), 141 DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), 142 DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"), 143 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), 144 DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"), 145 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), 146 DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"), 147 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), 148 DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"), 149 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"), 150 DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"), 151 DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"), 152 DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"), 153 DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"), 154 DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"), 155 DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"), 156 DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"), 157 DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"), 158 DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), 159 DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"), 160 DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"), 161 DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"), 162 DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"), 163 DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"), 164 DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"), 165 DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"), 166 DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"), 167 DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"), 168 DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"), 169 DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"), 170 DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"), 171 DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"), 172 DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"), 173 DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"), 174 DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"), 175 DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"), 176 DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"), 177 DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"), 178 DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), 179 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), 180 DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), 181 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), 182 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), 183 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), 184 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), 185 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), 186 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), 187 DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"), 188 DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"), 189 DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"), 190 DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"), 191 DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"), 192 DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"), 193 DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"), 194 DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), 195 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), 196 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), 197 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), 198 DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"), 199 DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"), 200 DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"), 201 DT_CLK(NULL, "usim_ck", "usim_ck"), 202 DT_CLK(NULL, "usim_fclk", "usim_fclk"), 203 DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"), 204 DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"), 205 DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), 206 DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), 207 DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), 208 DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), 209 DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), 210 DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), 211 DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), 212 DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), 213 DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), 214 DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), 215 DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), 216 DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), 217 DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), 218 DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), 219 DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"), 220 DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"), 221 DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"), 222 DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"), 223 DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"), 224 DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"), 225 DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 226 DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 227 DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 228 DT_CLK("omap_i2c.4", "ick", "dummy_ck"), 229 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), 230 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), 231 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), 232 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), 233 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), 234 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), 235 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), 236 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), 237 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), 238 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), 239 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), 240 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), 241 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), 242 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), 243 DT_CLK(NULL, "uart1_ick", "dummy_ck"), 244 DT_CLK(NULL, "uart2_ick", "dummy_ck"), 245 DT_CLK(NULL, "uart3_ick", "dummy_ck"), 246 DT_CLK(NULL, "uart4_ick", "dummy_ck"), 247 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), 248 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 249 DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"), 250 DT_CLK("omap_wdt", "ick", "dummy_ck"), 251 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 252 DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"), 253 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"), 254 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"), 255 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"), 256 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"), 257 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"), 258 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"), 259 DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"), 260 DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"), 261 DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"), 262 DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"), 263 DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"), 264 DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"), 265 DT_CLK(NULL, "div_ts_ck", "div_ts_ck"), 266 DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
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H A D | clk-2xxx.c | 23 DT_CLK(NULL, "func_32k_ck", "func_32k_ck"), 24 DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"), 25 DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), 26 DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), 27 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 28 DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"), 29 DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"), 30 DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"), 31 DT_CLK(NULL, "osc_ck", "osc_ck"), 32 DT_CLK(NULL, "sys_ck", "sys_ck"), 33 DT_CLK(NULL, "alt_ck", "alt_ck"), 34 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), 35 DT_CLK(NULL, "dpll_ck", "dpll_ck"), 36 DT_CLK(NULL, "apll96_ck", "apll96_ck"), 37 DT_CLK(NULL, "apll54_ck", "apll54_ck"), 38 DT_CLK(NULL, "func_54m_ck", "func_54m_ck"), 39 DT_CLK(NULL, "core_ck", "core_ck"), 40 DT_CLK(NULL, "func_96m_ck", "func_96m_ck"), 41 DT_CLK(NULL, "func_48m_ck", "func_48m_ck"), 42 DT_CLK(NULL, "func_12m_ck", "func_12m_ck"), 43 DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"), 44 DT_CLK(NULL, "sys_clkout", "sys_clkout"), 45 DT_CLK(NULL, "emul_ck", "emul_ck"), 46 DT_CLK(NULL, "mpu_ck", "mpu_ck"), 47 DT_CLK(NULL, "dsp_fck", "dsp_fck"), 48 DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"), 49 DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"), 50 DT_CLK(NULL, "gfx_ick", "gfx_ick"), 51 DT_CLK("omapdss_dss", "ick", "dss_ick"), 52 DT_CLK(NULL, "dss_ick", "dss_ick"), 53 DT_CLK(NULL, "dss1_fck", "dss1_fck"), 54 DT_CLK(NULL, "dss2_fck", "dss2_fck"), 55 DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"), 56 DT_CLK(NULL, "core_l3_ck", "core_l3_ck"), 57 DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"), 58 DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"), 59 DT_CLK(NULL, "l4_ck", "l4_ck"), 60 DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"), 61 DT_CLK(NULL, "gpt1_ick", "gpt1_ick"), 62 DT_CLK(NULL, "gpt1_fck", "gpt1_fck"), 63 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), 64 DT_CLK(NULL, "gpt2_fck", "gpt2_fck"), 65 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), 66 DT_CLK(NULL, "gpt3_fck", "gpt3_fck"), 67 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), 68 DT_CLK(NULL, "gpt4_fck", "gpt4_fck"), 69 DT_CLK(NULL, "gpt5_ick", "gpt5_ick"), 70 DT_CLK(NULL, "gpt5_fck", "gpt5_fck"), 71 DT_CLK(NULL, "gpt6_ick", "gpt6_ick"), 72 DT_CLK(NULL, "gpt6_fck", "gpt6_fck"), 73 DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), 74 DT_CLK(NULL, "gpt7_fck", "gpt7_fck"), 75 DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), 76 DT_CLK(NULL, "gpt8_fck", "gpt8_fck"), 77 DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), 78 DT_CLK(NULL, "gpt9_fck", "gpt9_fck"), 79 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), 80 DT_CLK(NULL, "gpt10_fck", "gpt10_fck"), 81 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), 82 DT_CLK(NULL, "gpt11_fck", "gpt11_fck"), 83 DT_CLK(NULL, "gpt12_ick", "gpt12_ick"), 84 DT_CLK(NULL, "gpt12_fck", "gpt12_fck"), 85 DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"), 86 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"), 87 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"), 88 DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"), 89 DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"), 90 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), 91 DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"), 92 DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"), 93 DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"), 94 DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"), 95 DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"), 96 DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"), 97 DT_CLK(NULL, "uart1_ick", "uart1_ick"), 98 DT_CLK(NULL, "uart1_fck", "uart1_fck"), 99 DT_CLK(NULL, "uart2_ick", "uart2_ick"), 100 DT_CLK(NULL, "uart2_fck", "uart2_fck"), 101 DT_CLK(NULL, "uart3_ick", "uart3_ick"), 102 DT_CLK(NULL, "uart3_fck", "uart3_fck"), 103 DT_CLK(NULL, "gpios_ick", "gpios_ick"), 104 DT_CLK(NULL, "gpios_fck", "gpios_fck"), 105 DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"), 106 DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"), 107 DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"), 108 DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"), 109 DT_CLK(NULL, "wdt1_ick", "wdt1_ick"), 110 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), 111 DT_CLK("omap24xxcam", "fck", "cam_fck"), 112 DT_CLK(NULL, "cam_fck", "cam_fck"), 113 DT_CLK("omap24xxcam", "ick", "cam_ick"), 114 DT_CLK(NULL, "cam_ick", "cam_ick"), 115 DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"), 116 DT_CLK(NULL, "wdt4_ick", "wdt4_ick"), 117 DT_CLK(NULL, "wdt4_fck", "wdt4_fck"), 118 DT_CLK(NULL, "mspro_ick", "mspro_ick"), 119 DT_CLK(NULL, "mspro_fck", "mspro_fck"), 120 DT_CLK(NULL, "fac_ick", "fac_ick"), 121 DT_CLK(NULL, "fac_fck", "fac_fck"), 122 DT_CLK("omap_hdq.0", "ick", "hdq_ick"), 123 DT_CLK(NULL, "hdq_ick", "hdq_ick"), 124 DT_CLK("omap_hdq.0", "fck", "hdq_fck"), 125 DT_CLK(NULL, "hdq_fck", "hdq_fck"), 126 DT_CLK("omap_i2c.1", "ick", "i2c1_ick"), 127 DT_CLK(NULL, "i2c1_ick", "i2c1_ick"), 128 DT_CLK("omap_i2c.2", "ick", "i2c2_ick"), 129 DT_CLK(NULL, "i2c2_ick", "i2c2_ick"), 130 DT_CLK(NULL, "gpmc_fck", "gpmc_fck"), 131 DT_CLK(NULL, "sdma_fck", "sdma_fck"), 132 DT_CLK(NULL, "sdma_ick", "sdma_ick"), 133 DT_CLK(NULL, "sdrc_ick", "sdrc_ick"), 134 DT_CLK(NULL, "des_ick", "des_ick"), 135 DT_CLK("omap-sham", "ick", "sha_ick"), 136 DT_CLK(NULL, "sha_ick", "sha_ick"), 137 DT_CLK("omap_rng", "ick", "rng_ick"), 138 DT_CLK(NULL, "rng_ick", "rng_ick"), 139 DT_CLK("omap-aes", "ick", "aes_ick"), 140 DT_CLK(NULL, "aes_ick", "aes_ick"), 141 DT_CLK(NULL, "pka_ick", "pka_ick"), 142 DT_CLK(NULL, "usb_fck", "usb_fck"), 143 DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"), 144 DT_CLK(NULL, "timer_sys_ck", "sys_ck"), 145 DT_CLK(NULL, "timer_ext_ck", "alt_ck"), 150 DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"), 151 DT_CLK(NULL, "sys_clkout2", "sys_clkout2"), 152 DT_CLK(NULL, "dsp_ick", "dsp_ick"), 153 DT_CLK(NULL, "iva1_ifck", "iva1_ifck"), 154 DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"), 155 DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), 156 DT_CLK(NULL, "wdt3_fck", "wdt3_fck"), 157 DT_CLK("mmci-omap.0", "ick", "mmc_ick"), 158 DT_CLK(NULL, "mmc_ick", "mmc_ick"), 159 DT_CLK("mmci-omap.0", "fck", "mmc_fck"), 160 DT_CLK(NULL, "mmc_fck", "mmc_fck"), 161 DT_CLK(NULL, "eac_ick", "eac_ick"), 162 DT_CLK(NULL, "eac_fck", "eac_fck"), 163 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), 164 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), 165 DT_CLK(NULL, "vlynq_ick", "vlynq_ick"), 166 DT_CLK(NULL, "vlynq_fck", "vlynq_fck"), 167 DT_CLK("musb-hdrc", "fck", "osc_ck"), 172 DT_CLK("twl", "fck", "osc_ck"), 173 DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"), 174 DT_CLK(NULL, "mdm_ick", "mdm_ick"), 175 DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"), 176 DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"), 177 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), 178 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), 179 DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"), 180 DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"), 181 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), 182 DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"), 183 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"), 184 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"), 185 DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"), 186 DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"), 187 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), 188 DT_CLK(NULL, "icr_ick", "icr_ick"), 189 DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"), 190 DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"), 191 DT_CLK("musb-omap2430", "ick", "usbhs_ick"), 192 DT_CLK(NULL, "usbhs_ick", "usbhs_ick"), 193 DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"), 194 DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"), 195 DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"), 196 DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"), 197 DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"), 198 DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"), 199 DT_CLK(NULL, "gpio5_ick", "gpio5_ick"), 200 DT_CLK(NULL, "gpio5_fck", "gpio5_fck"), 201 DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"), 202 DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"), 203 DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"), 204 DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"), 205 DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"),
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H A D | clk-43xx.c | 23 DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), 24 DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), 25 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 26 DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), 27 DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), 28 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 29 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), 30 DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), 31 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 32 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 33 DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), 34 DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), 35 DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), 36 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 37 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 38 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), 39 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), 40 DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), 41 DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), 42 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 43 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 44 DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), 45 DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), 46 DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), 47 DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), 48 DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), 49 DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), 50 DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), 51 DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), 52 DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), 53 DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), 54 DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), 55 DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), 56 DT_CLK(NULL, "sha0_fck", "sha0_fck"), 57 DT_CLK(NULL, "aes0_fck", "aes0_fck"), 58 DT_CLK(NULL, "timer1_fck", "timer1_fck"), 59 DT_CLK(NULL, "timer2_fck", "timer2_fck"), 60 DT_CLK(NULL, "timer3_fck", "timer3_fck"), 61 DT_CLK(NULL, "timer4_fck", "timer4_fck"), 62 DT_CLK(NULL, "timer5_fck", "timer5_fck"), 63 DT_CLK(NULL, "timer6_fck", "timer6_fck"), 64 DT_CLK(NULL, "timer7_fck", "timer7_fck"), 65 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), 66 DT_CLK(NULL, "l3_gclk", "l3_gclk"), 67 DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), 68 DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), 69 DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), 70 DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), 71 DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), 72 DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), 73 DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), 74 DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), 75 DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), 76 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 77 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 78 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 79 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 80 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 81 DT_CLK(NULL, "mmc_clk", "mmc_clk"), 82 DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), 83 DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), 84 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 85 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 86 DT_CLK(NULL, "sysclk_div", "sysclk_div"), 87 DT_CLK(NULL, "disp_clk", "disp_clk"), 88 DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"), 89 DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"), 90 DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"), 91 DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"), 92 DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"), 93 DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"), 94 DT_CLK(NULL, "timer8_fck", "timer8_fck"), 95 DT_CLK(NULL, "timer9_fck", "timer9_fck"), 96 DT_CLK(NULL, "timer10_fck", "timer10_fck"), 97 DT_CLK(NULL, "timer11_fck", "timer11_fck"), 98 DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"), 99 DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"), 100 DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), 101 DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"), 102 DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"), 103 DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"), 104 DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"), 105 DT_CLK(NULL, "func_12m_clk", "func_12m_clk"), 106 DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"), 107 DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"), 108 DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), 109 DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), 110 DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), 111 DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"), 112 DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"), 113 DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
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H A D | clk-33xx.c | 23 DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), 24 DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), 25 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 26 DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), 27 DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), 28 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 29 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), 30 DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), 31 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 32 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 33 DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), 34 DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), 35 DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), 36 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 37 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 38 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), 39 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), 40 DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"), 41 DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), 42 DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), 43 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 44 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 45 DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), 46 DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), 47 DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), 48 DT_CLK(NULL, "cefuse_fck", "cefuse_fck"), 49 DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), 50 DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), 51 DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), 52 DT_CLK("481cc000.d_can", NULL, "dcan0_fck"), 53 DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), 54 DT_CLK("481d0000.d_can", NULL, "dcan1_fck"), 55 DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), 56 DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), 57 DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), 58 DT_CLK(NULL, "mmu_fck", "mmu_fck"), 59 DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), 60 DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), 61 DT_CLK(NULL, "sha0_fck", "sha0_fck"), 62 DT_CLK(NULL, "aes0_fck", "aes0_fck"), 63 DT_CLK(NULL, "rng_fck", "rng_fck"), 64 DT_CLK(NULL, "timer1_fck", "timer1_fck"), 65 DT_CLK(NULL, "timer2_fck", "timer2_fck"), 66 DT_CLK(NULL, "timer3_fck", "timer3_fck"), 67 DT_CLK(NULL, "timer4_fck", "timer4_fck"), 68 DT_CLK(NULL, "timer5_fck", "timer5_fck"), 69 DT_CLK(NULL, "timer6_fck", "timer6_fck"), 70 DT_CLK(NULL, "timer7_fck", "timer7_fck"), 71 DT_CLK(NULL, "usbotg_fck", "usbotg_fck"), 72 DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"), 73 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), 74 DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"), 75 DT_CLK(NULL, "l3_gclk", "l3_gclk"), 76 DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), 77 DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), 78 DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), 79 DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"), 80 DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), 81 DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), 82 DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"), 83 DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), 84 DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), 85 DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), 86 DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), 87 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 88 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 89 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 90 DT_CLK(NULL, "lcd_gclk", "lcd_gclk"), 91 DT_CLK(NULL, "mmc_clk", "mmc_clk"), 92 DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), 93 DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), 94 DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"), 95 DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"), 96 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 97 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 98 DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), 99 DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), 100 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), 101 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), 102 DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), 103 DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), 104 DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), 105 DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), 106 DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), 107 DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
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H A D | clk-816x.c | 18 DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), 19 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 20 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), 21 DT_CLK(NULL, "mpu_ck", "mpu_ck"), 22 DT_CLK(NULL, "timer1_fck", "timer1_fck"), 23 DT_CLK(NULL, "timer2_fck", "timer2_fck"), 24 DT_CLK(NULL, "timer3_fck", "timer3_fck"), 25 DT_CLK(NULL, "timer4_fck", "timer4_fck"), 26 DT_CLK(NULL, "timer5_fck", "timer5_fck"), 27 DT_CLK(NULL, "timer6_fck", "timer6_fck"), 28 DT_CLK(NULL, "timer7_fck", "timer7_fck"), 29 DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"), 30 DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"), 31 DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"), 32 DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"), 33 DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"), 34 DT_CLK(NULL, "sysclk24_ck", "sysclk24_ck"), 35 DT_CLK("4a100000.ethernet", "sysclk24_ck", "sysclk24_ck"),
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/linux-4.1.27/include/linux/clk/ |
H A D | ti.h | 209 #define DT_CLK(dev, con, name) \ macro
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/linux-4.1.27/drivers/net/ethernet/dec/tulip/ |
H A D | de4x5.h | 445 #define DT_CLK 0x00000002 /* Serial ROM Clock */ macro
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H A D | de4x5.c | 4210 sendto_srom(command | DT_CLK, addr); srom_latch() 4244 sendto_srom(command | DT_CLK, addr); srom_data()
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