Searched refs:DSI (Results 1 – 24 of 24) sorted by relevance
1 MIPI DSI (Display Serial Interface) busses6 define the syntax used to represent a DSI bus in a device tree.8 This document describes DSI bus-specific properties only or defines existing9 standard properties in the context of the DSI bus.11 Each DSI host provides a DSI bus. The DSI host controller's node contains a15 The following assumes that only a single peripheral is connected to a DSI18 DSI host22 a DSI host, the following properties apply to a node representing a DSI host.26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so32 DSI peripheral[all …]
3 This panel requires a dual-channel DSI host to operate. It supports two modes:7 Each of the DSI channels controls a separate DSI peripheral. The peripheral8 driven by the first link (DSI-LINK1), left or even, is considered the primary10 to the peripheral driven by the second link (DSI-LINK2, right or odd).12 Note that in video mode the DSI-LINK1 interface always provides the left/even13 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it20 - reg: DSI virtual channel of the peripheral22 Required properties (for DSI-LINK1 only):23 - link2: phandle to the DSI peripheral on the secondary link. Note that the24 presence of this property marks the containing node as DSI-LINK1.[all …]
5 - reg: the virtual channel number of a DSI peripheral
1 Exynos MIPI DSI Master10 - interrupts: should contain DSI interrupt21 according to DSI host bindings (see MIPI DSI bindings [1])27 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).34 - reg: (required) can be 0 for input RGB/I80 port or 1 for DSI port;36 endpoint node of DSI port (reg = 1):37 - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst39 - samsung,esc-clock-frequency: specifies DSI frequency in escape mode
21 - DSS Submodules: RFBI, DSI, HDMI55 DSI62 - interrupts: the DSI interrupt line64 - vdd-supply: power supply for DSI69 - Video port for DSI output70 - DSI controlled peripherals72 DSI Endpoint required properties:73 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
21 - DSS Submodules: RFBI, VENC, DSI, HDMI74 DSI81 - interrupts: the DSI interrupt line83 - vdd-supply: power supply for DSI88 - Video port for DSI output89 - DSI controlled peripherals91 DSI Endpoint required properties:92 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
68 DSI75 - interrupts: the DSI interrupt line77 - vdd-supply: power supply for DSI81 DSI Endpoint required properties:82 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
1 Generic MIPI DSI Command Mode Panel13 - Video port for DSI input
14 # MIPI DSI driver18 bool "EXYNOS MIPI DSI driver support."21 This enables support for MIPI-DSI device.
12 Plus a handful of blocks around them for HDMI/DSI/etc output.18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple40 encoder -> DTV/LCDC/DSI (within MDP4) /41 connector -> HDMI/DSI/etc --> other device(s)54 connector -> HDMI/DSI/eDP/etc --> other device(s)57 than needing a different implementation for DTV, DSI, etc. (Ie. the60 Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI,
40 bool "Enable DSI support in MSM DRM driver"46 Choose this option if you have a need for MIPI DSI connector
40 <debugfs>/omapdss/dsi_irq for DSI interrupts.96 bool "DSI support"99 MIPI DSI (Display Serial Interface) support.101 DSI is a high speed half-duplex serial interface between the host104 See http://www.mipi.org/ for DSI specifications.
27 tristate "S6E8AA0 DSI video mode panel"40 24 bit RGB per pixel. It provides a dual MIPI DSI interface to
43 tristate "Generic DSI Command Mode Panel"46 Driver for generic DSI command mode panels.
43 bool "EXYNOS DRM MIPI-DSI driver support"49 This enables support for Exynos MIPI-DSI device.
5 (let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,19 - MIPI DSI output in command mode25 - Use CPU to update RFBI or DSI output31 - Use DSI DPLL to create DSS FCK152 - Virtual overlay managers can only be connected to DBI or DSI displays.293 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock356 System DMA update for DSI
624 // supply for U8500 CSI/DSI; VANA LDO1023 <0xa0351000 0x1000>, /* DSI link 1 */1024 <0xa0352000 0x1000>, /* DSI link 2 */1025 <0xa0353000 0x1000>; /* DSI link 3 */1030 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */1031 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
271 regulator-name = "V-CSI/DSI";
398 regulator-name = "V-CSI/DSI";
152 DSI = 0x00100000, enumerator
184 - avdd-dsi-supply: phandle of a supply that powers the DSI controller186 which pads are used by this DSI output and need to be calibrated. See also194 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
48 tristate "S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver"54 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
27 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
266 S: DSI/IDASI