Searched refs:DRD (Results 1 – 9 of 9) sorted by relevance
124 Samsung Exynos5 SoC series USB DRD PHY controller133 - reg : Register offset and length of USB DRD PHY register set;137 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),168 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
54 u32 DRD; /* (u32*) address of self-modified DRD */ member231 var->DRD = bcom_sram_va2pa(self_modified_drd(tsk->tasknum)); in bcom_fec_tx_reset()
12 passed via DT, USB DRD controllers should default to
238 tristate "Exynos5 SoC series USB DRD PHY driver"246 Enable USB DRD PHY support for Exynos 5 SoC series.247 This driver provides PHY interface for USB 3.0 DRD controller
2 tristate "DesignWare USB3 DRD Core Support"
2 tristate "DesignWare USB2 DRD Core Support"
1903 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); in xgbe_config_dma_cache()
1979 * scsi.c: Add CDU-541, Denon DRD-25X to blacklist.
3111 DESIGNWARE USB2 DRD IP DRIVER3118 DESIGNWARE USB3 DRD IP DRIVER