/linux-4.1.27/arch/arm/mach-davinci/ |
H A D | dm365.c | 2 * TI DaVinci DM365 chip specific setup 41 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ 496 MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false) 498 MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false) 499 MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false) 500 MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false) 501 MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false) 502 MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false) 503 MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) 505 MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) 506 MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) 508 MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false) 509 MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false) 510 MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) 511 MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) 512 MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) 513 MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) 514 MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false) 515 MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false) 517 MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) 518 MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) 519 MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false) 520 MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false) 521 MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false) 522 MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false) 524 MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false) 525 MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false) 526 MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false) 527 MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false) 528 MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false) 530 MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false) 531 MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false) 532 MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) 533 MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) 534 MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false) 535 MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false) 537 MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false) 538 MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false) 539 MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false) 540 MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false) 541 MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false) 542 MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false) 543 MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false) 544 MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false) 545 MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false) 546 MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false) 547 MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false) 548 MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false) 549 MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false) 550 MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false) 551 MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false) 552 MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) 553 MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) 555 MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false) 557 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) 558 MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) 559 MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false) 560 MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false) 561 MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false) 562 MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false) 563 MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false) 564 MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false) 565 MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false) 566 MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false) 567 MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false) 568 MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false) 570 MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false) 571 MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false) 572 MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false) 573 MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false) 574 MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false) 576 MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false) 577 MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false) 578 MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false) 579 MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false) 580 MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false) 582 MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false) 583 MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false) 584 MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false) 585 MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false) 586 MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false) 588 MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false) 589 MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false) 590 MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) 591 MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) 592 MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) 594 MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false) 595 MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false) 596 MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false) 598 MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) 599 MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false) 600 MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false) 601 MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false) 602 MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) 603 MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) 604 MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false) 606 MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) 607 MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) 608 MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false) 609 MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) 610 MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) 611 MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false) 612 MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false) 613 MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false) 614 MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false) 615 MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false) 617 INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false) 618 INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false) 619 INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false) 620 INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false) 621 INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false) 622 INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false) 623 INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false) 624 INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false) 625 INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false) 626 INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false) 627 INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false) 628 INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false) 629 INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false) 630 INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false) 631 INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false) 632 INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) 633 INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) 634 INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) 636 EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false) 637 EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false) 638 EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false) 639 EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false) 854 /* Four Transfer Controllers on DM365 */
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H A D | davinci.h | 3 * of the TI DM644x, DM355, DM365, and DM646x. 66 /* DM365 base addresses */ 92 /* DM365 function declarations */
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H A D | board-dm365-evm.c | 2 * TI DaVinci DM365 EVM board support 104 * NAND shipped with the Spectrum Digital DM365 EVM 264 * Further details are available at the DM365 ARM dm365evm_emac_configure() 287 * Details are available at the DM365 ARM dm365evm_emac_configure() 300 * Further details are available at the DM365 ARM dm365evm_mmc_configure() 374 .card_name = "DM365 EVM", 777 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
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/linux-4.1.27/include/media/davinci/ |
H A D | vpss.h | 33 VPSS_PGLPBK, /* for DM365 only */ 34 VPSS_CCDCPG /* for DM365 only */ 49 /* DM355/DM365 */ 62 /* DM365 only clocks */ 90 /* set sync polarity, only for DM365*/ 92 /* set the PG_FRAME_SIZE register, only for DM365 */
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/linux-4.1.27/drivers/media/platform/davinci/ |
H A D | vpss.c | 84 /* masks and shifts for DM365*/ 95 DM365, enumerator in enum:vpss_platform_type 152 /* For DM365 only */ isp5_read() 158 /* For DM365 only */ isp5_write() 420 oper_cfg.platform = DM365; vpss_probe() 436 if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) { vpss_probe() 451 } else if (oper_cfg.platform == DM365) { vpss_probe()
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H A D | vpbe_venc.c | 439 /* DM365 component HD mode */ venc_set_720p60_internal() 469 /* DM365 component HD mode */ venc_set_1080i30_internal() 509 /* for DM365 VPBE, there is DAC inside */ venc_s_dv_timings() 516 /* for DM365 VPBE, there is DAC inside */ venc_s_dv_timings()
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H A D | vpbe_osd_regs.h | 38 /* DM365 ISP5 system configuration */ 139 /* DM365 ISP5 bit definitions */
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H A D | isif.c | 20 * This driver is for configuring the ISIF IP available on DM365 or any other
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H A D | vpbe_osd.c | 644 * DM365: start address is 27-bit long address b26 - b23 are _osd_start_layer()
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H A D | vpbe_display.c | 1537 MODULE_DESCRIPTION("TI DM644x/DM355/DM365 VPBE Display controller");
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/linux-4.1.27/drivers/leds/ |
H A D | leds-versatile.c | 3 * Based on DaVinci's DM365 board code
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/linux-4.1.27/include/linux/platform_data/ |
H A D | davinci_asp.h | 101 MCBSP_CLKR = 0, /* as in DM365 */
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H A D | spi-davinci.h | 27 SPI_VERSION_1, /* For DM355/DM365/DM6467 */
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/linux-4.1.27/arch/arm/mach-davinci/include/mach/ |
H A D | psc.h | 84 /* DM365 */
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H A D | irqs.h | 206 /* DaVinci DM365-specific Interrupts */
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/linux-4.1.27/drivers/staging/media/davinci_vpfe/ |
H A D | vpfe_mc_capture.c | 54 * block such as IPIPE (on DM355/DM365 only). 61 * - Work with DM365 or DM355 or DM6446 CCDC to do Raw Bayer
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/linux-4.1.27/sound/soc/davinci/ |
H A D | davinci-evm.c | 283 .name = "DaVinci DM365 EVM",
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