| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| H A D | r300_cmdbuf.c | 75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); r300_emit_cliprects()
121 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); r300_emit_cliprects()
148 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_emit_cliprects()
152 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_emit_cliprects()
336 OUT_RING(CP_PACKET0(reg, sz - 1)); r300_emit_carefully_checked_packet0()
380 OUT_RING(CP_PACKET0(reg, sz - 1)); r300_emit_packet0()
411 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_emit_vpu()
413 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_emit_vpu()
415 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); r300_emit_vpu()
428 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); r300_emit_vpu()
455 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_emit_clear()
457 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_emit_clear()
812 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); r300_pacify()
817 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); r300_pacify()
822 OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0)); r300_pacify()
827 OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0)); r300_pacify()
831 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_pacify()
836 OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0)); r300_pacify()
838 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_pacify()
897 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); r300_cmd_wait()
955 OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) ); r300_scratch()
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| H A D | radeon_state.c | 458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); radeon_emit_clip_rect()
460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); radeon_emit_clip_rect()
490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); radeon_emit_state()
498 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); radeon_emit_state()
502 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); radeon_emit_state()
509 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); radeon_emit_state()
516 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); radeon_emit_state()
519 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); radeon_emit_state()
526 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); radeon_emit_state()
528 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); radeon_emit_state()
536 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); radeon_emit_state()
545 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); radeon_emit_state()
557 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); radeon_emit_state()
559 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); radeon_emit_state()
566 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); radeon_emit_state()
579 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); radeon_emit_state()
586 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); radeon_emit_state()
599 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); radeon_emit_state()
606 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); radeon_emit_state()
619 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); radeon_emit_state()
626 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); radeon_emit_state()
644 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); radeon_emit_state2()
790 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); radeon_clear_box()
918 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); radeon_cp_dispatch_clear()
1308 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); radeon_cp_dispatch_clear()
1408 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0)); radeon_cp_dispatch_swap()
1420 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1)); radeon_cp_dispatch_swap()
1429 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2)); radeon_cp_dispatch_swap()
1628 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); radeon_cp_dispatch_indirect()
1948 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); radeon_cp_dispatch_stipple()
2193 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); radeon_do_init_pageflip()
2196 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); radeon_do_init_pageflip()
2663 OUT_RING(CP_PACKET0(reg, (sz - 1))); radeon_emit_packets()
2680 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); radeon_emit_scalars()
2700 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); radeon_emit_scalars2()
2719 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); radeon_emit_vectors()
2743 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); radeon_emit_veclinear()
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| H A D | radeon_drv.h | 1914 #define CP_PACKET0( reg, n ) \ macro
1930 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1949 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1955 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1958 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1965 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1968 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1975 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1978 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1985 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1988 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
2025 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
2030 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
2035 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
2113 OUT_RING( CP_PACKET0( reg, 0 ) ); \
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| H A D | r300d.h | 31 #define CP_PACKET0 0x00000000 macro
60 #define PACKET0(reg, n) (CP_PACKET0 | \
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| H A D | rv515d.h | 174 #define CP_PACKET0 0x00000000 macro
200 #define PACKET0(reg, n) (CP_PACKET0 | \
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| H A D | r100d.h | 31 #define CP_PACKET0 0x00000000 macro
59 #define PACKET0(reg, n) (CP_PACKET0 | \
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| H A D | radeon_cp.c | 619 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1)); radeon_do_cp_start()
628 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); radeon_do_cp_start()
669 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); radeon_do_cp_stop()
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