458 	OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));  in radeon_emit_clip_rect()
460 	OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));  in radeon_emit_clip_rect()
490 		OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));  in radeon_emit_state()
498 		OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));  in radeon_emit_state()
502 		OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));  in radeon_emit_state()
509 		OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));  in radeon_emit_state()
516 		OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));  in radeon_emit_state()
519 		OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));  in radeon_emit_state()
526 		OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));  in radeon_emit_state()
528 		OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));  in radeon_emit_state()
536 		OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));  in radeon_emit_state()
545 		OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));  in radeon_emit_state()
557 		OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));  in radeon_emit_state()
559 		OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));  in radeon_emit_state()
566 		OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));  in radeon_emit_state()
579 		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));  in radeon_emit_state()
586 		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));  in radeon_emit_state()
599 		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));  in radeon_emit_state()
606 		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));  in radeon_emit_state()
619 		OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));  in radeon_emit_state()
626 		OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));  in radeon_emit_state()
644 		OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));  in radeon_emit_state2()
790 	OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));  in radeon_clear_box()
918 		OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));  in radeon_cp_dispatch_clear()
1308 		OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));  in radeon_cp_dispatch_clear()
1408 		OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));  in radeon_cp_dispatch_swap()
1420 		OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));  in radeon_cp_dispatch_swap()
1429 		OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));  in radeon_cp_dispatch_swap()
1628 		OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));  in radeon_cp_dispatch_indirect()
1948 	OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));  in radeon_cp_dispatch_stipple()
2193 	OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));  in radeon_do_init_pageflip()
2196 	OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));  in radeon_do_init_pageflip()
2663 	OUT_RING(CP_PACKET0(reg, (sz - 1)));  in radeon_emit_packets()
2680 	OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));  in radeon_emit_scalars()
2700 	OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));  in radeon_emit_scalars2()
2719 	OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));  in radeon_emit_vectors()
2743 	OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));  in radeon_emit_veclinear()