Searched refs:CLKC (Results 1 – 4 of 4) sorted by relevance
15 #define CLKC 2 macro136 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */ in rsnd_adg_set_convert_clk_gen2()212 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */ in rsnd_adg_set_convert_clk_gen1()310 [CLKC] = 0x3, in rsnd_adg_ssi_clk_try_start()371 [CLKC] = 0x4, in rsnd_adg_ssi_clk_init()427 adg->clk[CLKC] = devm_clk_get(dev, "clk_c"); in rsnd_adg_probe()
4 The kernel supports scaling of CLCK.CMODE, CLCK.CM and CLKC.P0 clock9 p0 -- current value of the P0 bit in CLKC register.10 cm -- current value of the CM bits in CLKC register.11 cmode -- current value of the CMODE bits in CLKC register.
158 # Set the clock mode (CLKC register) as required.159 # - At this time, also set the CLKC register P0 bit.339 # (6) Set the clock mode (CLKC register) as required.340 # - At this time, also set the CLKC register P0 bit.
140 # (12) Set '1' to the CLKC.SWEN bit. In that case, do not change141 # fields other than SWEN of the CLKC register.